A ΔΣ Modulator Automated Synthesis Tool for Wireless Standards

: This paper presents the prediction of single - bit discrete - time feed - forward Delta - Sigma (DT FF ΔΣ) modulators performance for wireless standards with the use of two methods. The presented work uses the MAPLE tool and a new design automation tool to estimate the performance of different DT FF ΔΣ modulators topologies intended for low power consumption systems. The proposed tool is based on synthesis algorithm, which takes advantage of analytical models of both FF ΔΣ modulator and operational transconductance amplifier (OTA) performance. By defining the required specifications, the proposed synthesis tool is capable to find the predictive performance of both the modulator topology and the required OTA building block for future process. A Graphical User Interface is programmed to easily present some designed circuits examples.


INTRODUCTION
Among the diversity of Delta-Sigma (ΔΣ) modulators architectures, feed-forward Delta-Sigma (FF ΔΣ) modulators have become the most used architectures to meet the requirements of wireless communication systems [1].In fact, it has recently become very popular to feedforward the input signal in wideband ΔΣ modulators, so that the integrators only process quantization errors, the advantage being that the actual signal is not distorted by operational amplifier and integrator nonlinearities [2].In addition, the benefits of these topologies are their abilities to achieve high resolutions with a decrease in power consumption [3].The trend of designing low power ΔΣ modulators using upcoming CMOS Nano-process has been growing rapidly in recent years [4].Designers usually require much time to select the best ΔΣ modulator architecture with the appropriate process node, to determine its performance and to acquire the desired operational transconductance amplifier (OTA) circuits.The time spent for designing is very long and needs a lot of experience.Thus, new tools for ΔΣ modulators are required for unskilled designers.
In front of the increasing complexity of ΔΣ modulators, several studies proposed many tools [5,6].Medeiro proposed a high-level specifications tool.His tool has used an equation-based approach at the modulator level and a simulation-based approach at the cell level.It has only supported single-loop ΔΣ modulators and the simulation has taken a lot of time [7].Tang and Doboli presented a topology-synthesis methodology which gives all possible topologies under various design considerations for single-loop single-bit ΔΣ modulators [8].However, the ΔΣ modulator topology performance is strongly affected by the non-idealities of building blocks, therefore, the implementation is even more difficult in nanometer CMOS technologies.For this reason, it is recommended to ameliorate or to present other ΔΣ modulators structures with high performances that satisfy the specifications of new standards.
Given the frequent use of submicron CMOS process for low power ΔΣ modulators design, the aim of this work is focused on the prediction of different structures of DT FF ΔΣ modulators performance with process scaling for various mobile telecommunications standards.
In this context, this paper proposes a novel helpful approach for the synthesis of low power FF ΔΣ modulators with Nanometric CMOS process.Some equations models linking the FF ΔΣ modulator performance to the design and the technological parameters are developed.Then, a Graphical User Interface (GUI) is programmed in which the user can get access to additional interfaces for different tasks.The next Section details the procedure of NanoCMOS ΔΣ modulators performance prediction including the modeling of ΔΣ modulator and OTA performance and the use of the MAPLE tool.The following Section presents the design automation approach and the proposed synthesis algorithm.Some design examples are provided afterwards in order to show the operation of the system.Finally, the conclusions drawn from this work and possible future works are presented.

PROCEDURE OF NANOCMOS FF ΔΣ MODULATORS PERFORMANCE PREDICTION
In this Section, a prediction flowchart is introduced to detail the different steps to acquire predictive FF ΔΣ modulators performance.As it can be seen from Fig. 1, firstly, we fix the specifications including the wireless standard, the CMOS process node, the power consumption and the FS.Secondly, by varying the order of the FF ΔΣ modulator, we opt for its architecture.Taking both design and technological parameters into consideration, some equations models related to FF ΔΣ modulator and OTA performance could be developed.Finally, the performance of FF ΔΣ modulators architectures and the required OTA circuit performance are predicted for future process.

Modelling of FF Δ Σ Modulator Performance
Currently, designers focus on DT FF ΔΣ modulators design for submicron process to meet the requirements of new wireless communications systems [9].Our objective consists of predicting the performance of several singlebits DT FF ΔΣ modulators structures namely the signal-tonoise ratio (SNR), the resolution (ENOB), the power consumption (Pmod) and the figure of merit (FOM) for wireless standards.To estimate this performance, the selected FF ΔΣ modulator architecture should be modelled accurately.When modelling, we suppose that the errors caused by non idealities affecting the analog building blocks are neglected.

Signal to Noise Ratio (SNR)
The SNR is the most used criterion to characterize the modulator performance.In fact, the SNR which represents the ratio between the input signal power (PS) and the quantization noise power (P Q ) is defined by the following equation: U max presents the maximum voltage of the signal applied to the modulator input.It is given by Eq. ( 2): OL and V ref represent respectively the overload and the reference voltage.The quantization noise power is given by the following relationship [10]: where Δ, F S and NTF are respectively the quantization step, the F S and the noise transfer function.P Q varies from one modulator architecture to another.If we use a L th -order ΔΣ modulator architecture where its NTF is in the form of (1 − z −1 ) L , Eq. ( 3) is approximately rewritten as follows: where L and OSR are respectively the order and the over sampling ratio.The quantization step Δ is given by: where V fs and B are the full scale voltage and the quantizer bits number.For a N-stage cascaded ΔΣ modulator architecture, the quantization noise power can be approximated to Eq. ( 6): with d 2N−3 being the digital coefficient of the N th -stage ΔΣ modulator.

Effective Number of Bits (ENOB)
The quantization levels number of a conversion system is defined by the effective number of bits (ENOB) or resolution.The resolution is expressed as [11]:

Power Consumption
Given the increasing number of both the portable equipment and the functional blocks integrated on the same chip, low power consumption of a ΔΣ modulator is an important property.In this work, we aim to design a modulator structure where the power consumption of the used comparator is very low.In [12], Feldman assumes that the power dissipated in a switched capacitor integrator is that which is required to charge and discharge the sampling capacitor CS.Then, the required power consumption of the modulator can be approximated to Eq. ( 8): ( ) V dd , C S and F S are respectively the supply voltage, the sampling capacitor and the F S .

Signal bandwidth (BS)
It is the frequency band on which the ΔΣ modulator may be used.It can be written in the following form [11]:

Figure of Merit (FOM)
The FOM compares the performance of various ΔΣ modulators.It is given by the following expression [13]: where BS is the signal bandwidth.

Modelling of OTA Performance
The most important block in the DT FF ΔΣ modulator structure is the OTA circuit which has a great impact on modulators performance.Thus, the designer should use a suitable OTA topology to realize robust ΔΣ modulators.In this work, we focus on finding a relationship between ΔΣ modulator and OTA performance.The main OTA performance which may directly affect the operation of ΔΣ modulator are the DC gain (Adc), the gain-bandwidth product (GBW) and the Slew Rate (SR).

DC Gain Requirement
The settling error at the output of the OTA circuit, resulting from the finite open loop DC gain A dc is approximately given by [14][15]: where β i is the feedback factor.
The OTA circuit will be used in a data converter with ENOB bits accuracy and it must amplify signals to within half least significant bits (LSB) of the ideal value [14].Therefore, the required OTA DC gain can be obtained to meet the accuracy requirement of the ADC circuit.It is given by the following expression: The minimum required DC open loop gain can be expressed as:

Gain-Bandwidth Product Requirement
For a single pole system, where the OTA settling requirement is ENOB bits, the output settles to ENOB in the sampling time period T S if [16]: where τ and T S are respectively the settling time constant and the T S .Eq. ( 15) describes the settling time constant where C f is the integration capacitor and β i is the feedback factor which is detailed in Eq. ( 16) [17].
It leads to the following requirement for the GBW using Eq. ( 14) and Eq. ( 15): The minimum required OTA GBW is given by Eq. ( 18):

Slew Rate Requirement
It is assumed that the OTA integrator is a first order system, the maximum variation of the circuit response is given by the following expression [18]: g 1 and V in, max are respectively the integrator gain and the maximum input voltage.Regarding the settling error, in the case of: there is no Slew Rate limitation and the integrator output will be linearly settled.From Eq. ( 20), the minimum required OTA SR is obtained: Using Eq. ( 14), the minimum required Slew Rate is rewritten as: where V in, max = V ref •OL.The V ref voltage value is chosen very close to the OTA circuit output swing in order to increase the ΣΔ modulator input swing.Referring to Eq. ( 13), Eq. ( 18) and Eq. ( 22), it can be noted that the OTA performance depends on the ΔΣ modulator performance (ENOB, OL, analog coefficient), the selected F S and the CMOS process node (V dd ).The prediction of the required OTA circuit performance for each provided ΔΣ modulator architecture can be an important key to success.Technical Gazette 25, Suppl.2(2018), 487-494

Prediction of FF Δ Σ Modulator Performance through Maple Tool
The presented work aims to estimate different FF ΔΣ modulators structures used for low and high-speed applications.The prediction is limited to single-bit FF ΔΣ modulator topology whose quantizer is a single-bit one (B = 1).Therefore, according to the literature, we fix some standards summarized in Tab. 1 [19][20][21].During this phase, to project some FF ΔΣ modulators performance predictions for low power systems, we choose a decreasing power consumption estimated less than 1mW and a variable F S using future CMOS process (Tab.2).Tab. 2 presents supply voltages predicted for each process node using the Bisquare Weights method described in [22].Aiming at the implementation in Nanometer CMOS technologies, many efforts have been devoted to choose the ΔΣ topology suitable for the ΔΣ ADC design.A detailed analysis has been presented in [23], leading to optimized loop coefficients and performance for various FF ΔΣ modulators architectures.Optimized loop coefficients have been developed from behavioral simulations to stabilize high performance ΔΣ modulator.The loop coefficients represent the analog coefficients (ai), the feedforward coefficients (c j ) and the digital coefficients (e k ).The adopted prediction method is based on the following steps given by Fig. 2. In fact, we start with introducing some constants such as the signal bandwidth (BS), the F S , the supply voltage (V dd ), the analog and digital coefficients (a i and e k ), the order (L), the OverLoad (OL), the quantizer bits number (B) and the estimated value of the FF ΔΣ modulator power consumption (P mod ), taking Tab. 1 and Tab. 2 into consideration.After that, the equations models related to FF ΔΣ modulator performance (equations from Eq. (1) to Eq. ( 10)) are used to present the trend of different singlebit FF ΔΣ modulators performance scaling from 350nm to 22nm process nodes.As an example, we are looking for designing the 2-2 cascaded FF ΔΣ modulator for DVB-H, WLAN and WIMAX standards.Thus, the loop coefficients introduced in the prediction method are taken from Tab. 3 [23].
The analog and the digital coefficients are respectively given by Eq. ( 23) and Eq. ( 24): . 1   show respectively the SNR, the ENOB, the power consumption and the FOM scaling of the 2-2 cascaded FF ΔΣ modulator for DVB-H, WLAN and WIMAX standards.Fig. 3 shows that the SNR has been scaled from 67 dB to 37 dB when process node is scaling for DVB-H standard.From this figure, it has been remarked that the decrease of SNR is due to the FS reduction when scaling the device sizes.We notice a tradeoff between a higher bandwidth and a lower SNR.In Fig. 4, due to the SNR reduction, the value of the resolution decreases from 11bits.Fig. 6 shows that the FOM remains less than 0.26 pJ/conversion when the channel length becomes shorter.Regarding the required human effort for the ΔΣ modulator performance prediction, the time spent is very large.This prompted us to propose a novel method that permits a fast ΔΣ modulator automatic design.

AUTOMATED SYNTHESIS TOOL
Our objective is to design different ΔΣ modulators topologies using future process without losing time.For this, we propose a new approach which is based on an algorithm to synthesize low power DT FF ΔΣ modulators.

Proposed Synthesis Algorithm
This algorithm is developed with "ActionScript 3" language while considering steps listed in Fig. 7. First, we start by setting the wireless standard and the FS variations ranges listed in Tab. 1 and 2.Then, we choose power consumption less than a maximum default value of 1 mW.Next, we indicate the modulator order "L" variations ranges.In this case, we choose to predict single loop (SL) 2 nd order modulators (L = 2), 2-1 and 2-1-1 cascaded modulators (L = 3, 4).By using the Eq. ( 8), all possible values of power consumption are generated followed by a verification of preliminary conditions.This condition consists of checking whether the calculated power consumption of the modulator is less than the maximum power value P max which is initially selected.After that, the generation of possible power consumption values yields to possible generated supply voltages values followed by a verification of preliminary conditions.These conditions are imposed to ensure that the generated supply voltage is equal to the process node supply voltage given by 2. If these conditions are fulfilled, the supply voltage is saved and it is a candidate for the following steps, otherwise we do another choice.For each power consumption and process node, a FF ΔΣ modulator type is then defined.The computation of its performance according to their developed equations models (Eq.(1) to Eq. ( 10)) yields to projected predictions.The characterization of OTA circuit depending on ΔΣ modulator performance is used to calculate the required performance for each designed modulator structure and find the best adopted OTA architecture (Eq.( 13)-Eq.( 18)-Eq.( 22)).

FF Δ Σ Modulators Design Examples via Programming GUI
Designing a good User Interface encourages an easy and natural interaction between a user and a system.A graphical application tool is a software program that graphically provides a user with a set of commands and icons with which he can graphically manipulate to generate or modify a design product in a work space area.
The proposed tool provides a wide design environment for designing different FF ΔΣ modulators.In fact, a GUI is programmed with "ActionScript 3" language where the user can easily include the data and display the results.In this subsection, we illustrate the design automation approach with some examples.Tab. 4 lists some required input parameters that the user should define at the beginning.In these examples, we are looking for designing FF ΔΣ modulators structures projected for UMTS, WLAN and WIMAX standards.From Fig. 8, it is seen that the user of the tool can select which standard to take into account during the prediction and set values for their lower and upper bounds.After defining the design specification, the user waits for possible FF ΔΣ modulators architectures.In fact, the algorithm looks for candidate architectures with the given specifications.Fig. 9 displays various FF ΔΣ modulators topologies predicted for WIMAX standard.For each designed topology, the ΔΣ modulator performance is then computed.Among the availability of many structures, Tab. 5 presents predicted performance of the candidates architectures solutions for each given standard.Fig. 10 presents the corresponding required OTA performance for the provided 2-1 cascaded FF ΔΣ modulator given by Fig. 9. From Tab. 5, it can be concluded that the larger the value of modulator order, the higher the SNR is.In fact, the highest SNR value is achieved for 2-1-1 cascaded configuration.One of the important features of the design automation tool is the ability to find the best OTA structure for the provided FF ΔΣ modulators (Tab.6).From Tab. 6, it is clear that for a given set of performance specifications, more than one topology is often feasible.In addition, the required type of OTA circuit can be provided for each calculated OTA performance.

CONCLUSION AND FUTURE EXTENSIONS
This paper proposed a novel helpful approach for the synthesis of low power FF ΔΣ modulators with process scaling for various mobile telecommunications standards.The procedure of NanoCMOS ΔΣ modulators performance prediction and the use of the MAPLE tool have been presented.Automation of predicting ΔΣ modulators performance is a very challenging and time-consuming task.Thus, a novel automated synthesis tool, which includes FF ΔΣ modulators performance synthesis and OTA performance modeling, has been proposed.A new algorithm has been suggested to provide the prediction of single-bit FF ΔΣ modulators performance for wireless standards.The presented approach proves that the design effort is reduced with the assistance of an automated tool.Some design examples have been presented through a programmed Graphical User Interface.This GUI was designed allowing convenient and fast access to all functionality.These examples showed that the proposed tool may be used to generate different FF ΔΣ modulators structures types for desired specifications.It has shown that higher SNR can be reached for high order low power modulator topology.This tool reveals the link between both the design and the technological parameters and structures performance to provide an insight to the ΔΣ modulator design problem and lightens up the design environment for the designer.The outcome of the synthesis tool is not only the projected ΔΣ modulator performance, but also the required building block specifications.The Technical Gazette 25, Suppl.2(2018), 487-494 proposed tool is beneficial in predicting the FF ΔΣ modulators performance and the required OTA specifications.It can further shorten the design time for inexperienced designers.The automated synthesis tool can be used to predict the performance of a wide variety of analog circuits and topologies.
In the future, to raise the efficiency of design automation systems, developed analytical models incorporating circuit non-idealities will be introduced further in the proposed synthesis tool.In addition, an extension of this research might be the prediction of transistor sizes of analog circuits for upcoming process using a Nano-CMOS device-level tool to increase its usability

Figure 1
Figure 1 Prediction flowchart of FF ΔΣ modulators performance

Figure 3
Figure 3The scaling of SNR Figs.3, 4, 5 and 6 show respectively the SNR, the ENOB, the power consumption and the FOM scaling of the 2-2 cascaded FF ΔΣ modulator for DVB-H, WLAN and WIMAX standards.Fig.3shows that the SNR has been scaled from 67 dB to 37 dB when process node is scaling for DVB-H standard.From this figure, it has been remarked that the decrease of SNR is due to the FS reduction when scaling the device sizes.We notice a tradeoff between a higher bandwidth and a lower SNR.In Fig.4, due to the SNR reduction, the value of the resolution decreases from 11bits.Fig.6shows that the FOM remains less than 0.26 pJ/conversion when the channel length becomes shorter.Regarding the required human effort for the ΔΣ modulator performance prediction, the time spent is very large.This prompted us to propose a novel method that permits a fast ΔΣ modulator automatic design.

Figure 8
Figure 8 GUI: specifications design Due to the higher constraint on DC gain, the tool selects an OTA gain-boosted for 2-1-1 cascaded configuration for UMTS standard and a telescopic OTA for the rest.

Figure 9 Figure 10
Figure 9 GUI: predicted performance of different modulators architectures for WIMAX standard

Table 1
ADC specifications for mobile telecommunications standards Prediction method of FF ΔΣ modulators performance through maple tool

Table 3
Optimized loop coefficients and performance for the single-bit cascaded 2-2 FF ΔΣ modulator Loop coefficients and performance (a 1 , a 2 , a 3 , a 4 , c 1 , c 2 , c 3 , c 4 , e 1 , e Proposed algorithm for FF ΔΣ modulators automatic design

Table 4
Input parameters to the design examples

Table 5
Designed single bit FF ΔΣ modulators structures projected for different standards

Table 6
Required OTA performance for the provided FF ΔΣ modulators

Table 6
Required OTA performance for the provided FF ΔΣ modulators