Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

INTRODUCTION Huge number of FPGA applications during the last three decades have been influenced many scientists and engineers to develop a more and more fast and more capacity of Field Programmable Gate Arrays (FPGA) chips. However, the optimal speed and minimum area of a circuit when it is implemented on an FPGA chip may not be achieved if the HDL (Hardware Description Language) codes do not describe the nets properly.
In terms of area, most of the researchers have put their research focus on developing the more efficient basic FPGA blocks such as adder, multiplier and other basic circuits. Some important developments on adder circuit have been patented during last three decades [1]- [5].
Saha et al proposed various integer arithmetic algorithms [6]. Simultaneous design of multiplier-free filters and hardware implementation in FPGA had been proposed by Shajaan et al [7]. Some other recent developments on area efficiency of FPGA implementation had been reported; efficient FIR for high speed FPGA implementation [8], enhancing area efficiency of hard circuit using shadow clusters [9], a method of reducing area based on fullyparallel stochastic LDPC decoding [10], efficient convolution implementation [11], area efficient for logic element and efficient area for floating point [12].
For a huge and complex arithmetic calculation, it is better to perform all arithmetic operations in the integer format. However, it is required special care in decrypting the nets on the codes. Thus the efficient area using embedding block of optimal circuits may be obtained. The paper presents a novel method for area efficiency of arithmetic operations using IEEE (Numeric_std 1076.3) package library.
The rest of this work is organized as follows. In section II describes about FPGA programming. The following section explains the style of VHDL programming for area efficiency in arithmetic operations. Implementation results and discussions are covered in section IV. Calculation and possible future works are presented in section V. the VHDL codes of the designed circuit are listed at the end of this article.
II. FPGA PROGRAMMING To configure the behavior of the FPGA, the designer provides an HDL or a schematic design. The HDL form is more suitable to work with large structures since it is possible to just specify them numerically rather than having to draw every piece by hand. Still, the schematic entry can allow for easier visualization of a design.
There are also many ways of how to program an FPGA chips through HDL. For area efficiency and faster speed Abstract²A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits..

Keywords.Optimasi area, FPGA, VHDL, Verilog, paket VHDL.
purposes, most of scientists and engineers prefer VHDL and Verilog languages. These codes provide more flexibility and capability for programmers to program the specific circuits and able to maintain (control) detail nets connections between basic gates [13]- [16].

A. Verilog
The most common used HDL language in the design, verification and implementation of digital chips at level of register transfer is Verilog. This language is also used for verification of analog and mixed signal circuits [13].
Verilog was invented by Phil Moorby and Prabhu Goel in 1983. This language is the first modern Hardware Description Language (HDL). Initially, the language was intended to explain (describe) and allow to run simulation. Later on, it was also supported for performing synthesis.
The code of a two simple flip-flop in Verilog as follows: The package provides two ways of converting numbers between integer and standard logic vector either through signed or unsigned format. For certain purposes in arithmetic operations, the operations may also be performed in signed or unsigned formats only. Table 1 shows conversion commands among integer, signed and unsigned format. Meanwhile, Table 2 views list of instructions for converting among unsigned, signed and standard logic vector format. By combining the commands in those tables, we are able to perform direct conversion between standard logic vector and integer format [17].
III. VHDL STYLE FOR AREA EFFICIENCY IN ARITHMETIC OPERATIONS For illustrations, consider multi stages block circuit that shown in Fig. 1. The circuit operation may be explained by (1), (2) and (3). All word lengths size that used to connect all blocks is similar 6 bits.   Fig. 2.
The circuit in the Fig. 2 occupies less area when it is implemented into chips. This is due to the circuit in the Fig.1 has similar and bigger word lengths. Therefore, it is required to design the efficient VHDL code that minimized area use. It can be done by assigning suitable and might be different word lengths block interconnects.
A design in VHDL consists at least an entity which describes the interface and an architecture which contains the actual implementation. Moreover, most circuit designs import library modules. Some circuit designs may also contain multiple architectures and configurations [14].
Any input and output data or numbers in VHDL are considered as bit, standard logic or standard logic vector format. Bit format provides less choice 0 or 1. However, standard logic format extend the choice up to 9 logic values (U, X, 0, 1, Z, W, H, L, -). A parallel data may be represented using standard logic vector format [15].
Inside the architecture, the values (data) might be converted to other formats such as signed, unsigned or integer. To simplify the code for a complex arithmetic operation, we prefer integer format for processing most of the arithmetic operations. For instance, a number (A) represented in 4-bit standard logic vector, may be converted into integer (B) and Vice Versa as follows: B <= to_integer(signed(A)) A <= std_logic_vector(to_signed(B,4)) All variables and signals that are defined in integer format inside architecture, may or may not be limited (specific range). For example, signal Z : integer; variable S : integer range -16 to 15; IV. IMPLEMENTATIONS AND DISCUSSIONS In order to show the performance of the proposed VHDL coding style, we choose two circuits; 4-bit addition and 8bit counter. Both of the circuits have been synthesized using Xilinx ISE 9.2i. Fig. 3 shows a circuit for adding two values A and B controlled by clock. Both input numbers are represented in 4 bits (standard logic vector format). Meanwhile, clock may be represented using bit or standard logic format (the code listed in the Program 1).

A. Four-bit Addition
Both input values are stored separately in two buffers (4 bit). Each times clock goes high, both of the stored values are adding up. The addition result is saved into a 5-bit buffer this is due to additional 1 bit because of addition process of two values. Fig. 4  It can be seen that the second synthesis result require smaller register (5-bit) compare than the first one which is 32-bit register. This is the maximum register size available since the software was run under 32-bit windows.

B. Eight-bit Counter
An 8-bit Counter has been designed and synthesized using the proposed VHDL coding style (the codes are listed in the Program 2). Figs. 5 and 6 show behavior simulation results of 8-bit Counter circuit. Output is viewed in unsigned number format.
Synthesis results below views report macro statistic and device utilization summary of the circuit with no limitation