In the process of VLSI design, ECO (Engineering Change Order) may occur at any design phase. When ECO happens after the netlist is generated and optimized, designers may like to modify the netlist directly. This is because if ECO is performed in the high-level description, the netlist should be resynthesized and the result may be significantly different from the original one, even if the modification in the high-level description is small. As the result, the efforts spent on optimization so far may become useless. When the netlist is modified directly, the C description should be revised accordingly. This paper proposes a method to reconstruct a C description from the revised netlist. In the proposed method, designers need to provide a template represented in C, which has some vacant (blanked) places and is created from the original C description. The vacant places are automatically synthesized using a CEGIS-based method (Counter Example Guided Inductive Synthesis). Using a set of use-cases, our method tries to find the correct expressions for the vacant places so that the entire description becomes functionally equivalent to the given modified netlist, by only simulating the netlist. Experimental results show that the proposed method can reconstruct C descriptions successfully within practical time for several examples including the one having around 9,000 lines of executable statements. Moreover, the proposed method can be applied to equivalence checking between a netlist and a C description, as shown by our experimental results.