IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Analog Circuits and Related SoC Integration Technologies
A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network
Lechang LIUTakayasu SAKURAIMakoto TAKAMIYA
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2012 Volume E95.C Issue 6 Pages 1035-1041

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Abstract

A 315MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11µW power consumption at 315MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4µW with 7.9dB noise figure and 20.5dB gain in state-of-the-art designs.

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© 2012 The Institute of Electronics, Information and Communication Engineers
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