An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast

Tatsuya KOBAYASHI; Keita YASUTOMI; Naoki TAKADA; Shoji KAWAHITO

doi:10.1587/transele.2022CTP0003

Special Section on Analog Circuits and Their Application Technologies

An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast

Tatsuya KOBAYASHI, Keita YASUTOMI, Naoki TAKADA, Shoji KAWAHITO

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Keywords: SOI detector, lock-in pixel, parasitic light sensitivity, modulation contrast

JOURNAL FREE ACCESS

2023 Volume E106.C Issue 10 Pages 538-545

DOI https://doi.org/10.1587/transele.2022CTP0003

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Abstract

This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.

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