In this letter, a new read circuit with self-adjusted column pulse width is proposed for low-power applications of resistive memories. In the conventional read circuit, its column pulse width is determined by the worst-case value of the cell resistance variations thereby the pulse width being longer than required when the resistance variations are not in the worst case. In this paper, to alleviate power loss due to this long column pulse width, the column pulse width is self-adjusted according to the resistance variations thus unnecessary power loss being able to be reduced significantly. The power consumption during the read is expected to be less by 28.6% than the conventional circuit when the SET resistance is its mean value as large as 2kΩ . The Monte Carlo simulation also shows that the power consumption of the proposed circuit is reduced by 25% in average than the conventional.