LETTER
Floating-point operation based reconfigurable architecture for radar processing
2016 Volume 13 Issue 21 Pages 20160893
Details
2016 Volume 13 Issue 21 Pages 20160893
To meet the increasing demand of large bandwidth and high throughput in modern radar system, we proposed a reconfigurable application specified processor (RASP) according to the feature of radar digital signal processing applications. RASP is a reconfigurable coprocessor based on hierarchical floating-point operation elements that is capable of executing a set of fundamental subalgorithms, take these subalgorithms as the minimal task node can improve the computational efficiency tremendously. The experimental results show that the processor performance exceeds TI state-of-the-art DSP by 1.05× to 3.22×. Our reconfigurable processor can be integrated into customizable radar systems, it was fabricated with TMSC 40 nm CMOS process and has an area of 19.2 mm2.
