IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A high speed modulo (2n − 2p + 1) multiplier design
Hai YanLei LiQyu Zhang
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JOURNAL FREE ACCESS

2015 Volume 12 Issue 23 Pages 20150870

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Abstract

In this express, an optimized architecture for modulo (2n − 2p + 1) multipliers is proposed. Compared with the state-of-art, synthesized results demonstrate that the proposed multipliers can achieve an average delay savings of about 11.8%. With the increase of n, the average delay savings also increases remarkably.

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© 2015 by The Institute of Electronics, Information and Communication Engineers
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