Electronically and Independently Controllable Quadrature Sinusoidal Oscillator with Low Output Impedances

. This work presents the quadrature sinusoidal oscillator using two Voltage Differencing-Differential Input Buffered Amplifiers (VD-DIBAs), two resistors, and two capacitors. The VD-DIBA is an electronically controllable active building block with high input and low output impedances that can con-nect to other circuits directly without the buffers. With these distinguished features, the VD-DIBA is employed in this design. The proposed oscillator can produce two sine waves with a phase shift of 90 degrees. Over the entire tuning frequency range, the magnitude of the quadrature output voltages is constant. The proposed oscillator is independently adjustable in terms of frequency and oscillation condition. Moreover, the frequency of oscillation can be electronically and linearly adjusted by the bias currents. The condition of oscillation is adjustable by resistors, R 1 and R 2 . The performances of the proposed quadrature oscillator are tested through the PSpice simulation and the experiment. In the simulation, the VD-DIBA is built from the 0.18 µ m Taiwan Semiconductor Manufactur-ing Company (TSMC) CMOS process with ± 0 . 9 V supply voltages. In the experiment, the VD-DIBA is implemented using the commercial ICs, LM13700, and AD830 with ± 5 V supply voltages. The simulated To-tal Harmonic Distortion (THD) values of the output voltages, V o 1 and V o 2 at f 0 = 1 . 03 MHz are 1.63 % and 1.81 % , respectively. The experimental THD values of the output voltages, V o 1 and V o 2 at f 0 = 536 . 6 kHz, are 1.43 % and 1.00 % , respectively.


Introduction
A sinusoidal oscillator that provides two output signals with a 90 • phase difference is known as a "quadrature sinusoidal oscillator". It is a fundamental circuit that is important in electrical engineering systems. Many applications need the quadrature sinusoidal oscillator as the sub-circuit, such as electrical measuring systems, medical equipment, audio-visual system, signal processing system, communication, and telecommunication [1] and [2].
Numerous researchers have attempted to design a sinusoidal oscillator using several kinds of active building blocks. The use of active building blocks in the circuit design is convenient and flexible when it is compared with using the BJT or CMOS transistors. Moreover, using the active building block in the circuit design requires a few passive elements which are easy to analyse for finding out the equation of the circuit parameters. Literature [3] and [4] now recognizes the benefits, applications, and utility of a newly introduced active Tab. 1: The comparison of the sinusoidal oscillators using VD-DIBA.
Herein, the review of sinusoidal oscillators [13], [14], [15], [16], [17], [18] using VD-DIBA as the active building block is given. The simple sinusoidal oscillator with a single VD-DIBA is proposed in [14] and [15]. The oscillators in [13], [14], [15], [16] and [17] use grounded capacitors which is attractive from an integration point of view. The proposed oscillators in [15] and [16], are adjustable independently of frequency and oscillation frequency. The frequency of the oscillator proposed in [13] and [16] is linearly and electronically tuned. However, there are some drawbacks existing from those oscillators. The oscillators in [13], [14], [15] and [17] cannot provide the quadrature output waveform. The output voltage nodes of the quadrature oscillators in [18] are not low in impedance. The proposed oscillators in [13], [14], [17] and [18] are not adjustable independently of frequency and oscillation frequency. The frequency of the oscillators in [14], [15], [17] and [18] is not linearly and electronically controlled. Table 1 shows the comparison of the sinusoidal oscillators using VD-DIBA.
In this study, our attention is focused on the design of the quadrature sinusoidal oscillator employing two VD-DIBAs, with two resistors and two capacitors. The circuit can generate sinusoidal signals with a 90-degree phase difference. The conditions and frequency can be adjusted independently, and especially the frequency of the wave can be adjusted linearly and electronically. The workability of the circuit is verified by PSpice simulation and experiment in a laboratory using VD-DIBAs constructed from the 0.18 µm TSMC CMOS process (simulation) and the commercial IC LM13700 and AD830 (experiment).

2.
Theories and Principle

VD-DIBA
The VD-DIBA's circuit symbol is shown in Fig. 1 which consists of two parts, the transconductance amplifier and the unity gain voltage differencing amplifier. At the first part, the input voltage terminals V + and V − and the output current terminal Z have high impedance. The transconductance, g m of the first part is adjustable by controlling the bias current, I B . In the second part, the input voltage terminals, V and Z are high impedance. While, the output voltage terminal, W is low impedance. The equivalent schematic of VD-DIBA is illustrated in Fig. 2. The input and output relationship of VD-DIBA is shown in Eq. (1). The internal construction of VD-DIBA realized from the CMOS transistors is depicted in Fig. 3. It is found that the transconductance amplifier is constructed from the MOS transistors, M 1 -M 8 , and the unity gain voltage differencing amplifier, which is modified from the Differential Difference Current Conveyor (DDCC) [19], is constructed from the MOS transistors, M 9 -M 18 . With this structure, the g m is electronically adjusted by the bias current (I B ) as depicted in Eq. (2).
where µ n is the electron mobility, C ox is the oxide capacitance, and W/L is the aspect ratio of MOS M 1 and M 2 channel width and length. The VD-DIBA implemented from the commercially available ICs is cost-effective and easier to implement. In this design, the VD-DIBA is implemented from the commercially available ICs, LM13700 by Texas Instruments [20], and AD830 by Analog Devices [21] as shown in Fig. 4. For LM13700, the gm for this VD-DIBA structure is given in Eq. (3).

Proposed Circuit
In this paper, a VD-DIBA-based voltage-mode firstorder all-pass filter [8] and a lossless integrator are utilized to construct the quadrature sinusoidal oscillator circuit. As shown in Fig. 5, both a first-order all-pass filter and a lossless integrator are realized using VD-DIBA as the active building block. The first-order all-pass filter consists of the components VD-DIBA1, C 1 , and R 1 , R 2 . The lossless integrator is constructed from VD-DIBA2 and C 2 , which is grounded. Circuit structure in Fig. 5 reveals that the output voltage nodes V o1 and V o2 are at the low impedance output voltage nodes W 1 and W 2 , respectively. Therefore, they can be connected directly to other circuits without the need for a buffer circuit. The characteristic equation of the proposed quadrature sinusoidal oscillator shown in Fig. 5 is given in Eq. (4).
If g m = g m1 = g m2 and C = C 1 = C 2 , the Frequency of Oscillation (FO) of the second order characteristic equation is given as: Also, the Condition of Oscillation (CO) of the second-order characteristic equation is given by: From Eq. (5) and Eq. (6), the FO and CO of the proposed quadrature oscillator can be independently adjusted. Additionally, the frequency of oscillation can be linearly and electronically controlled. For amplitude stabilization, the resistor R 2 can be easily realized from a photoresistor. This device is a part of the 3WK16341 (optocoupler with photoresistor) [23]. More details of the amplitude stabilization using 3WK16341 can be seen in [24] and [25]. The circuit in Fig. 5 gives the voltage ratio of V o2 and V o1 as shown in Eq. (7).
It is found from Eq. (7) that the phase difference of output voltages V o2 and V o1 is 90 • when phase of V o2 leads phase of V o1 . At the frequency of oscillation (ω = ω 0 ), the magnitude voltage ratio of V o2 and V o1 in Eq. (7) becomes Substituting the frequency of oscillation, ω 0 depicted in Eq. (5) into Eq. (8), the magnitude ratio of V o2 and V o1 is unity as shown in Eq. (9).
Equation (9) revealed that if C 1 = C 2 and the frequency of oscillation is tuned by simultaneously changing g m1 and g m2 (I B1 = I B2 ), the amplitude of the output voltages, V o2 and V o1 is equal over the tuning frequency range.

Non-Ideal Study
In this section, the effect of the non-ideal properties of VD-DIBA on the oscillator performance is considered. The non-ideal properties of VD-DIBA can be expressed in Eq. (10).
In Eq. (10), β z is the voltage gain error from z to w terminal and the β v is the voltage gain error from v to w terminal. Considering those voltage gain errors, the characteristic equation of the proposed oscillator is shown in Eq. (11).
If g m = g m1 = g m2 and C = C 1 = C 2 , the frequency of oscillation of the second-order characteristic equation in Eq. (11) is given by: .
Also, the condition of oscillation of the second-order characteristic equation in Eq. (11) is given by: It is found that the voltage gain errors affect both the oscillation frequency and condition frequency. Fig. 6: Parasitic elements in the proposed circuit.
The influence of the parasitic elements in VD-DIBAs on the performance of the proposed quadrature oscillator is also studied. Figure 6 shows the involvement of parasitic elements in the proposed circuit. For easy analysis of the proposed circuit, the parallel of the parasitic element is considered as the admittance, where the admittances, Y 1 , Y V 1 , Y 2+ , and Y 2 appeared in Fig. 6 are defined as follows: where If R 1 and R 2 are much less than R −1 , R Z1 , R V 1 , R +2 R Z2 , and the operational frequency of the proposed quadrature oscillator is much less than 1/[2πC V 1 (R 1 //R 2 )], 1/[2πC 1 (R W 2 //R 1 )] and 1/[2πC + 2(R W 1 //R 2 )], the characteristic equation of the proposed quadrature oscillator is given by: where C * 2 = C 2 + C Z2 . The frequency and condition of oscillation of the second-order characteristic equation in Eq. (15) are given by: and It is found that the parasitic element in VD-DIBA affects the frequency and condition of oscillation as well as the operating limitation at high frequency. It is also noted that R 1 and R 2 should be low for getting a higher frequency of operation.

Simulated Results
PSPICE is used to be the tool for simulating the workability of the proposed quadrature sinusoidal oscillator shown in Fig. 5. The simulation is carried out by using the VD-DIBA constructed from the CMOS transistors as shown in Fig. 3. The CMOS model parameters are offered by 0.18 µm TSMC technology in level 7 [22]. The power supply is ±0.  Fig. 6 is the sinusoidal output waveform in the initial state until steady state. It is found that the sinusoidal signal has entered a steady state after t ≈ 200 µs. The quadrature sinewave at a steady state is shown in Fig. 7. It is found that the amplitudes of sinusoidal output voltages, V o1 and V o2 are 162.01 mV p−p and 160.17 mV p−p , respectively. The simulated magnitude ratio of V o2 and V o1 is 0.988 (1.2 % error) which is closed to unity as depicted in Eq. (9). The phase of the sinusoidal output voltage V o2 leads the phase of the sinusoidal output voltage V o1 by 89.41 • (0.65 % error) which is consistent with the theoretical analysis as depicted in Eq. (7). The simulated f 0 is 1.03 MHz (2.64 % error). The THDs of the sinusoidal output voltages, V o1 and V o2 are 1.63 % and 1.81 %, respectively. Figure 9 shows the output spectrum of the sinusoidal output voltages V o1 and V o2 .  The plot of theoretical and simulated f 0 against the bias current is shown in Fig. 10. In this simulation, the bias current (I B1 = I B2 = I B ) is varied from 10 µA to 80 µA. With these variations of the bias current, the simulated f 0 is adjusted from 0.71 MHz to 1.72 MHz which is consistent with the theoretical analysis as depicted in Eq. (8). This simulation result confirms that the frequency of oscillation is electronically controlled. This advantage feature is easily controlled by the microcomputer or microcontroller for modern circuit applications. Figure 11 shows the simulated V o2 − V o1 phase relationship against the frequency of oscillation. The phase difference swings from 86.75 • (at f 0 = 1.2 MHz) to 91.41 • (at f 0 = 0.86 MHz) which is closed to the theoretical expectation (90 • ) as depicted in Eq. (7).  Figure 12 depicts the amplitude of the quadrature sinusoidal output voltages V o1 and V o2 versus the simulated oscillation frequency. Over the tuning frequency range, the amplitude of the sinusoidal output voltage, V o1 , is found to be close to the amplitude of the sinusoidal output voltage, V o2 , as determined by Eq. (9). Due to the non-ideal features of VD-DIBA, the amplitude of the sinusoidal output voltage, V o2 , is somewhat less than the amplitude of the sinusoidal output voltage, V o1 . Figure 13 depicts the percent THD of the quadrature sinusoidal waveforms V o1 and V o2 versus the oscillation frequency. THD varies from 1.
It is found that the amplitudes of the quadrature sinusoidal output voltages, V o1 and V o2 , are 54.90 mV p−p and 56.76 mV p−p , respectively. The experimental magnitude ratio of the sinusoidal output voltages V o2 and V o1 is 1.034 (3.4 % error) which is closed to unity as depicted in Eq. (9). In this experiment, the phase of the sinusoidal output voltage V o2 leads the phase of the sinusoidal output voltage V o1 by 92.27 • (2.52 % error) which is consistent with the theoretical analysis as depicted in Eq. (7). The experimental f 0 is 536.6 kHz (2.11 % error). The THDs of the sinusoidal output voltages, V o1 and V o2 obtained from the experiment are 1.43 % (−36.875 dB) and 1.00 % (−40 dB), respectively. Fig. 15 shows the measured output spectrum of the sinusoidal output voltages V o1 and V o2 .
The plot of theoretical and experimental f 0 against the bias current is shown in Fig. 16. In this exper-   The amplitude of the quadrature sinusoidal waveforms, V o1 and V o2 against the frequency of oscillation obtained from the experiment is plotted in Fig. 18. It is found that the amplitude of the sinusoidal output voltage, V o1 is closed to the amplitude of the sinusoidal output voltage, V o2 over the tuning frequency range as analyzed in Eq. (9). However, the amplitude of the sinusoidal output voltage, V o1 is a little less than the amplitude of the sinusoidal output voltage, V o2 due to the non-ideal properties of VD-DIBA. Figure 19 shows the experimental result of the percent of THD of the quadrature sinusoidal waveforms V o1 and V o2 against the frequency of oscillation. The percent of THD for the sinusoidal output voltage, V o1 swings from 0.931 %

Conclusion
In this research, a voltage-mode quadrature sinusoidal oscillator is proposed. The proposed quadrature sinusoidal oscillator requires two VD-DIBAs, two resistors, and two capacitors. It provides two sinusoidal voltage waveforms, V o1 and V o2 with a 90-degree phase difference. The V o1 and V o2 outputs are accessible from nodes with low impedance, allowing them to be connected to other voltage-mode circuits without the need for voltage buffers. By setting capacitors C 1 and C 2 to the same value and simultaneously tuning bias currents I B1 and I B2 , the frequency of oscillation can be controlled electronically and independently from the oscillation condition. Additionally, the condition of oscillation is modified by resistors R 1 and R 2 without affecting oscillation frequency. The amplitudes of V o1 and V o2 are equal over the tuning frequency range. The proposed oscillator is simulated via PSpice program using CMOS model parameters offered by 0.18 µs TSMC technology in level 7 with ±0.9 V. The simulation revealed that the magnitude ratio of V o2 and V o1 is 0.988 (1.2 % error). The phase of V o2 leads the phase of V o1 by 89.41 • (0.65 % error). The simulated f 0 is 1.03 MHz (2.64 % error). The THDs of V o1 and V o2 obtained from the simulation are 1.63 % and 1.81 %, respectively.
The simulated power consumption is 1.37 mW. In addition, the proposed oscillator is experimentally tested using VD-DIBA constructed from the commercial ICs with ±5 V. The experiment revealed that the magnitude ratio of V o2 and V o1 is 1.034 (3.4 % error). The phase of V o2 leads the phase of V o1 by 92.27 • (2.52 % error). The experimental f 0 is 536.6 kHz (2.11 % error). The THDs of V o1 and V o2 obtained from the experiment are 1.43 % and 1.00 %, respectively. The experimental power consumption is 265.7 mW.