Single-Phase PLL Based on an Adaptive Notch Filter

Single-Phase Phase-Locked Loops (PLL) have become a crucial component of grid-tied power converters. PLL accuracy and fast response are important for control and protection purposes, especially in the presence of voltage harmonics and frequency variations. In this paper, a new PLL structure based on an Adaptive Notch Filter (ANF) is presented. This ANF, which generates the orthogonal system of the PLL, is implemented with an All-Pass Filter (APF) having inherent advantages, such as low sensitivity to coefficient rounding when implemented in fixed-point microprocessors and easy implementation in a Digital Signal Processing (DSP). Both simulation with MATLAB/Simulink, and experimental results on a fixedpoint DSP, are presented and analyzed to evaluate the performance of the introduced PLL and to support the theoretical development. A set of comparative simulations between the proposed PLL and a some singlephase PLL described in the literature are conducted to validate the method.


Introduction
Distributed Energy Resources (DERs) have become increasingly widespread in recent years. This has increased grid connection requirements of renewable energy sources e.g. wind or solar. The control of power electronics front ends has been improved in order to meet new standards and grid codes [1] and [2]. In order to meet the new requirements, researches have focused on synchronization and control techniques of renewable energy powered grid-connected converters [3]. The grid synchronization is based on the detection of the voltage phase angle at the Point of Common Coupling (PCC). Synchronization must be accurate and fast, even in the presence of grid disturbances such as line harmonics, voltage sags/swell/loss, frequency variations and phase jumps [4].
Among DERs, single-phase ones have only recently gained interest [5], and the PLL topology has emerged as de facto phase detection structure. Information regarding the condition of the grid is scarcer in singlephase systems than in three-phase systems [6]. Hence, more advanced methods should be considered to create an orthogonal voltage system which makes it possible to obtain the voltage phase angle at the PCC. Apart from single-phase DERs, such as photovoltaic inverters [7] and energy storage devices, all single-phase power electronic front ends, like Uninterruptible Power Supplies (UPS) or regenerative drives, need a PLL in their control loop [8] and [9]. With the voltage phase angle at the PCC, the active and reactive current references of the inner current loop are calculated so that the power factor of the device has the design value. Moreover, the PLL should provide instantaneous Root Mean Square (RMS) voltage, and it would be very interesting if it could provide grid frequency, too. Both magnitudes are usually needed for both active and passive anti-islanding detection algorithms in photovoltaic inverters [10] or in the droop method for converter parallel operation [11].
General structure of a single-phase PLL for grid synchronization is presented in [12]. The most important component is the orthogonal system generator, and the main difference among all PLLs proposed in the literature lies precisely in this element. The orthogonal system can be generated in several ways [13]. The methods commonly found in the technical literature use the transport delay block [14], Hilbert transformation, Moving Average Filter (MAF) with variable sampling time, such as in [15] or constant sample time [16], and inverse Park transformation as in [17] and [18]. However, these techniques have one or more of the following shortcomings: frequency dependence, high complexity, non-linearity, and poor or no noise filtering capability.
A single-phase PLL structure based on a Second Order Generalized Integrator (SOGI) which overcomes all the aforementioned drawbacks was presented in [19] and [20], together with a filtering delay due to its resonance at the fundamental frequency. Rodriguez et al. [21] and [22] presented a three-phase PLL based on a Dual Second Order Generalized Integrator (DSOGI). The SOGI structure has also been applied to other aspects of power electronic control [23], mainly to the current control loop [24] and [25], harmonic detection [26] and even in active anti-islanding methods [27]. However, as already stated in [20] and later in [24], since the SOGI structure was designed in the continuous time, its discrete implementation has amplitude ripples and phase delays different from the quadrature. Moreover, it requires a lot of resources to implement in a fixed-point DSP or Field-Programmable Gate Array (FPGA) due to its limited accuracy and sensitivity to coefficient rounding.
Continuous time notch filters and their adaptive version ANF, have long been used as frequency detectors [28], especially in single-phase systems [29]. Only recently have they started being used as orthogonal system generators, especially in the continuous time domain [30]. Besides having the same drawbacks as the SOGI structure, ANF does not provide any unity gain orthogonal system generator but one whose gain depends on the 3 dB band pass of the filter. This drawback, which is common to both the continuous and discrete time versions of ANF, does not allow the use of traditional ANF as PLL despite being a good candidate.
In this paper, a new single-phase PLL based on a second order Normalized Digital APF is presented. An APF is like a versatile DSP building block with the best characteristics for notch filter [31] and adaptive notch filter applications. In order to provide a unity gain orthogonal system, the authors propose a normalization method which provides two orthogonal signals (the in-phase and the quadrature one) with the same amplitude of the input, just as traditional PLL implementations do, but without the above drawbacks. This paper is organized as follows. In Sec. 2. , an overview of the whole system is given. Section 3. describes the APF and its application to the ANF. The normalization of the ANF is described in Sec. 4. while in Sec. 5. some implementation issues are presented. Next, simulation and experimental results are provided in Sec. 4. Section 7. presents a comparison study with others PLLs.

2.
Overview of Single-Phase PLL According to Fig. 1, Single-Phase PLLs are mainly composed of two blocks: a first block which generates an orthogonal system (with one of its components in phase and a second component lagging π/2 the input single-phase voltage) and a second block which computes the angle and voltage magnitude from the orthogonal system [32]. The most important role is played by the orthogonal system generator, where the main differences lie between all PLLs in the literature. The rest of the blocks are the same as in most PLL implementations. A second order ANF based on a discrete APF seems a good candidate as the orthogonal system generator due to its low sensitivity to coefficient rounding and loss-less internal structure, very suitable for adaptive algorithms [33]. Furthermore, the computational cost of implementation is quite low, especially in the statespace representation.
In order to allow extraction of the voltage amplitude by the second block, the transfer function from the magnitude of the input voltage to both output orthogonal signals of the ANF must have either a unity magnitude or a known constant gain. This is not true of traditional ANF, although they have a gain different from unity which depends, among other factors, on the 3 dB band pass of the filter. This important drawback of traditional ANF is the main reason why they have not been used in single PLL so far. The next sections describe a normalization of the ANF which meets the above requirements while generating a unity gain orthogonal system (that is, it generates an orthonormal system).

APF: DSP Building Block
Digital APF was analyzed in detail in [31], and hence they are briefly described for the sake of completeness. The frequency response of an APF has unity magnitude at all frequencies: Transfer functions of APF have all poles and zeroes as conjugate reciprocal pairs. If the transfer function is constrained to be a real function, then the numerator polynomial is obtained from the denominator by reversing the order of the coefficients. Among all implementation structures for discrete filters, the normalized lattice structure (Fig. 2) is the most useful for real coefficient, second order filters as all internal nodes are automatically scaled (coefficients are less than or equal to 1), which is a suitable characteristic for fixed-point DSP implementation [31] and [34]. In Fig. 2, u(n) is the input signal and y f (n) is the output filtered signal, A(n) is the filter transfer functions and x 1 (n) and x 2 (n) are the two orthogonal components. A second order APF transfer function can then be expressed as: Considering that all internal nodes are less than or equal to 1, we can make the following changes to Eq. (2), k 1 = sin θ 1 and k 2 = sin θ 2 , where θ 1 and θ 2 can be further expressed as: where ω 0 is the so called notch frequency, and BW = 2πB · f −1 s , is the so called band width of the filter, with B being the band pass and f s the sampling frequency. Finally, we obtain: The lattice notch filter, expressed as Eq. (5), provides a decoupling between the notch frequency ω 0 and the 3 dB band pass of the filter. Decoupling is very useful in adaptive filters where it is necessary to adapt the notch or band pass frequency. This characteristic will be used later for obtaining an ANF [35]. Apart from having unity magnitude at all frequencies, the real coefficient, second order APF has zero phase shift for ω < ω 0 and π shift for ω = ω 0 whereas the rest have a phase shift of 2π.
As mentioned before, the APF is a versatile DSP building block. Furthermore, due to the π shift for ω = ω 0 , it is easy to construct a Digital Notch Filter (DNF) and its complementary one (a band-pass filter) from the APF presented before (Fig. 3).

Bandpass Output
Notch Output Fig. 3: Generation of a band-pass (G(z)) and notch (F(z)) filter based on an All-pass filter.
Notch and band-pass filter transfer functions can be obtained as: For our interest, only the transfer function of F(z) is given: The Notch Filter based on the APF of Eq. (6) and Eq. (7), has the particularity of generating an orthogonal system. Figure 2, where the lattice implementation of the APF is depicted, shows the two internal nodes x 1 and x 2 . The transfer functions for both nodes are as follows: X 1 (z) = cos θ 1 cos θ 2 z −1 1 + sin θ 1 (1 + sin θ 2 )z −1 + sin θ 2 z −2 , (10) Although these two internal nodes represent an orthogonal system (x 1 is lagging 0.5 π the input sinusoidal voltage and x 2 is in phase with the input sinusoidal voltage), their amplitudes are not directly related to the magnitude of the input voltage because the gain of their transfer functions at the notch frequency is different from unity. For x 1 and x 2 to be an appropriate orthogonal system generator for a single PLL, the transfer functions must be previously normalized; that is, they must have a unity gain at the notch frequency. The following section presents a normalized version of Eq. (10) and Eq. (12).
Since the main purpose of a PLL is to extract the input voltage angle, it is also highly desirable to obtain other characteristics of the input voltage such as the instantaneous RMS voltage and frequency. In most cases, it is not only desirable but also necessary, as in solar Photovoltaic (PV) inverters implementing the anti-islanding algorithm [27], where a quick and precise estimate of the magnitude and main frequency is needed. Although the DNF in the previous section could extract the input voltage angle, if either the magnitude or the frequency of the input voltage must be extracted too, then an adaptation algorithm must be implemented. Figure 4, shows the structure of the proposed APF-PLL, with the three main blocks: • the orthonormal generator based on an APF, • the adaptation algorithm, • last block, which extracts the input voltage angle and magnitude.

Adaptation
Algorithm APF Lattice This adaptation algorithm must make ω 0 (or by Eq. (3), its associated variable θ 1 ) converge towards the mains pulsation ω e . In [33] and [36], Regalia proposed a stable and efficient lattice algorithm for adaptive Infinite Impulse Response (IIR) filtering but the adaptation performance depended on the amplitude of the signal. In [37], a similar algorithm is presented which improves the performance in the presence of amplitude variation: where A is the amplitude of the signal, and , µ, are positive parameters which determine the speed of adaptation, and e(n) is the error signal between the input and the output of the filter.

ANF Normalization
In order to obtain a unity gain of the transfer functions for the orthogonal system Eq. (10) and Eq. (12), first the steady-state gain at the notch frequency must be calculated. This gain is obtained by substituting z = e jθ (where θ is the utility phase of the input signal) in both transfer functions and obtaining the absolute value of the result. Then, we obtain: where M and N are, respectively: N = sin θ 1 sin θ + sin θ 1 sin θ sin θ 2 + sin 2θ.
Finally, if the frequency of the input signal is the same as the notch frequency, ensuring that is θ = θ 1 , which is ensured by the adaptive algorithm in Sec. 3. , then the gains reduce to: Dividing Eq. (10) and Eq. (12) by the gain Eq. (17), both transfer functions will have a unity gain: Figure 5, shows the structure of the APF once normalized and Fig. 6 shows the bode plot for these two transfer functions before and after normalization.
The state-space equation can be rewritten in a more compact form as:   x 1 (n + 1) x 2 (n + 1) y(n)   =   sin θ 1 cos θ 1 sin θ 2 cos θ 1 cos θ 2 cos θ 1 sin θ 1 sin θ 2 sin θ 1 cos θ 2 0 cos θ 2 sin θ 2 and once normalized, we obtain: In order to calculate the updates of the two signals of the orthonormal system generator, it is sufficient to calculate the two first rows of Eq. (23). Finally, it is important to note that no special care must be taken to address a possible DC component of the input voltage signal although, unlike with the other traditional PLLs [30], the notch filtering of the APF-PLL prevents the effect of a biased input sinusoidal voltage on the orthogonal system generator. The following section shows the validity of these statements.

Simulation and Experimental Results
In order to prove the validity of the theoretical results in the previous sections, Matlab/Simulink simulation and experimental results are given. The set of perturbations used, namely those relevant to Institute of Electrical and Electronics Engineers (IEEE) Std. 929-2000 [38], IEEE Recommended Practice for Utility Interface of Photovoltaic (PV) Systems, was the same in both cases.
The variables in all the simulation and experimental results are: the single-phase voltage to the APF-PLL, the two orthogonal signals generated by the APF-PLL, the fundamental vs. estimated phase angle, and finally, depending on the perturbation, the input vs. output frequency or the input vs. output voltage amplitude. The tuning of the APF-PLL was kept constant throughout the simulations, with a notch frequency of 50 Hz, a pass band of 28 Hz, a sampling frequency of 20 kHz, = 0.0001 and µ = 0.0001. The set of perturbations includes: • Frequency variation: the input to the PLL consisting of a sinusoid of frequency 50 Hz. At time 0.2 s, the frequency is changed with a step to 52 Hz. As a reference value, IEEE Std. 929-2000 states that the frequency variation rate should be no faster than 0.5 Hz·s −1 , and the delay time for the inverter to cease to energize the utility line should be no longer tan six cycles. Moreover, the frequency measurement error should be ≤ 0.1 Hz. Figure 7(a), shows the estimated phase angle versus reference phase angle and estimated frequency versus reference frequency. The simulation results show that, after a short transient, the APF-PLL algorithm estimates accurately the new frequency in less than 3 cycles, fulfilling the above standard.
• Voltage sag: the input to the APF-PLL consisting of a sinusoid of 50 Hz and amplitude of 1.0 p.u. At time 0.2 s, a voltage sag of 25 % is suddenly applied to the PLL. As a reference value, IEEE Std. 929-2000 states that in a voltage sag of 50 % or less, the maximum trip time of the PV inverter should be less than 6 cycles. Figure 7(b), shows the instantaneous RMS value versus reference value of the amplitude voltage. The simulation results show that, after a short transient, the APF-PLL algorithm estimates accurately the new amplitude in less than 2 cycles, fulfilling the above standard.
• Harmonic distortion: IEEE Std. 929-2000 states that PV inverters must withstand a certain amount of waveform distortion without specifying any value. The APF-PLL algorithm is subjected to a voltage distortion in Fig. 7(c) consisting of 25 % of the third harmonic and 15 % of the fifth harmonic. Again, no impact on the phase angle or frequency estimation is detected.
The APF-PLL presented in this paper, has been implemented in a DSP from Texas Instruments (TMS320F2812), which has a 32 bit fixed-point Central Processing Unit (CPU) with 150 Mips. This CPU is provided with a hardware multiplier, and so it can realize a multiplication and posterior addition in one single clock cycle; this is an important feature for the execution of state-space equations such as that in Eq. (23). Apart from that, a look-up table for sine and cosine calculations is located in the boot Read Only Memory (ROM) of the device, making the trigonometric calculations to be performed efficiently (the sine and cosine function for an angle, with an accuracy of 30 bits, can be executed in 60 clock cycles). The set-up consisted in a board with the aforementioned DSP, along with a 12 bit 4-channels Digital to Analog Converter (DAC) interfaced with the DSP through the SPI bus; and connected to this DAC, a Picoscope oscilloscope which plots are depicted in Fig. 8.
The inputs to the APF-PLL algorithm were the same as in simulation. These inputs were internally generated, through mathematical equations, so that no Analog to Digital Converter (ADC) was necessary, and in Ref.
Fe est. (a) Step change in the input frequency.   this way, avoiding any non-desired noise which could mask the output results.
In Fig. 8, there is complete consistency between the simulation outputs and those resulting from the implementation in a DSP. The APF-PLL, in all three cases implemented in the DSP, accurately estimates the x 2 (n) output as an input signal image, without disturbances and determines the phase angle with great precision. In Fig. 8(a), it is shown that the implementation of the APF-PLL, estimates the new frequency of 52 Hz, in less than 3 cycles, just as was done in the simulation of Fig. 7(a). In Fig. 8(b), the APF-PLL estimates, as in the simulation, the new amplitude in less than 2 cycles of the input signal. And in Fig. 8(c), the frequency achieved is identical to that of the simulation exhibited in Fig. 7(c), presenting the same variations, which are not very pronounced, being less than 0.2 Hz.
The experimental results, carried out in a DSP, have confirmed the simulation results, showing a fully satisfactory behavior of the proposed PLL in both transient and steady-state. In particular, the APF-PLL presents a considerable robustness against input signals variations and distortions; moreover, the steady-state errors on phase angle and on frequency are reduced to negligible values.

Comparative Study
We carried out a comparative study, by simulation, with other PLLs, the most representative ones: the Amplitude Adaptive Notch Filter (AANF) [37], SOGI [20], [24] and [27] and Park-PLL [17]. This comparison has been made regarding the estimation of the frequency and amplitude of the grid voltage under abnormal conditions.
The set of perturbations used are similar to the ones of the previous section, including a frequency jump from 50 Hz to 51 Hz; a voltage sag from 1.5 p.u. to 1.0 p.u.; a phase-jump of 40 degrees; and the addition of a 25 % of the third harmonic and 15 % of the fifth harmonic. The sampling frequency is kept constant to 20 kHz.
The dynamic response of the four PLLs under +1 Hz frequency jump scenario is displayed in Fig. 9(a). It can be obtained that the AANF-PLL and APF-PLL shows the fast dynamic response of near 2 cycles, and do not produce frequency overshoot. Further, the AANF-PLL and APF-PLL have no oscillation after the frequency jump, which offers the good performance with frequency immunity, and may be the best choice under this situation among the four PLLs. The SOGI also shows a fast, but 3 cycles dynamic response with a small oscillation.   As is exhibited in Fig. 9(c), when the grid voltage undergoes a phase angle jump of +40 degrees, the AANF-PLL, SOGI and APF-PLL have a similar dynamic re-sponse, with a tracking time of about 3 cycles. The Park-PLL does not perform well, which takes more 5 cycles to reach the steady-state conditions and with pronounced oscillations. Figure 9(d) offers the simulation results when the grid voltage undergoes harmonics scenario. The harmonics have almost no influence on SOGI and APF-PLL thanks to their filter properties. But the ANNF-PLL and Park-PLL show noticeable oscillations greater than 1 Hz and 4 Hz, respectively.
In Fig. 9, the comparative results are presented. One can observe that the APF-PLL, the AANF-PLL (being a closed continuous time implementation of the APF-PLL) and the SOGI exhibit similar performance in all the four simulations. It is possible to verify that the APF-PLL, in addition to providing good work with low frequency pass, amplitude change, phase pass and good harmonic rejection, has the notable advantage of its simplicity.

Conclusion
A new orthogonal system based on an APF with Lattice structure has been proposed. This structure was presented and its discrete algorithm has been detailed. The Lattice APF generates an identical signal and another signal orthogonal to the input fundamental signal, without disturbances since the orthogonal system is filtered without delay by the same structure due to resonance at the fundamental frequency. This proposed orthogonal system, according to its characteristics and behavior, is ideal to be used as a single-phase PLL.
A single PLL based on an ANF is presented and behavior and implementation issues are analyzed in detail. The APF-PLL, has shown the ability to generate an orthogonal system from a single phase signal, with unity gain, which does not depend on the 3 dB pass-band of the filter and does not depend on the frequency as it is adaptive to it, maintaining high linearity and great filtering power. Despite its simple design, it uses few resources to implement in a fixed-point DSP, it requires only 6 multiplications plus accumulations, the APF-PLL provides great precision and low sensitivity to coefficient rounding (due to its internal structure) while exhibiting good response to frequency variations, voltage sags and harmonic distortion. The APF-PLL does not present considerable amplitude ripples and phase delays for the generated quadrature signal. These results have been confirmed by simulations and an experimental setup.