Degradation Analysis of DC-Link Aluminium Electrolytic Capacitors Operating in PWM Power Converters

The most common failure mode of aluminium electrolytic capacitor is the so-called wear out fault. It is caused by the high core temperature of the capacitor. Therefore, life cycle calculations generally use temperature data to estimate degradation level. Core temperature-based life cycle calculations can consider different current loads on capacitors. The calculation method uses scaling factors for different ripple current waveforms. However, it is not observed that temperature only is responsible for aging, but current waveform also influences the level of degradation. Therefore, sinusoidal and PWM-loaded capacitor tests were performed under the same temperature conditions. The results show that the pore distribution of aluminium anode foil has changed during the test. The pore diameter reduces and it leads to an increase in the ESR value and decrease in the capacitance, electrolyte amount and weight. Comparative results show that the PWM-loaded capacitor is more degraded than the capacitor loaded by sinusoidal test current.


Introduction
Aluminium electrolytic capacitors have been used almost in every power electronic system and application, such as Power Factor Correction (PFC) circuits, power supplies, PWM inverters or other switch-mode converters, because they have relatively high capacitance and low cost. The capacitor as an energy storage element is used as a voltage level compensator between input and output power levels to decrease the ripple of the DC-side voltage level.
The common faults in electrolytic capacitors during long-term usage or misapplication are wear-out faults [1], [2], [3], [4], [5], [6], [7], [20], [21] and [22] due to the vaporization of electrolyte caused by high core temperature. Inside the capacitor, there are continuous hydrolysis and oxide-layer forming mechanisms due to current flow through the anode foil (Fig. 1). The aluminium anode foil is oxidized by the oxygen from the water content of the electrolyte. The thicken oxide layer of the anode foil, the reducing electrolyte and the increasing hydrogen gas formation are the different appearances of the degradation.
The occurrence of degradation can be delayed and its level can be reduced if the operating temperature and the heat generated by the ripple current are lowered. The capacitor core temperature (T C ) is determined [8] by Eq. (1): where T A denotes the ambient temperature, I C,rms symbolizes the capacitor RMS current, R ESR denotes the equivalent serial resistance and R th denotes the thermal resistance between the capacitor can and the environment. Decrease in the inner temperature of capacitor by 10 • C in the rated operating temperature doubles the capacitor lifespan. The R ESR is a construction dependent parameter, which contains the inner resistance of the conductive components (dielectric losses and ohmic resistance of raw materials, electrolyte, terminals and connections). This is a relatively small resistance but still not negligible. Beside the ripple current, these resistances are responsible for the temperature increase in the core. Reliability and lifetime of the capacitor are mainly influenced by the ripple current [22], [23] and [24].
The calculation of core temperature can be scaled by correction factors to be valid for different ripple current waveforms [18] and [19]. Lifecycle calculations consider modified core temperatures by scaling factors for different ripple current waveforms. However, it is not revealed how life cycle varies at the same core temperatures when the capacitor is loaded by different ripple current. In this study, we analysed capacitor degra-dation caused by different ripple current waveforms at the same core temperatures.

Measurement Environment
For comparative analysis, different capacitors have been loaded by the standard sinusoidal current and PWM load.
During Endurance test with sinusoidal current, the capacitor current is sinusoidal. The ambient temperature is the recommended maximum operating temperature of the tested capacitor, usually 85 or 105 • C depending on its construction. The applied voltage is constant during the entire test duration and both the voltage and temperature are the rated values.
None of the standardized test procedures use highfrequency square-wave voltage to load the capacitor, therefore, a switch-mode power converter has been developed to ensure the PWM load to the analysed capacitor.
For degradation tests under PWM operation, a Two-Quadrant Chopper has been used, which contains the examined capacitor as can be seen in Fig. 2. The rated voltage of the capacitor meets the supply voltage of the converter. The converter contains an inductor (L) as output, which loads the capacitor (C). Two switches ensure the PWM voltage operation of the circuit. The elements of the test circuit had to be appropriately chosen for the proper measurements. The initial parameters were the following: C R = 4700 µF, U R = 400 V, ESR = 23 mΩ, Z = 28 mΩ, d = 76.9 mm, l = 105.7 mm; I AC,R = 13.8 A.
The specifications of the circuit were the following: f s = 10 kHz, T = 10 µs; the operating current and ripple: I op = 27.3 A, ∆I op = 2.7 A, and the operating current of the capacitor was calculated from I AC,R at U T = 400 V. The signal generator is based on SG3524 IC, which can generate accurate square waveform with variable duty cycle. The IGBT modules (SEMIKRON SKM 195GB126D) were driven by HCPL-3120 IGBT gate drive optocoupler circuits, which provides +15/ − 5 V signals. In order to minimize the losses, the inductor resistance (R L ) must be as small as possible, hence the value R L = 1 Ω has been chosen. It can be seen that in contrast to low resistance, relatively high power dissipation occurs.
The specified ripple current can be ensured by calculating the duty cycle (Eq. (2)) and the inductivity of the coil (Eq. (3)) as the following: The environment was verified based on SPICE circuit simulation of the model and the realized equipment was validated by test measurement. The circuit can generate the needed current stress for capacitor testing.

Test and Measurement Results
The 48 capacitors have been chosen from the rated voltage and capacitance domain of 400 V and 560 µF, respectively. The tested capacitors were grouped into four sets (Lot A -Lot D) based on their part numbers. Each group contains 12 capacitors, 6 for standard test, and 6 for PWM load test. The operating leakage current (I OLC ) was measured before the test procedure in order to verify the same initial conditions for all the tested capacitor pairs. The measurement was performed on 105 • C (the maximum operating ambient temperature of the capacitors) in a heating chamber. As can be seen in Tab. 1, the currents converge to the same values. Consequently, the conditions of the oxide layers were similar.
The capacitors were tested with both the standard equipment to perform sinusoidal tests and the developed test bench to perform PWM tests. The allowed maximum ratings (current and voltage level) for the alternating current tests were calculated according to the catalogue data of capacitors.
When capacitors were tested with PWM load, it was necessary to obtain the needed load current by Eq. (4), which is equivalent to the current applied in standard test. Capacitor ESR and power (P ) are known as a result of standard procedures: The determined core temperature for all the tests was 109 • C in order to ensure identical test conditions for all capacitors and to avoid different capacitor degradation and electrolyte vaporization caused by different core temperatures. During test procedures, the core temperatures of the capacitors were measured with a K type thermocouple, which was inserted into the capacitor. Based on the measured core temperature, the duty cycle of the PWM voltage signal was adjusted to maintain 109 • C.
The weight and electrical parameters of the capacitors (C, ESR, Z) were measured at the beginning of the test and in every 250 hours. The 10 kHz PWM voltage signal test resulted in more intensive aging than the standard sinusoidal endurance test: higher rate of capacitance reduction, weight loss and ESR increase were noticed. The weight loss indicates the evaporation of the electrolyte, while the change of the capacitance and ESR identify the structural, chemical and volumetric transformation of the anode, cathode and the electrolyte. The capacitance values decrease that can be explained by the reduction of conducting plates (the charge storing capacity of anode foil is less) and/or distance increase between them.
After the alternating current tests, the OLC measurements were performed. The values of steady-state OLCs were categorized in Tab. 1 for all tested capacitors. The OLC measurements of Lot B can be seen in   The spikes in the current waveforms can be explained by the deformed spatial structure of the oxide layer. When analysing the current waveform after 10 kHz test, it can be concluded that spikes are more relevant. Lower leakage current level can be observed in steady-state because of the thickened oxide layer of anode. Since the oxide layer went through a more significant deformation, the OLC has less steady-state value when the capacitor was tested with 10 kHz PWM signal instead of 50 Hz sine wave.
Both the capacitance and OLC reduction imply anode foil structural change. Therefore, the anode foils were investigated with structural analysis. The morphology of the anode foil surface was investigated with a scanning electron microscope. As can be seen in Fig. 3, there are no significant differences between the results, hence the pore size distribution was examined in order to find the reason for the capacitance and OLC reduction.
The results were obtained from the pore size distribution and the specific surface area examinations. Micro-and macroporosity, as well as specific surface area, were measured by mercury intrusion and nitrogen adsorption porosimeters, after eight hours vacuum treatment on 125 • C.
The change of the specific surface area was determined by nitrogen adsorption and the pore size distribution was used for characterization of the degrada- tion of the anode surface. The differential logarithmic pore volume functions in the range of 10-10000 nm have a maximum in the interval of 1000-2000 nm pore diameters. This maximal (Fig. 5) value is shifted to a smaller (600-700 nm) pore size in the case of the capacitor tested on 10 kHz PWM voltage signal. It means that the pits diameter of the foil narrowed during the high-frequency test.

Conclusions
The general problem with the electrolytic capacitor is the electrolyte vaporization during operation. Core temperature is an important property of the tests because it influences the level of the degradation. It is also affected by ambient temperature and load current. The capacitors are loaded by dynamically changing current in modern switched power electronics applications. The standard validation test methods work with sinusoidal load current only. During tests, square-wave voltage was applied (10 kHz PWM) on the tested capacitor beside the standard sinusoidal voltage (50 Hz). The general electrical parameters of capacitor were analysed. These values show that the PWM current cause more severe degradation than sinusoidal load current. The ESR values are increased, while the capacitance and weight decreased more than in the case of the standard sinusoidal endurance test. The reduced capacitance and lower leakage current level imply the change of anode foil oxide layer.
In order to analyse the structural change of the anode material, micro-and macroporosity, as well as specific surface area, were measured by mercury porosimeter. The pore size distribution showed that the PWM voltage based current load decreased the pore diameter of the capacitor anode foil. It initiated an oxide layer formation, which consumes the electrolyte. Therefore, the electrolyte transformation is accelerated which leads to faster aging and shorten the lifetime.
The analyses showed that the introduction of a new type of standard test, namely testing the degradation under PWM load is worth to estimate the life span of capacitors in PWM power converters.