A Class of Differentiator-Based Multifunction Biquad Filters Using OTRAs

This paper presents Signal Flow Graph (SFG) approach-based realization of Single Input Multiple Output (SIMO) filter topologies. A differentiator is placed as basic building block. A total of sixteen variants are derived from the proposed differentiatorbased SFG. The Operational Trans-Resistance Amplifier (OTRA), an active block having low parasitics at input terminals, is used to validate the proposed methodology. All the derived filter structures use three OTRAs, six resistors and two capacitors. The filter performance parameters can be adjusted independently. The functional verification of the proposed method is done via SPICE simulations using 0.18 μm CMOS technology parameters from MOSIS.

The paper is arranged in five sections. Section 2. includes the discussion on the proposed SFG, followed by a brief review of OTRA and basic signal processing blocks designed using OTRA. The OTRA-based SIMO filter topologies are also included in the same section subsequently. The non-ideality analysis is given in Sec. 3. , followed by simulation results in Sec. 4. The paper is finally concluded in Sec. 5.

The Proposed SFG
The proposed differentiator-based SFG, which uses two differentiators in forward path, is depicted in Fig. 1. The coefficients k i (i ∈ {1, 2, 3, 4}) may assume value 1 and −1. Four different SFGs can be generated from  It may be noted that the SFG in Fig. 1 uses an inverting differentiator, followed by a non-inverting differentiator. Alternate SFGs can be derived by placing • a non-inverting differentiator followed by an inverting differentiator, • two non-inverting differentiators, or • two inverting differentiators.
The resulting SFGs are depicted in Fig. 3.

The OTRA
The OTRA is an active block with two low-impedance input terminals and a low-impedance output terminal. The circuit symbol of OTRA is given in Fig. 5 and its terminals are characterized by matrix of Eq. (1): where R m is trans-resistance gain of OTRA. The value of R m is ideally infinity; therefore, OTRA is generally used in negative feedback configuration.  A close inspection of SFGs in Fig. 2 and Fig. 4 reveals that the circuit realization would require voltage addition-subtraction followed by amplifier (inverting / non-inverting), and differentiators (inverting / non-inverting).
The OTRA-based realization of voltage addition/subtraction is shown in Fig. 6. It uses five resistors and one OTRA. By equating the currents of inverting and non-inverting terminals, the output of the circuit from Fig. 6 is obtained as: Exchanging Fig. 6 yields the following relation: It may be noted that Eq. (3) is inverting form of Eq. (2). By choosing the values of resistances appropriately, the desired addition-subtraction can be performed. Equation (2) provides non-inverting output, whereas Eq. (3) gives an inverting output.
The OTRA-based circuits of inverting and noninverting differentiators are given in Fig. 7 and their respective outputs are given by:

OTRA-Based Realization of SFGs
The OTRA-based realization of SFGs can be obtained by using the basic blocks from Fig. 6 and Fig. 7.
The corresponding circuit realizations of SFGs from Fig. 2(a), Fig. 2(b), Fig. 2(c) and Fig. 2(d) are depicted respectively in Fig. 8(a), Fig. 8(b), Fig. 8(c) and Fig. 8(d). It may be noted that the realizations from Fig. 8(a) and Fig. 8(b) are same as those given in Fig. 8(c) and Fig. 8(d) respectively, since their corresponding k 1 k 2 product terms are the same. The transfer functions of the topology in Fig. 8(a) are obtained as: where The transfer functions of the topology in Fig. 8(b) are computed as: It may be noted that V 1 , V 2 and V 3 respectively represent low pass, band pass and high pass responses. All the transfer functions at different nodes represented by Eq. (6) and Eq. (8) are characterized by following pole frequency (ω 0 ), bandwidth ( ω0 Q ) and quality factor (Q): It is clear from Eq. (9), Eq. (10) and Eq. (11) that both bandwidth and quality factor can be adjusted independently by varying R 5 without modifying the pole frequency. The pole frequency may be varied by changing R i and C i (i = 1, 2) and quality factor may be kept constant by assuming R 3 = R 4 = R 5 and R1 R2 = C2 C1 . Further, the gain of the filter responses can be changed by varying the value of k.
The OTRA-based realizations of the SFGs listed in Fig. 4 are also obtained and omitted for the sake of brevity. The transfer functions are similar to the one given in Eq. (6), Eq. (7) and Eq. (8).

The Non-Ideality Analysis
The response of the filter may deviate due to nonideality of OTRA. Ideally, the trans-resistance gain R m is assumed to approach infinity. However, in practice, R m is a frequency-dependent finite value. Considering a single-pole model for trans-resistance gain, R m (s) can be expressed as: where R 0 is low-frequency trans-resistance gain. For high-frequency applications, the trans-resistance gain R m (s) is approximated as: where Taking this effect into account, the transfer functions in Fig. 8(a) in presence of finite transimpedance are computed as: where It is clear from Eq. (15) and Eq. (16) that transfer functions modify in presence of non-ideality. These equations reduce to Eq. (6) and Eq. (7) by choosing the operating frequency below min

Simulation Results
To verify the proposed scheme, the functionality of the filter from Fig. 8(a) is tested through SPICE simulations using CMOS OTRA architecture of [34] and 0.18 µm CMOS process parameters provided by MO-SIS (AGILENT). Supply voltages ±1.5 V are taken. The simulation is performed for pole frequency of 159 kHz and unity quality factor. All the resistances are taken as 10 kΩ and capacitor is taken as 100 pF. The simulated frequency response for low pass, band pass and high pass for the circuit from Fig. 8(a) are depicted in Fig. 9. The total power consumption is found to be 6 mW.
The other set of simulations is carried out to show tuning of band pass filter center frequency and gain. The center frequency is varied by changing R 1 and R 2 simultaneously from 5 kΩ to 20 kΩ in step of 5 kΩ while keeping all other resistances and capacitances at 10 kΩ and 100 pF respectively. This setting leads to constant Q value. Figure 11 shows the simulated band pass response for variation in center frequency and Q with change in resistance. It may be noted that Q varies slightly from unity value, which may be attributed to non-idealities of OTRA. chosen as 10 kΩ and 100 pF, respectively. The values of k = 1, 2 and 4 are taken to obtain gain of 1, 2 and 4, respectively. The simulated response is depicted in Fig. 12, which agrees with theoretical predictions.
The SPICE simulations are also performed to observe the time domain behavior. All resistances and capacitances are kept at 10 kΩ and 100 pF, respectively. A 5 kHz sinusoidal input of 50 mV amplitude is applied to the filter and the low pass transient response is depicted in Fig. 10. Total harmonic distortion is also measured by changing input sinusoid amplitude and its value was found to be within 3 % till 150 mV amplitude. Another simulation is done by applying three sinusoids having frequencies of 10 kHz, 100 kHz and 1 MHz, respectively. Figure 13 shows the input and output waveforms and corresponding frequency spectrums. It is clear that the sinusoid having 1 MHz frequency is significantly attenuated.
Monte Carlo simulations are also done to check robustness of the proposed circuits by considering Gaussian distribution for fifty runs with 5 % variations in all passive components. For brevity, the histogram of circuit from Fig. 8(a) at LPF node output is depicted in Fig. 14, it implies the circuit is well operated within the theoretical frequency.
The performance parameters related to power consumption, THD and output noise are presented in [11], [12], [13] and [14]. The same is placed in Tab. 1. The higher power consumption of the proposed topology in Center frequency (kHz)   compatison with other CMOS-based OTRA implementations may be observed. However, the output noise for the proposed topology is lowest.

Conclusion
An alternate realization for Single Input Multiple Output (SIMO) filter topologies has been presented in this contribution wherein differentiator is used as basic building block. An SFG is proposed for this purpose, which can further be used to derive sixteen SFGs through proper selection of inverting and non-inverting differentiators placed in loop; and their addition. The active block OTRA is used to verify the concept. All the realizations use three OTRAs, six resistors and two capacitors. The bandwidth and quality factor of these configurations can be adjusted independently of the pole frequency. The functional verification of the proposed method is done through SPICE simulations using 0.18 µm CMOS technology parameters from MO-SIS.