OTRA Based Piece-Wise Linear VTC Generators and Their Application in High-Frequency Sinusoid Generation

. This paper proposes methods to generate various types of Linear Voltage Transfer Curves (VTC) using Operational Trans-Resistance Ampliﬁer (OTRA) as the active block. It further goes on to propose meth-ods to multiplex various individual Linear VTCs to obtain any form of Piece-Wise Linear Voltage Transfer Curves (PWL), which ﬁnd many applications in the world of circuitry. One particular application has been highlighted, i.e. generation of High-Frequency Sinu-soids. Simulations of the Circuits proposed via Cadence Virtuoso, using TowerJazz’s 180 nm Technology Node have been reported, which satisfy the aim behind its development.


Introduction
Voltage transfer curves are essential in any form of analog signal processing.They provide an appropriate output waveform based on the need.Wave shaping finds many uses in electronics, from voltage limitation, to signal processing, and waveform generation.Sinusoidal signals are an integral part of many electronic apparatus, from communication systems, to power conversion, control systems, data processing, and instruments [1] and [2].
The usual choice of active block for such implementations is the Operational Amplifier (Op-Amp).However, this comes with many disadvantages.Op-Amp based circuits are limited by their low slew rate, and low bandwidth of operation, which makes them undesirable for high-frequency and high-speed operations.Current-mode processing is a leading choice of today's engineers, which gives us many advantages like high slew rate.As such, it is more linear, more dynamic, and faster in operation as detailed in [3].This has made current-mode active blocks increasingly popular.The OTRA block used in this work offers a much higher pole (corner frequency) than the generic Op-Amp, and a higher bandwidth of operation.Many applications of the OTRA have emerged in recent times, which indicate the usefulness of OTRA [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19] and [20].
Several PWL VTC and sinusoidal oscillators using current-mode active blocks exist in literature.Current Limiters based on the active block CDTA, and their practicality are detailed in [21].Methods to synthesise PWL VTCs have been discussed in [22], which can be modified for our use.CDTA [23] and [24], and OTRA [25], [26] and [27] based oscillators show the application of current-mode active blocks in generation of sinusoids.However, they use harmonic methods, which usually fail in high frequencies.Also, the solution in [24] has current inputs, making it impractical.None of the cited works use current-mode active blocks in PWL VTC generation to produce a sinusoid, which shows the gap in research, and the motivation behind this work.
In this work, we propose methods to generate any desired PWL VTC using OTRA active block, which gives us benefits of current-mode processing [3].One specific use case of voltage controlled high-frequency sinusoid generation is detailed, where voltage-mode active blocks and harmonic methods fail.All the circuits proposed have been simulated successfully, and the results are included.

2.
The OTRA The Operational Trans-Resistance Amplifier (OTRA) is a three-terminal device as shown in Fig. 1.
The OTRA amplifies the difference of the currents I p and I n and the output is the voltage V o in accordance to port characteristics as expressed by Eq. ( 1).The R m is known as the trans-resistance gain, and its value approaches infinity for an ideal OTRA, which in turn forces the input currents to be equal.For ideal operation, V p and V n should be zero.Also, V o should not depend on the current drawn from the output terminal, i.e.
The output of an ideal OTRA reaches positive or negative saturation levels (V DD or V SS ) if used in an open loop configuration as the R m is infinite.Thus, for linear applications the OTRA must be used in a negative feedback configuration.The OTRA used in this work [28] is shown in Fig. 2. The values of transistor W/L ratios, V B1 and I B may be referenced from [28].The OTRA gives us a Gain-Bandwidth Product of 600 GHz Ω, which makes it suitable for High-Frequency Applications.

Proposed VTC Generators
Positive and negative slope VTC generators based on OTRA are proposed in this section.
The schematic of the positive generator is shown in Fig. 3, where the OTRA is used in the non-inverting amplifier configuration [28].The output voltage V out is related to the input voltage V in by Eq. (2).
The first term in the RHS of Eq. ( 2) provides the desired slope, and the second term introduces the required DC offset.Here, the OTRA is used in inverting amplifier configuration [29].The output voltage V out is related to the input voltage V in by Eq. (3).3: Schematic for positive slope linear VTC generator.

Proposed PWL VTC Generators
The individual VTC generators as proposed in Sec. 3. can be multiplexed to generate a complex piece-wise linear voltage transfer curve (PWL VTC).To switch between appropriate VTCs at breakpoints, comparators need to be used, which compare the input voltage with the breakpoint voltage.The comparators feed a digital logic circuit, which needs to be synthesised for each use case.The logic gates will operate between V DD and V SS .The digital logic should be designed such that one and exactly one channel of the multiplexer is active for each and every piece of the PWL VTC, i.e. for all values of input voltage, exactly one of (S0, S0'), (S1, S1'), or (S2, S2') are active, and the rest inactive.
The digital logic controls the output of the analog multiplexer formed by transmission.The multiplexer lets the output from the desired VTC Generator pass based on the digital control logic.Standard CMOS design techniques may be used to design the gates [30].Using the blocks of Fig. 3, Fig. 4, Fig. 5 and Fig. 6, and the procedure outlined above, any desired PWL VTC can be generated.A simple use case of this has been illustrated in Sec. 5. , which uses a PWL VTC to convert a triangular wave into a sinusoid.

Application: High-Frequency Sinusoid Generation
A triangular wave, when passed through an appropriate PWL VTC, can produce an approximate sinusoid, as detailed in [1].This concept has been used to illustrate the usefulness of the PWL VTC generators proposed in this work.
The triangular wave is generated from a voltagecontrolled ring oscillator (demarcated by dashed line in Fig. 7) as detailed in [30], with transmission gates to control the delays, connected to an integrator circuit based on OTRA [29].Figure 7 shows the triangular wave generator used.All the transistors in the Voltage Controlled Ring Oscillator have the W/L ratio as 1 µ/0.5 µ.
Assuming the tripping voltage for an inverter is (V DD + V ss )/2, we get the equation for the propagation delay through the transmission gate as detailed in Eq. ( 4).Where the C L is the input capacitance of inverter, and V X the DC control voltage.Equation (5) gives the delay for one inverter, as explained in [30].
Thus, the frequency of the oscillator can be given by Eq. (6).
OTRA 1 is a comparator which compares this rectangular wave to ground, and outputs a sharper rectangular wave.
OTRA 2 is a lossy integrator [29].It integrates the rectangular wave into a triangular wave.OTRA 3 is used to boost the output of OTRA 2 to a rail to rail value.This outputs a triangular wave, which is passed on to the PWL VTC generator to output a sinusoid.

Control Voltage
Voltage Controlled Ring Oscillator Triangular Wave The PWL VTC generator for triangular to sinusoidal conversion is as shown in Fig. 8 OTRAs 1, 2 and 3 are used to generate the individual PWLs as follows: • OTRA 1 generates a VTC with slope = −1 and V bias = 0 V.
OTRAs 4 and 5 are connected as comparators with reference voltages +1 V and −1 V respectively.OTRA 6 is the output stage that converts the PWL VTC output to a rail to rail sinusoid.The output of an OTRA based amplifier near the rails is naturally slewed, and this can be used to our advantage to obtain a curvature in the transient waveform near the rails.

Simulation Results
The functional verification of proposed circuits is carried out on Cadence Virtuoso ADE using TowerJazz's 180 nm technology node.V DD is taken as +2 V and V SS is taken to be −2 V globally for simulations.The simulated and theoretical output of the positive VTC generator without and with bias have been reported in Fig. 9(a) and Fig. 9(b) respectively.Similar outputs for negative VTC generators are placed in Fig. 10(a) and Fig. 10(b).For these simulations, the values of R b and R in were taken to be 10 kΩ, V bias and R f were varied accordingly.
The operation of the proposed VTC generators is tested against process corner variations, for typical, fast-fast, fast-slow, slow-fast and slow-slow corners.Simulation results are shown in Fig. 12, which prove that the outputs are insensitive to process variations.Further, to test the effect of temperature variations, simulations were carried out by varying the temperature of the simulation environment, from −20 • C to +60 • C, in steps of 20 • C. The simulated output is shown in Fig. 13.The plot shows that the circuits are resilient to any forms of temperature variations.
Transient response of the triangular wave generator is shown in Fig. 11, which also shows variation in frequency with respect to control voltage V X .To verify the functionality of the sinusoid generator, the different VTCs chosen are as follows: • OTRA 1 is generating a VTC with slope = −1 and V bias = 0 V.The values of R i1 and R f 1 are both taken to be 100 KΩ.
• OTRA 2 is generating a VTC with slope = −0.4 and V bias = +0.6V.The values of R i2 and R f 2 are taken to be 100 KΩ and 40 KΩ respectively.
• OTRA 3 is generating a VTC with slope = −0.4 and V bias = −0.6V.The values of R i3 and R f 3 are taken to be 100 KΩ and 40 KΩ respectively.R c was taken to be 10 KΩ, and standard CMOS logic gates were used for the digital logic, as detailed in [30].
Theoretically, by Eq. ( 6), the frequency for the VCO at V X = 180 mV was found to be 1.13 MHz.On simulation, we found it was equal to 1 MHz.It can thus be calculated that the frequency deviation between theoretical and experimental frequencies is 13 % for the case implemented.The experimental value for frequency is lower than theoretical as the theory does not account for delays caused by the parasitic resistances and capacitances, which increase the time, and thus reduce the frequency.
The three individual VTCs are shown in Fig. 14, and the transient response output of the PWL VTC Generator is shown in Fig. 15.
Fig. 14: The individual VTCs and combined PWL VTC.In the output stage, R oi and R of were taken to be 10 KΩ and 25 KΩ respectively.The transient output of the output stage is shown in Fig. 16, in comparison with a standard sine wave.The obtained waveform slightly deviates from the ideal waveform, as we have used only three VTC sections.However, on increasing the number of VTC sections, this deviation can be reduced.Figure 17 shows the frequency spectrum of the output in comparison with that of an actual sine wave for 1 MHz frequency.As can be clearly observed, there is a good level of accuracy achieved in delivering a sinusoid output.Total Harmonic Distortion was calculated for the generated sinusoid, up to five harmonics, and the value was found to be 9.3776 %.The THD can be further improved by increasing the number of VTC sections.Monte-Carlo Analysis was done to test the performance of the circuit against component value variations.The resistors were varied with 10 % tolerance from the nominal value.The test was performed for 500 samples.It was found that for a < 5 % mismatch with respect to the nominal waveform, over 83 % of the samples passed the Monte-Carlo Simulation, which illustrates the low sensitivity to passive component parameter variations that our circuit exhibits.Monte-Carlo Analysis was also performed on the MOSFET Width parameter (W) with 5 % tolerance, < 5 % mismatch pass mark, and 500 samples yielded a pass for over 70 % of the samples.As on changing the W, the frequency of the VCO changes, the waveform is not a match to the nominal value, and shows variation.Also, the OTRA Gain is also changed, thus causing the mismatch.
Analyses for testing the behavior of the circuit against parasitic elements were performed.The input capacitance for the Inverter was 83 fF, and for the NOR Gate was 104 fF.The Output Capacitance of the OTRA was found to be 3.04 pF, which is much larger than that of the Digital Logic, and hence, the OTRA will dominate in the parasitic effects.It can be noted from [28] that for the low gain case as used in this work, the OTRA will function well for frequencies much higher than the ones at which we are generating the sinusoid.Hence, the effect of parasitics is negligible in our work.

Conclusion
In this work, positive and negative slope linear VTC generators using OTRA have been proposed, which can be designed to generate any linear curve as per the design rules mentioned in Eq. ( 2) and Eq. ( 3).They can be multiplexed to generate any desired PWL VTC as detailed in Sec. 4. As a particular application, three different VTCs have been multiplexed to generate a PWL VTC that converts a triangular wave into a sinusoid.This is useful in generating high-frequency sinusoids where harmonic oscillator methods and other voltage mode active block based circuits fail.
Simulation results on Cadence Virtuoso using Tow-erJazz's 180 nm technology node have been reported for all the circuits proposed.The VTC generators were tested for process corner and temperature variations, and were found to be extremely resilient to their changes.The frequency spectrum of the generated sinusoid is found to be very close to that of an original sine wave.

Figure 4
Figure 4 depicts the negative slope VTC generator.Here, the OTRA is used in inverting amplifier configuration[29].The output voltage V out is related to the input voltage V in by Eq. (3).

Figure 5 andFig. 5 :Fig. 6 :
Figure 5 and Fig. 6 show the implementation of the analog multiplexer and the OTRA based comparator respectively.
Positive VTC with bias.
pursuing his Bachelor of Technology in Electronics and Communication Engineering from Delhi Technological University.His research interests include Low-Power VLSI Design, Mixed-Signal VLSI Design, Analog Design, Neural Detectors and Brain Machine Interfaces.Neeta PANDEY is currently a Professor in Department of Electronics and Communication Engineering, Delhi Technological University.She did her M.E. in Microelectronics from Birla Institute of Technology and Sciences, Pilani and Ph.D. from Guru Gobind Singh Indraprastha University Delhi.She is a life member of ISTE, and Senior Member of IEEE, USA.Her research interests are in Analog and Digital VLSI Design.Rajeshwari PANDEY is currently a Professor in Department of Electronics and Communication Engineering, Delhi Technological University.She did her M.E in Electronics and Control from BITS, Pilani, Rajasthan, India and Ph.D. from Faculty of Technology, Delhi University, India.She is a life member of IETE, ISTE and member of IEEE, and IEEE WIE for over 12 years.Her research interests include Analog Integrated Circuits, and Microelectronics.