A Novel Realization of Low-Power and Low-Distortion Multiplier Circuit with Improved Dynamic Range

A novel topology of four-quadrant analog multiplier circuit is presented in this paper. The voltage mode technique is employed to design the circuit in CMOS technology. The dynamic input and output ranges of the circuit are improved owing to the fact that the circuit works in the saturation region not in weak inversion. Also the proposed multiplier is suitable for low voltage operation and its power consumption is relatively low. In order to verify the performance of the proposed circuit, performance of the circuit affected by second order effects including transistor mismatch and mobility reduction is analyzed in detail. It will be shown that any conceivable mismatch in the transistor parameters leads to second harmonic distortion. Additionally, the effect of mobility reduction in the third harmonic distortion will be computed. In order to simulate the circuit, Cadence and HSPICE software are used with TSMC level 49 (BSIM3v3) parameters for 0.18 μm CMOS technology, where under supply voltage of 1.5 V, total power consumption is 44 μW, the corresponding average nonlinearity remains as low as 1 %, and the input range of the circuit is ±400 mV.


Introduction
In recent years, analog multipliers are widely used in many applications such as phase-locked loops, adaptive filters, modulators, automatic gain controlling, image processing, artificial neural networks and fuzzy integrated systems [1], [2], [3] and [4].Different methods of implementation of this building block have been recently presented based on the use of bulk driven MOS [5], Floating Gate MOS (FGMOS) [6] and class-AB mode [7].In the past decade, the demand for portable operation of electronic systems has led to the trend of designing circuits to be featured with low power consumption and operate for low supply voltages.One possible technique to design the low-power dissipation multiplier circuit is to use MOSFETs in sub-threshold region [8], [9] and [10] in which most of them follow the Gilbert cell topology and modified Gilbert cell [11].
The drawback of designs in this region has been referred to poor dynamic range, limited bandwidth and low voltage swing.Another approach of designing low power multiplier circuits is to use the translinear principle of MOS transistors operated in the weak inversion [12] and [13].Although this approach has the advantage of low power consumption, the dynamic range of these circuits is very small and operation speed is slow.On the contrary, presented multipliers based on the translinear loop in saturation region exhibit wider bandwidth, higher dynamic range and lower distortion and thus they are more preferred than those operating in weak inversion [14].Nonetheless, the channel length modulation and body effect are the important issues in the circuits based on translinear loop principle.Another salient feature of the circuits is the four-quadrant operation capability, an important asset very useful in various applications [15] and [16].Some of the wellknown multiplier circuits operate only in one [17] and [18] or two quadrants [19] and [20], which was discussed in [21] and not suitable for many of mentioned applications.
Another factor, which is important in the multiplier circuit, is non-linearity factor, because of the fact that the multiplication operator is a linear map between input and output.Therefore this factor is a serious challenge in the multiplier circuits, which is commonly affected by body effect, mobility reduction and mismatch in the circuit devices.In some existing analog multipliers, the effects of these non-idealities were properly studied and a few techniques were proposed in order to reduce the non-linearity [22] and [23].However, they suffer from low accuracy and/or low bandwidth.Moreover, single supply voltage circuits are preferred to those in dual mode [24], where the multipliers reported in [8] and [20] require dual supply voltage.As such these circuits are not suitable for today's world of portable equipment.
In this paper, a novel design of four quadrant analog multiplier is presented which benefits from advantages of differential output topology.The dynamic input and output ranges of the circuit are significantly improved.High linearity and high accuracy are further advantages of the circuit.Also the proposed multiplier is suitable for low voltage operation and its power consumption is relatively low.The performance of the proposed multiplier is characterized using HSPICE with TSMC in 0.18 µm CMOS technology.The paper is organized in 5 sections: The proposed circuit is presented in Sec. 2. , followed by the performance analysis in Sec. 3. In Sec. 4. , HSPICE simulation results of proposed multiplier circuit are presented to prove the efficiency of the design.Finally, Sec. 5. concludes the most important achievement of the proposed circuit.

The Proposed Multiplier
The proposed four-quadrant multiplier circuit is shown in Fig. 1, which is based on the square-difference algebraic identity as: According to this, to realize this equation, two squaring functions should be designed in which their outputs need to be subtracted.Let us consider the proposed circuit of Fig. 1.Assume that all of the transistors operate in saturation region (except for M 17 and M 18 ), thus the drain current of transistors by neglecting the second order effect such as mobility reduction and channel-length modulation can be expressed as: where K = 0.5µ 0 C OX (W/L) is related to transconductance parameter, V GS is gate-to-source voltage and V T represents the threshold voltage of MOS transistor which can be affected by body effect.The body effect refers to change in the transistor threshold voltage resulting from a voltage difference between the transistor source and substrate, which can be characterized by: where V t0 is the zero-bias threshold voltage, γ is the body-effect coefficient and ϕF is the Fermi potential.
Considering the figure, two squaring circuits are shown in left half and right half of the structure.Focusing on the left side squaring circuit, since transistors M 1 and M 2 are biased in the saturation region and also I D1 = I D2 , the relationship can be written as: Simplifying equation above we have: Replacing Eq. ( 5) and Eq. ( 6) in Eq. ( 7); after few mathematical manipulations we have: It can be clearly seen from Eq. ( 8) that the current I D13 is the square of the input voltage plus some constant voltages.The same procedure can be followed for the right half of the circuit to obtain I D15 : The currents of I D13 and I D15 are transferred to the output through transistors M 14 and M 16 , respectively.Transistors M 17 and M 18 are biased in the triode region (by setting V Bp = −1) and perform as the resistors in which their resistance values can be represented by: By setting R 17 = R 18 = R, the output voltage of proposed circuit can be derived as: According to Eq. ( 11), by establishing V in1 = V x +V y and V in2 = V x − V y the ultimate voltage is eventually what would be expected as follows: Take notice that summation of the signals is provided by series connection of the voltage sources (V x and V y ).Also subtraction of the input signals was realized in the same way except for changing the polarity of V y , which were performed using a well-known inverting amplifier.Also, there is no need subtraction at the output node, because the output is differential.

Performance Analysis
In this section, performance of the circuit affected by second order effects including transistor mismatch and mobility reduction is analyzed in detail.It will be shown that any conceivable mismatch in the transistor parameters leads to second Harmonic Distortion (HD).Additionally, the effect of mobility reduction in the third harmonic distortion will be computed.Following that, the effect of corresponding parameters derived in each section as well as improvement methodology will be thoroughly discussed.

Second HD Due to the Mismatch
In Sec. 2. , the well-matched parameters including trans-conductance and threshold voltage of the transistors were assumed to obtain the output of the circuit.Considering Eq. ( 5), due to the fact that the voltage of V 1 is resulted by supposing these matched parameters, any possible mismatch in the proposed circuit will affect the voltage of this node.Similarly, the voltages of V 2 , V 3 and V 4 get affected by the mismatch accordingly.Since these voltages have direct proportion to V in1 and V in2 , consequently the total mismatch is referred to the input signals and can be modeled as: where ∆v in1 and ∆v in2 are mismatch percentages of V in1 and V in2 , respectively.By applying V in1 = V x +V y and V in2 = V x −V y to the multiplier circuit, the output voltage is given by: It can be clearly seen that the terms of ∆v 2 in1 and ∆v 2 in2 are very small (because ∆v in1 and ∆v in2 < 1), therefore the resulted error will be negligible.It is worthwhile to calculate the harmonic distortion of the circuit at the output considering the method presented in [25], if one of the inputs (V x ) is kept constant and the other one is sinusoidal in the form of V y = v m sin t, second harmonic distortion can be derived as follows: The equation implies that when the mismatch percentage of ∆v 2 in1 and ∆v 2 in2 increases, second harmonic distortion decreases.Also, it decreases with decreasing V x as well.

Effect of Mobility Reduction in Third HD
If the mobility reduction is taken into calculations, the drain current of a MOS transistor operated in saturation is given by [26]: where θ is the mobility degradation parameter which varies typically from 0.001 to 0.1 V −1 .This equation may be expanded in a Taylor series: To simplify the calculations, just the first order of θ is used, and the higher-order terms are ignored.Replacing the expansion in Eq. ( 4), one can reach V 1 and V 2 as: The same procedure can be followed to obtain V 3 and V 4 .In this case, the output of the multiplier circuit can be represented as follows: By applying V in1 = V x + V y and V in2 = V x − V y , the final output will be obtained.Since the output voltage includes third-order of the inputs, third harmonic distortion is achieved by keeping one of the inputs (V x ) as a constant and the other one as sinusoidal.Again using the method presented in [25] we have: 4.

Post Layout Simulation Results
In this section, simulation results are presented using HSPICE with TSMC level 49 (BSIM3v3) parameters for 0.18 µm CMOS technology so as to verify the performance of the proposed circuit.The simulation results are carried out after extracting the layout, which is drawn by Cadence software using single poly and two metals (Metal1 and Metal2).Figure 2 shows the full layout of the circuit, in which the area is 66.35 µm×58.2µm.The aspect ratio of transistors is given in Tab. 1 and the supply voltage is 1.5 V. Considering the condition of triode region for PMOS transistors of M 17 and M 18 , choosing V Bp = −1 V guaranties that these transistors operate in the triode region and work as the active resistances.DC transfer characteristic of the circuit over a considerable range of the inputs is shown in Fig. 3, in which one of the inputs (V y ) is kept constant and the other one (V x ) swept from −400 mV to +400 mV.By changing the constant voltage of V y and then sweeping of V x , desired outputs will be obtained.Within this range, the average of measured nonlinearity error is 0.94 %.
Tab. 1: Transistor aspect ratios.Figure 4 shows the multiplier being used for balance modulator as well as the error quantity.V x and V y are 500 kHz and 50 kHz, 800 mV P-P sinusoidal carrier and modulation signals, respectively fed to inputs of the proposed multiplier.Also Fig. 5 demonstrates how the multiplier circuit can be employed as a frequency doubler.In this simulation, if both frequencies of the input voltage are 500 kHz, the figure shows the corresponding output waveform with double frequency of 1 MHz.Frequency response in Fig. 6 shows that bandwidth of the circuit is 196 MHz when the input signal is applied to V x , and V y = 400 mV.The same result is obtained for constant value of V x and AC signals for V y .The Total Harmonic Distortion (THD) versus input signal at 100 kHz and 1 MHz is shown in Fig. 7. THD simulations are carried out for both of V x and V y , when one of them is constant and another one is sinusoidal.In the worst case, an input signal of 1 V p-p at a frequency of 1 MHz resulted in a THD of less than 1.2 %.In order to evaluate the robustness of the circuit against the process variation, the Monte Carlo analysis with 100 samples is performed by applying ±5 % Gaussian distribution at ±3σ level in the variation of all transistors aspect ratio and threshold voltage simultaneously.Two sinusoidal signals with the frequencies of 500 kHz and 1 MHz and also 400 mV p-p and 800 mV p-p amplitudes are applied to the circuit under the aforesaid variations and then the outputs are compared with the ideal values.The average of error in each sample is considered as the relative error.The result is shown in Fig. 8, in which 68 % of the total samples occurred with the relative error of less than ±1 %.
To analyze the performance of the proposed circuit regarding temperature variations the simulations are carried out in different temperatures.The threshold voltage is the most important parameter in the analysis of temperature dependence of CMOS circuits [27].Therefore, a small variation in threshold voltage causes a large change in the output.Although single-ended output of the squaring circuits (see Eq. (8) or Eq. ( 9)) includes the threshold voltage, the output of the complete circuit (see Eq. ( 12)) does not depend on the threshold voltage, therefore no remarkable change occurs at the final output.summarized in Tab. 2 and compared with the former works to prove the efficiency of the circuit.

Conclusion
A new CMOS voltage-mode analog multiplier circuit was presented in this paper.The key features of the circuit are its high accuracy and high linearity as well as its body effect-free operation, owing to the fact that the circuit was designed based on a new symmetrical configuration.Compared to the previously reported works, the dynamic input and output ranges of the circuit are considerably improved, since the circuit works in the saturation region not in weak inversion.To prove the efficiency of the proposed circuit, it was employed as a modulator and frequency doubler, and the simulation results were compared with ideal performance of these applications.The performance of the proposed multiplier was characterized using HSPICE with TSMC level 49 (BSIM3v3) parameters for 0.18 µm CMOS technology.

Fig. 8 :
Fig.8: Monte Carlo analysis of the circuit for ±5 % mismatch in threshold voltage and transistors aspect ratio.

Figure 9 Fig. 9 :
Figure9shows the relative error of the circuit in different temperatures, where the maximum error occurred at −40 • C with 1.18 %.In this simulation, the obtained output at the temperature of 25 • C is considered as the reference value (relative error = 0), then the resulted outputs in other temperatures are compared with that value and the relative error is computed.It should be pointed out that the input signals are the same as the signals that were applied in the Monte Carlo analysis.The characteristics of the circuit are Tab. 2: Comparative parameters of the proposed multiplier with other recent works.
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