Ultra Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL Logic

With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Efficient Charge Recovery Logic), 2N-2N2P and PFAL (Positive Feedback Adiabatic Logic), and presents a new proposed circuit based on the PFAL logic circuit. The aim of this paper is to simulate various logic gates using PFAL logic circuits and with the proposed logic circuit, and hence to compare the effectiveness in terms of average power dissipation and delay at different frequencies. This paper further presents implementation of C17 and C432 benchmark circuits, using the proposed logic circuit and the conventional PFAL logic circuit to compare effectiveness of the proposed logic circuit in terms of average power dissipation at different frequencies. All simulations are carried out by using HSPICE Simulator at 65 nm technology at different frequency ranges. Finally, average power dissipation characteristics are plotted with the help of graphs, and comparisons are made between PFAL logic family and new proposed PFAL logic family.


Introduction
The rapid advancement in semiconductor technology in electronic devices over the years has resulted in bet-ter performance and higher circuit densities.However, as the size is getting smaller and the integration density increases, the increasing power dissipation has become a primary concern for further development of VLSI circuit technology.The two main types of power dissipation in semiconductor devices are: static power and dynamic power dissipation.The dynamic power dissipation is due to the energy loss during the process of charging and discharging of output capacitance, during switching activities in transistor, while static power dissipation is caused by internal leakage in devices when the circuit is in off state [1].
Dynamic power dissipation has been the primary concern of circuit designers in early period.Various circuit technologies have been introduced for reducing dynamic power like sub-threshold logic [3], multithreshold technology [4], and adiabatic logic circuit [2].The adiabatic logic is a novel low power circuit technology which utilizes AC voltage supply as opposed to DC voltage supply so as to recycle the energy of circuits.
The term 'adiabatic' comes from 'thermodynamics' which is used to describe a process in which no energy exchanges with the environment, and hence no dissipation energy loss takes place.While in semiconductor devices, the charge transfer between different nodes is the process of energy exchange and different techniques can be used for minimizing this energy loss due to charge transfer.While fully adiabatic operation is the ideal condition of a circuit operation, in practical cases partial adiabatic operation of circuit is used because it gives considerable performance.
In conventional CMOS circuits the energy stored in load capacitors was dissipated to ground.While adiabatic logic, in contrast, offers a way to reuse this energy and thus prevents the wastage of this energy.By adding the ideas of both the conventional and the adiabatic logic circuits together, power dissipation can be reduced drastically.
Different circuits based on adiabatic logic have been proposed over the years [5], [6], [7] and [8].To recycle the energy of circuit nodes, adiabatic logic based devices utilize AC power clock which has a four-phase operation.In these circuits the charge, rather flowing from the load capacitance to ground, it flows back to the trapezoidal or sinusoidal supply voltage and thus can be reused [9].
In this paper, power dissipation and delay is calculated for different logic gates using PFAL and with proposed PFAL logic, and results are compared graphically to see the effectiveness of the proposed logic circuit over the base PFAL adiabatic logic circuit.The rest of the paper is organized as follows: Section 2. overviews the conventional CMOS and adiabatic logic circuits.In Section 3.
a proposed logic circuit is presented in brief and a 2:1 Multiplexer circuit is implemented using the proposed logic circuit.In Section 4. , simulation of circuits is done at different frequencies and results of power dissipation and propagation delay are compared and presented graphically.The paper ends with the conclusion given in Section 5.

2.
Conventional CMOS and Adiabatic Logic

Conventional CMOS
In order to understand the conventional switching operation, a simple CMOS inverter is used.A pull-up and a pull-down MOS transistor, connected in series with a load capacitance C Fig. 1.
Power dissipation in CMOS transistors occurs mainly because of the device switching operations.At each charging and discharging operation, there is an inevitable energy loss of CV 2 dd for static CMOS circuits.During charging operation, the energy dissipation through pull-up block from power supply is equal to CV 2 dd , of which half of the energy (0.5 CV 2 dd ) is stored in load capacitor.The other half is dissipated through the resistive path, and lost as heat to the environment.Now during the operation of discharging, the residual energy stored in the load capacitor (0.5 CV 2 dd ) will be released to the ground through pull-down network [11].And therefore, no energy recovery is possible in the conventional CMOS circuits.

Adiabatic Logic
The use of AC power clock as opposed to DC supply makes the adiabatic circuits capable of recovering the stored energy of node capacitors back to the power source, and hence avoids the dynamic power loss almost completely, theoretically.The use of adiabatic logic principle in designing low power circuits is continuously growing and is proving to be a better selection in comparison to other conventional circuits.The adiabatic operation usually consists of four phases, with a phase difference of one quarter of a period.The four phases of operation respectively are Wait, Evaluate, Hold and Recovery Fig. 2. In the WAIT phase the power clock stays at low (zero) value, which maintains the outputs at low value, and the evaluation logic generates pre-evaluated results.Now, since the power clock is at low level, the pre-evaluated inputs will not affect the state of the gate.In the EVALUATE phase, the power supply ramps up from zero to V dd gradually, and the outputs will be evaluated as per the result of pre-evaluation logic.In the HOLD phase, power clock stays high, providing the constant input signal for the next stage in pipelining of adiabatic circuits, and keep the outputs valid for the entire phase.Meanwhile inputs ramp down to low value.In the RECOVERY phase of operation, the power supply ramps down to zero and the energy of the circuit nodes is recovered back to the power source instead of being dissipated as heat [6].

Efficient Charge Recovery Logic (ECRL)
Efficient Charge Recovery Logic (ECRL) [5], as shown in Fig. 3, uses two PMOS transistors in cross-coupled fashion, and two NMOS transistors in the N-functional blocks of ECRL logic block.In order to recover the supplied energy which can be reused, ECRL gates use AC power clock (pck).Let us assume, input 'In' is at high level and 'Inb' is at low level.At the beginning of a cycle, when power clock 'pck' rises from zero to V dd , 'Out' remains at low level because the high input 'In' turns the F NMOS logic high.Output 'Outb' follows the power clock 'pck' through M1.Now when 'pck' reaches to V dd , the outputs hold valid logic values.During the hold phase these output values are maintained and can be used as inputs for evaluation of the next stage.In the next phase of recovery, the power clock falls down to zero level and the energy from the output node can be returned to the 'pck' so as to recover the delivered charge [13].The major disadvantage of this circuit is the existence of coupling effects, since the two outputs are driven by the PMOS latch, and so the two complementary outputs may interfere with each other.And as the operation is concerned, it is identical to that of ECRL family.This new family is derived in order to reduce the coupling effects in the circuit.Also, the two new NMOS transistors have the advantage of eliminating the floating nodes for large part of the recovery phase.However, the added transistors prevent the circuits form achieving significant power reduction as compared to the ECRL logic circuits [10].

Positive Feedback Adiabatic Logic (PFAL)
The Positive Feedback Adiabatic Logic (PFAL) achieves the lowest power consumption as opposed to other similar adiabatic logic families.The generalized PFAL circuit diagram is shown in Fig. 5.The latch is made similar to the 2N-2N2P logic circuit with two PMOS transistors and two NMOS transistors.The functional blocks of NMOS logic are connected in parallel with the PMOS transistors of the latch and form the transmission gates.The fact that the functional blocks are in parallel with the PMOS transistors, the equivalent resistance is smaller during the charging of capacitance [13].

Proposed Circuit
The generalized circuit diagram for the proposed logic is shown in Fig. 6.The circuit is similar to PFAL logic circuit with the latch comprising of two PMOS The effect of connecting an active load and a DC voltage source needs to be understood in order to analyze the proposed logic effectively.As we know from the basic concept of MOSFET that in an NMOS transistor with its drain terminal shorted to gate terminal, it will always be working in the saturation region.
As, V ds = V gs .Therefore, V DS > V GS − V T always and thus it is in saturation region.That is the NMOS diode is always on for all V GS V T values.And the current IDS will be given by: ( From the equation it can be seen that IDS is now dependent on VDS squarely.In our proposed DCDB-PFAL logic, the source terminal of the NMOS diode is connected to a positive DC voltage source of value V dc which is then connected through ground terminal. Thus we see that the source voltage V S = V dc .And so, V DS = V D − V dc .Therefore, Eq. ( 1) will now become: From Eq. ( 2) it can be seen that, as we apply a positive voltage at DC source, V DS will start reducing.As a result, V DS − V T will reduce and thus I DS will start reducing.Therefore, we can see that with the use of an NMOS diode and with increasing the DC voltage both the voltage difference and the current start reducing.And thus a further reduction in power dissipation is achieved with the new proposed DCDB-PFAL technology of adiabatic logic family.The circuit attains low-power operation because a low DC Source is connected to the circuit in series.Thus the proposed logic family reduces the gate to source voltage at the output transistors and thus reducing the gate and leakage current and providing further lower power dissipation as compared to conventional PFAL logic circuit.A 2:1 MUX has been implemented using conventional PFAL and proposed DCDB-PFAL logic.Circuit diagrams for both of them are shown in Fig. 7 and Fig. 8 respectively.In Fig. 9 and Fig. 10 we have shown the waveforms for implemented combinational circuits using conventional PFAL logic and by using proposed logic family, respectively at 100 MHz frequency.The graph shows the waveform for power clock used, inputs A and B, select line S and the output waveform.The effect of using a dc source can be seen from the output waveform of Fig. 10, where the output voltage is not zero but it is level shifted by the value of the V dc which is varied in between 0.1 V to 0.3 V.

Simulation and Result
In order to see the effectiveness of the proposed DCDB-PFAL logic circuits over conventional PFAL logic family, different logic gates have been implemented, first using conventional PFAL logic family and then by us- All the logic circuits are simulated using HSPICE Simulator at 65 nm technology.Table 1 lists the design parameters utilized in the simulation of circuits, and Tab. 2, Tab. 3, Tab.4, Tab. 5 and Tab.6 show the results of power dissipation, delay and power delay product (PDP) for different logic circuits.Finally, the graphs have been plotted, showing the comparison of average power dissipation for the PFAL and DCDB-PFAL circuit.We have shown the waveforms of simulation of 2:1 MUX using PFAL and DCDB-PFAL logic families.Further, Fig. 11, Fig. 12, Fig. 13 show an average power comparison for 2:1 MUX circuit using proposed circuit over PFAL, while Fig. 14, Fig. 15, Fig. 16 show a comparison of lowest power dissipation achieved using proposed DCDB-PFAL circuits over conventional PFAL circuits.
It can be seen from the readings of different tables and different graphs plotted for different logic circuits at different frequencies that with the dc voltage varying between 0.1 V to 0.3 V, power first decreases up till around 0.25 V and then increases gradually.And the proposed circuit performs better in comparison to the conventional adiabatic families up to a voltage range of 0.  the logic circuit as compared to that of conventional PFAL adiabatic logic family.For proper validation and verification of the results we have tested our existing and proposed work on bechmark circuits C17 and C432 as shown in Fig. 17 The results for average power dissipation of the benchmark circuits are shown in Tab. 7. C17 benchmark circuit provides a percentage improvement of 32 % in power dissipation for DCDB-PFAL logic over PFAL logic based circuit.While for the C432 benchmark circuit a power reduction of 22 % is achieved for the DCDB-PFAL logic circuit over the conventional PFAL based benchmark circuit.

Conclusion
This paper reviews the basic adiabatic logic circuits.Different logic gates have been implemented using the proposed DCDB-PFAL logic and conventional PFAL logic at different frequencies and for different values of dc voltages for the new logic circuit.Besides, a combinational circuit 2:1 MUX has also been implemented for the proposed and the conventional logic.Finally, we have further implemented benchmark circuits C17 and C432 for further validation of the proposed DCDB-PFAL logic family.The results show much enhanced performance of the proposed circuit over conventional PFAL logic and it offers significant power reduction over the PFAL.DCDB-PFAL based C17 benchmark circuit provides 32 % lower power dissipation while DCDB-PFAL based C432 benchmark circuit provides 22 % lower power dissipation as compared to the conventional PFAL based benchmarks circuits respectively.It can be seen from the tables and different graphs plotted, that as the dc voltage is varied between 0.1 V to 0.3 V, power first decreases up till around 0.25 V and then increases gradually.The proposed DCDB-PFAL logic can be used in devices which need to work on ultra-low power such as pacemaker, hearing machine and other medical purpose devices.As the quest for ultra-low power circuit designs keep on increasing, these improved circuit technologies would prove to be very useful in serving the need.
2N-2N2P Logic family is a variation of ECRL Logic family with two new cross coupled NMOS transistors added parallel to the 2 existing NMOS transistors.The generalized 2N-2N2P circuit diagram is shown in Fig. 4.
Multiplexer circuit is implemented and average power and delay calculations are made at different frequencies and different DC voltages for the voltage source.
c 2017 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING Tab.7: