VDCC Based Dual-Mode Quadrature Sinusoidal Oscillator with Outputs at Appropriate Impedance Levels

This article presents a new dual-mode (i.e. both current-mode and voltage-mode) quadrature sinusoidal oscillator using two Voltage Differencing Current Conveyors (VDCCs), two resistors and two capacitors. The proposed configuration use only grounded passive elements and enjoys independent resistor/electronic tuning of both Condition of Oscillation (CO) as well as Frequency of Oscillation (FO). The quadrature current and voltage mode outputs of this circuit are available at appropriate impedance terminals. The behavior of presented oscillator is also examined under non ideal/parasitic conditions. The validity of the proposed configuration has been confirmed by SPICE simulations with TSMC 0.18 μm process parameters.


Introduction
Oscillator is an important circuit configuration, which finds several applications in measurement, signal processing, communication, instrumentation and control systems [1], [2], [3], [4], [5].A quadrature sinusoidal oscillator which provides two 900 phase shifted sinusoidal outputs simultaneously is widely used in telecommunication engineering applications such as in quadrature mixers, single sideband modulators and directconversion receivers or for measurement purpose in se-lective voltmeters and vector generators [6], [7], [8].Several VM and CM quadrature sinusoidal oscillators employing different Active Building Blocks (ABBs) have been reported in open literature.Careful investigation of literature available on quadrature oscillators reveals that most of the oscillators provide either voltage mode quadrature outputs or current mode quadrature outputs but only very few circuits are those which provide voltage mode and current mode quadrature outputs simultaneously.This simultaneous availability of quadrature outputs is very useful in mixed mode applications where current and voltage signals are required together.
The earlier work on dual-mode quadrature sinusoidal Oscillators employing different active element(s) has been reported in [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21].Unfortunately, these reported circuits suffer from one or more of following drawbacks: (i) presence of floating passive component(s), which is not desirable from the viewpoint of monolithic integration (ii) lack of independent electronic control of both FO and CO (iii) lack of independent resistive control of both FO and CO (iv) non-availability of quadrature VM outputs at low impedance terminals (which need additional voltage followers for cascading) and (v) nonavailability of high impedance explicit quadrature CM outputs (which need additional current followers for sensing and taking out the currents) (vi) use of ABB with current copy terminal(s) to get explicit CM outputs (which need additional MOSFETs/BJTs to realize current copy terminal(s).
Therefore, the purpose of this article is to present a new CM/VM sinusoidal quadrature oscillator employing two VDCCs, two resistors and two capacitors which enjoys following advantageous features simultaneously Fig. 2: CMOS implementation of VDCC [23].
which are not available with any of the previously proposed quadrature oscillator configurations; • Use of all grounded passive components.
• Independent electronic control of both FO and CO.
• Independent resister control of both FO and CO.
• Independent tuning of FO and CO under non-ideal conditions.
• Independent tuning of FO even under the influence of parasitics.
• Availability of high impedance explicit CM quadrature outputs.
• Availability of low impedance quadrature VM outputs.
VDCC is a versatile ABB proposed by Biolek in 2008, which provides electronically tunable transconductance gain in addition to transferring both current and voltage in its relevant terminals [22].Some applications of VDCC as grounded/floating inductor simulators [23], [24], Single Resistance Controlled Oscillator (SRCO) [25] and voltage mode biquad filter [26] have been reported in available literature.
The circuit symbol and behavioral model of VDCC are shown in Fig. 1, where P and N are input terminals and Z, X, W P and W N are output terminals.The terminals Z, X, W P and W N exhibit high impedances while X is a low impedance terminal.The CMOS implementation of VDCC [23] has been shown in Fig. 2. The ideal terminal characteristics of VDCC can be defined by the hybrid matrix as given by Eq. (1): (1)

Proposed Quadrature Oscillator
The proposed dual-mode quadrature oscillator is shown in Fig. 3.
The routine circuit analysis of proposed dual mode quadrature oscillator configuration as shown in Fig. 3, Fig. 3: The proposed dual-mode quadrature oscillator configuration.
From Eq. (3) and Eq. ( 4) it is clear that CO can be set by R 2 or g m2 and FO is tuned by R 1 or g m1 .Hence, CO and FO both enjoy the independent electronic as well as resistive tuning.
The expressions of CO and FO do not have any common term.Thus, the proposed circuit has the feature of completely non-interactive control of CO and FO.The current relationships derived from Fig. 3 are: For sinusoidal steady state, Eq. ( 5) and Eq. ( 6) become: It is evident from Eq. ( 7) and Eq. ( 8) that the phase difference between currents (I o2 and I o1 ) and (I o2 and I o3 ) is −90 • .Hence, the currents (I o1 and I o2 ), and (I o2 and I o3 ) are in phase quadrature.The currents I o2 and I o3 are explicit quadrature current outputs at high impedance terminals.

The voltage transfer function from
In sinusoidal steady state: Hence, the phase difference between V 1 to V 2 is −90 • i.e.V 2 and V 1 are in quadrature form and are available at low impedance terminals.Thus, the proposed circuit configuration can provide both VM and CM quadrature signals simultaneously at appropriate impedance levels.

Effects of VDCC Parasitics
In this section, the proposed quadrature oscillator is investigated under the influence of VDCC terminal parasitics.In CMOS VDCC (shown in Fig. 2) parasitic resistance R x appears in series with X terminal, parasitic resistance R P and parasitic capacitance C P appears in parallel between W P terminal and ground,parasitic resistance R N and parasitic capacitance C N appears in parallel between W N terminal and ground and a grounded parasitic resistance R Z appears at Z terminal.The proposed oscillator configuration including VDCC terminal parasitics has been shown in Fig. 4.
The effect of low resistance parasitic resistors R X1 and R X2 can be eliminated by merging them with external resistors R 1 and R 2 respectively.It is further noted the low parasitic capacitances C N 1 and C N 2 are in parallel with external capacitor C 2 .So, the effects of C N 1 and C N 2 can be alleviated by merging them with C 2 .Therefore, the influence of parasitic capacitances can be completely removed from the proposed oscillator configuration but grounded parallel parasitic resistances R N 1 , R N 2 , R Z1 and R Z2 cannot be balanced and will affect the circuit.To minimize the influence of theses parasitic resistances, the operating frequency can be chosen as Eq.(11).
The parasitic resistance R P 1 (or R P 2 ) and parasitic capacitance C P 1 (or C P 2 ) appear between W p terminal of VDCC1 (or W p terminal of VDCC2) and ground.The phase relationship between current I 2 and I 3 will be changed due to these parasitic components.So, to reduce the effect of these parasitics, the operating frequency (ω 0 ) has to be chosen as: Therefore, the useful operating frequency range of presented quadrature oscillator circuit can be described by combining conditions given in Eq. (11) and Eq. ( 15) we obtain Eq. ( 12) The CO and FO of oscillator shown in Fig. 4 are given for CO Eq. ( 13) and for FO Eq. ( 14).
From Eq. ( 13) and Eq. ( 14) it is clear that even under the influence of parasitics the FO can be independently tunable by g m1 .So, proposed configuration exhibits low parasitic effects.

Non-Ideal Analysis and Sensitivity Calculations
In the non-ideal case, the VDCC can be characterized by the following equations: where α, γ W P , γ W N are current tracking errors and β is voltage tracking error.
Considering the non-idealities of VDCC-1 and VDCC-2, the characteristic equation of circuit shown in Fig. 4 becomes: where are tracking errors of VDCC-1 and VDCC-2 respectively.
The CO and FO of proposed circuit under non ideal conditions can be found from Eq. ( 20), for CO: Eq. ( 21) and for FO: Eq. ( 22): It is noted from Eq. ( 21) and Eq. ( 22) that CO and FO are independently tunable under non-ideal conditions as well, CO by g m2 or β 2 or α 2 or γ W N2 and FO by g m1 or α 1 or γ W N2 , which confirm the good nonideal behavior of presented oscillator.The sensitivities of ω 0 with respect to R 1 , R 2 , C 1 , C 2 , g m1 , g m2 under the influence of terminal parasitics of VDCCs are given by Eq. ( 23).Also under non-ideal conditions, the sensitivities of ω 0 with respect to various active and passive elements are obtained in Eq. ( 24).So, it can be seen from Eq. (24), that all the sensitivities under non-ideal conditions are low and not more than half in magnitude.
The frequency Stability Factor S F of proposed oscillator is found to be 2 √ n for C 1 = C 2 , 1/R 2 = g m2 , and 1/R 1 = ng m1 .Therefore, a high value of frequency stability can be achieved by selecting large value of n.

Simulation Results
The performance of proposed oscillator has been verified by SPICE simulations using TSMC CMOS 0.18 µm processes parameters.Simulations have been performed using CMOS VDCC (shown in Fig. 3) with supply voltages ±0.9 VDC and transconductances gains g m1 = g m2 = 277 µA•V −1 .The passive component values were chosen as: R 1 = 5 kΩ, R 2 = 3.65 kΩ, C 1 = C 2 = 0.05 nF.The dimensions of MOS transistors used in simulation have been given in Tab. 1.
Tab. 1: Dimensions of MOS transistors.Simulated current and voltage responses have been shown in Fig. 5 and Fig. 6 respectively.The lissajous figures shown in Fig. 7 and Fig. 8 are ellipses with no tilt in axis which confirm the quadrature relationship of current I 2 with current I 3 and voltage V 1 with V 2 .Output spectrum of current I 2 is shown in Fig. 9, where the frequency of oscillation equals to 737.8 kHz and the Total Harmonic Distortion (THD) is found to be 2.66 %. Figure 10 shows the variation of amplitude and frequency of current output I 2 on varying resistance R 1 .The electronic control of FO (of I 2 ) with the bias current I B1 was shown in Fig. 11.The THD values of current I 2 for different values of bias current I B1 havebeen shown in Fig. 12 and it is clear here that except I B1 = 55 µA (for which THD is 3.55 %), for all other values of I B1 THD is less than 3 % which is under expectable range.
The robustness of proposed configuration has been checked by Monte-Carlo simulations on ±10 % variation of R 2 and the sample results are shown in Fig. 13.
It can be illustrated from Fig. 13 that, the frequency of oscillation varies from 721.176 kHz (minimum value) to 739.103 kHz (maximum value) with mean value of 732.578 kHz.So, the variation from mean frequency is 1.5 % (lower side) and 0.088 % (upper side), which confirms the good frequency stability.
These results thus validate the feasibility of proposed configuration.
A comparison of proposed oscillator configuration with previously reported second order dual mode quadrature sinusoidal oscillators has been summarized in Tab. 2.

Conclusions
A new CM/VM quadrature sinusoidal oscillator employing two VDCCs, two grounded resistors and two grounded capacitors has been proposed.Use of grounded resistors and capacitors make the proposed configuration suitable for monolithic integration.The presented circuit configuration enjoys several advantageous features expected from a dual mode quadrature oscillator such as: independent electronic tuning of FO and CO, independent resistive control of FO and CO, explicit quadrature current outputs at high impedance terminals, quadrature voltage outputs at low impedance terminals, independent control of FO even under the influence of VDCC port parasitics, low active/passive sensitivities, good frequency stability and low non ideal effects.The SPICE simulation results confirm the validity of theoretical predictions.
Transient response of I 1 , I 2 and I 3 .Steady state response of I 1 and I 2 .
Steady state response of I 2 and I 3 .
Steady state response of V 1 and V 2 .

Fig. 10 :
Fig. 10: Variation of of output current I 2 amplitude with resistance R 2 .