Ultra Low Power High Speed Domino Logic Circuit by Using FinFET Technology

Scaling of the MOSFET faces greater challenge because of extreme power density due to leakage current in ultra-deep sub-micron (UDSM) technology. To overcome this situation double gate device such as FinFET is used which has excellent control over the thin silicon fins with two electrically coupled gates that mitigate shorter channel effect and exponentially reduce leakage current. The present work utilized the property of FinFET in domino logic, for high speed operation and reduction of power consumption in wide fan-in OR gate. The proposed circuit is simulated in FinFET technology by BISM4 model using HSPICE and 32nm process technology at 25 ◦C with CL =1 pF and 100 MHz frequency. For 8 and 16 input OR gate in SG mode, we saved an average power of 11.5 % and 11.39 % in SFLD, 22.97 % and 18.12 % in HSD, 30.90 % and 34.57 % in CKD, respectively; while for that in LP mode, we saved an average power of 11.26 % and 15.78 % in SFLD, 19.74 % and 17.94 % in HSD, 45.23 % and 34.69 % in CKD respectively.


Introduction
Scaling of CMOS technology is needed to improve device density and performance of the circuit.However difficulties in scaling of bulk CMOS are the prime thrust for developing a new architecture with a double gate which has higher scalability than single gate transistor, because both the gates control the fin potential over the body [1].It is important to develop an efficient technique to overcome shorter channel ef-fect and; power consumption as well as maintain the performance of the circuit.As shown in Fig. 1(a) and Fig. 1(b), double gate FinFET has an excellent control over thin silicon body which suppresses the shorter channel effect in sub 22 nm and beyond, and reduces the sub threshold and gate oxide leakage current [2].
FinFET technology has a wide range of characteristics.
The gate terminal can be shortened to replace CMOS technology in SG mode.In Independent Gate (IG) mode, two gates work independently, for better control over the silicon fin.The fin body of a double-gate device is typically undoped or lightly doped; therefore, enhancement of carrier mobility and device variations due to doping fluctuations are reduced.To increase the ION current of the FinFET the number of fins in the FinFET can be increased, which in turn increases the current driving capability.
The paper is organized as follows: Section 2. describes the FinFET technology for DSM.Section 3. presents the literature review of high speed domino circuits.Section 4. depicts the proposed circuit for low-power and high-speed operation.Section 5.
describes the simulation results and discussion using HSPICE EDA tool, and finally, the conclusion is presented in Section 6.

FinFET Technology
The main advantage of the FinFET structure is the fabrication of double gate using a single lithography and etch step.A gate is easily wrapped over the silicon fin.As the front and back gate have different doping profile, they operate independently according to the requirement [3].One of the main challenges in developing FinFET over bulk-CMOS is the high current drive by reducing parasitic resistance, and the source drain region requires re-engineering.Owing to the vertical gate structure, the width of FinFET is quantized, and the fin height is determined by minimum transistor width (W min ).When two gates of a single-FinFET is tied together as shown in Fig. 1(a), W min is effective channel width: effective channel length: where H f in is the height of the fin, T f in is the thickness of the silicon body, and L ext is the extension of fin from gate to source or drain terminal [4].To suppress shorter channel effect and enhance the area efficiency in FinFET, the fin thickness should be much lower than the fin height [5], [6], [7].Table 1 shows the parameters that must be taken into consideration during the simulation of N-FinFET and P-FinFET.
FinFET works in three different modes according to the supply of front and back gates, namely Short Gate (SG) mode, Low Power (LP) mode and Independent gate (IG) mode as shown in Fig. 2 [8].
• SG mode -In this mode, the front and back gates are tied together with common supply voltage.The short gate is faster and has higher ION current.
• LP mode -In this mode, the front and back gates bias independently, and back gate is reverse biased for reduction of leakage current.
• IG mode -In this mode, both gates are connected to different inputs, similar to a two parallel transistors which reduces the area of the circuit.Biasing of the back gate of FinFET increases the ON state current (I ON ) and mitigates the OFF state current (I OF F ).I ON can be defined when V ds =0.8 V and V GS =0.8 V, where I OF F can be defined when V ds =0.8 V and V GS =0 V.A symbolic representation and biasing is shown in Fig. 3, FinFET has four terminals that's why we call it is 4T device.As shown in Tab. 2 and Tab. 3 following application of different biasing on the back gate of N and P FinFET, P-FinFET presented significantly lower leakage current than N-FinFET.Furthermore, it can be observed that with the increase in VBG of 4T P-FinFET from 0.6 to 1.6 V both the I ON and I OF F decreased, but the percentage of reduction of I OF F was much higher than I ON (reduction is 250x) from orignal [8].
Table 3 presents the value of I ON and I OF F calculated for V GB from -0.6 V to 0.4 V both I OF F and I ON increases but increment of I OF F is much higher than I ON current.The simulation results indicate that the driving capability of N-FinFET was higher than that of P-FinFET when V BG was reverse biased N-FinFET presented greater advantage than P-FinFET when the back gate biased, which significantly reduced the leakage current in FinFET based digital circuit.Nevertheless P-FinFET exhibited higher driving capability and decreased the sub-threshold leakage current [9].
Tab. 2: Results of I OF F and I ON of 4T P-FinFET for single Fin. V

Literature Review
Domino logic circuit is used in high-speed microprocessors, where speed and high performance are the prime concern with respect to scaling of technology.

Footless Domino Logic Circuit
Footless domino logic circuit is an existing domino logic circuit.The major difference between footless and footed domino logic circuit is the footed NMOS transistor which is placed below the evaluation network in footed domino logic circuit, and which is absent in footless domino logic circuit.The circuit diagram for footless domino logic circuit is shown in Fig. 4.

Footed Domino Logic Circuit
Footed domino logic is a general form of domino logic circuit.It is called so because of the presence of a footer transistor in the circuit.The footer transistor is generally an NMOS transistor and shows better noise and leakage tolerance because of leakage reduction due to stacking effect [6], [7].The circuit diagram for footed domino logic circuit is shown in Fig. 5.

High-speed Domino Logic Circuit
In high speed domino logic circuit current is drawn through the keeper transistor and evaluation network at the beginning of the evaluation phase.Thus current can be reduced on applying a clock delay at keeper transistor [10], this leads to high speed domino logic circuit shown Fig. 6.This arrangement does not affect the leakage current in the circuit; however, the extra clock delay consumes extra area and power, which is a big drawback of the circuit [11].
In High-speed domino logic circuit when the clock becomes high, M n1 is still off and M p2 is still on.Therefore, M p2 turns off the keeper transistor.After some delay in inverter M p2 turns off.Now, if the dynamic node remains high during the evaluation phase, NMOS is turned on which turns on the keeper transistor.Hence, at the beginning of the evaluation phase the dynamic node is afloat, and hence in the absence of keeper transistor, the evaluation node may be discharged for any noise at the input section.Furthermore the voltage at the gate of the keeper transistor is V DD -V tMn1 , which could provide a DC current flow through the PMOS keeper transistor and the NMOS network.

Conditional Keeper Domino Logic Circuit
In most of the high-speed timing performance schemes, input signals of the dynamic logic gates are ready just before or close to the start of the evaluation phase.In such situations the maximum time slot for any output transition is only a fraction of the total evaluation time, which takes half time period of 50 % duty cycle clock.Therefore leakage and noise exist unnecessarily for a long time at the output of the gate [12].In the conventional circuit a standard keeper transistor is which is turned on unconditionally at the start of the evaluation phase, and takes down the performance of the dynamic logic gate as shown in Fig. 7.The conditional keeper domino logic contains two PMOS keeper transistor circuits with variable strength.One keeper transistor has lower strength, while the other has higher strength [13].When the dynamic node is at high voltage M kp1 turns on to avoid the voltage drop at the dynamic node.If the dynamic node is still high, then after a certain amount of delay, during the evaluation phase, the output of NAND gate becomes low, thus turning on M kp2 .It must be noted that M kp1 is responsible for maintaining the state of the dynamic node, during the beginning of the evaluation phase, while M kp2 is responsible for it for the rest of the evaluation phase.Another type of domino circuit developed from CMOS technology is the diode footed domino logic (DFD), which reduces power consumption and delay of the circuit by inserting the mirror circuit below the evaluation network.By inserting the mirror, the path of discharge of the dynamic node increases as shown in Fig. 8. Thus, the dynamic node discharges slowly and removes the contention current between the dynamic node and evaluation network, improving the performance and robustness of the circuit [6], [14], [15].In Leakage Controlled Replica (LCR) modification is achieved over the keeper transistor by inserting a mirror circuit in parallel to the keeper transistor, which mitigates power consumption and area of the circuit, as shown in Fig. 9 [15].This circuit is helpful in improving the noise immunity of the circuit in evaluation phase [16], [17].
Several studies have been conducted on domino logic to achieve faster operation of the circuit and reduction of power consumption.In the present study, a new current comparison of domino (CCD) circuit has been proposed which enhances the performance of the circuit; and improves the UNG of the circuit by maintaining its robustness [18].Thus, our proposed circuit is a new class of domino circuit with lower power and high speed with constant delay of the circuit.
A recent addition to the different type of domino circuit is voltage comparison circuit which has been developed, with domino circuit for wide fan in gate.In present study, the voltage swing of the dynamic node has been reduced by decreasing the power consumption  by heavy swing of the switching capacitance [14].All simulations were performed with 90 nm technology for 64-bit OR gate, which saved 36 % power and provided 2.32x noise immunity.

Proposed Circuit
In proposed circuit we have modified the keeper transistor.For the reduction of contention between the keeper and evaluation network, we split the keeper transistor into two for proper strength.Furthermore, by sizing the keeper transistor we reduced the power and delay of the domino circuit.
As shown in Fig. 10 we use Ultra Low Power Stacked Design (ULSD) which is a combination of PMOS and NMOS.ULSD achieves higher reduction of leakage current, when compared with other standard logic.Our proposed circuit works in two phases.In first phase when the clock pulse is 0, the circuit remains in pre-charge phase, which charges the dynamic node and the output of the logic is always 0. During second phase the circuit enters the evaluation the clock pulse becomes 1, and if one of the inputs of the OR gate is active then the dynamic node is discharged.Subsequently transistor MN1is is turned ON, dynamic node easily discharges through MN1, and also MN2 transistor is turned ON as gate voltage is high on transistor MN2, dynamic node discharges through evaluation and MN1 transistor slowly due to gate delays, hence two invertors are connected in series at a gate of MN1 to provide delay in making MN1 ON.This will save power of the circuit.As shown in Fig. 11 transistors MN3 and MP4 try to discharge the dynamic node towards the ground.The main function of this transistor is to draw the contention current of the PMOS keeper, which also speeds up the discharging process of the capacitor at the dynamic node.At the beginning of the pre-charge phase the pre-charge transistor is in active mode and the voltage at the dynamic node will be at 0 V.This 0 V is fed to the inverter as an input which makes the output of the inverter as V DD .The modification of the keeper transistor helps in discharging the dynamic node, and the charge stored over the dynamic node floats, when all the inputs of the OR gate are disconnected.By providing a proper stacking with the help of ULSD transistor, which helps in improving the UNG of the circuit, power consumption is reduced and speed is enhanced by using FinFET technology in different mode.The transistors MN3, MP4 and MN2 are arranged as stack transistors and provide a stacked effect in pull down network, and by reducing the leakage current simultaneously a proper logic level is achieved as shown in Fig. 12.

Simulation Results and Discussion
The simulation results were obtained by using BISM4, HSPICE model at 32 nm technology, by using Predictive Technology Model (PTM).In FinFET technology, the circuit is simulated in SG and LP modes with 0.8 V supply at 100 MHz frequency.All simulations were performed at room temperature of 25 where W and L denote the transistor size, and µ n , µ p are the mobility of electron and hole respectively [2].
Table 4 and Tab. 5 show the comparison of the average power, delay and PDP using FinFET technology.It can be observed that the proposed FinFET based circuit shaved maximum power, with an average power 11.25 % and 11.39 % in FLD, 18.76 % and 18.12 % in HSD, 30.90 % and 34.57% in CKD for 8 input OR gate in SG and LP modes of the FinFET technology.Furthermore, the saving of the delay was 24.31 % and 13.18 % in FLD, 53.19 % and 46.79 % in FDL, 20.60 % and 10.34 % in HSD, 29.34 % and 24.99 % in CKD for 8 input OR gate in SG and LP mode of FinFET technology respectively.The saving of the average power of the proposed circuit was 15.60 % and 14.86 % in DFD and 13.93 % and 17.64 % in LCR for 8 and 16 input OR gate respectively.Subsequently, the Unit Noise Gain (UNG) of the circuit was calculated (Tab.6) by applying narrow width of pulse having 50 ps and measuring the amplitude at the output of the circuit.If the amplitude obtained at the input and output was the same, we considered as the UNG of the circuit.UNG can be defined as the amplitude of the input noise that causes the same amplitude of noise at the output: UNG is inversely proportional to the leakage current.As shown in Tab.6 the proposed circuit presented higher UNG than the existing circuit, which was, 0.382 in SG mode and 0.532 in LP mode.However, the UNG was lower in LP mode due to reverse biase of the pull down network of the circuit which reduced the leakage power of the circuit.
In the standby power, the evaluation network of the circuit is turned off and the precharge transistor comes into the existence.Subsequently, the PMOS of the transistor turns on and charges the dynamic node.As dynamic node does not acquire any path to discharge the voltage, the volatge is floats over thedynamic node and this power is known as standby power.As shown in Tab.6, the proposed circuit, achieved maximum saving of standby power with 37.0 % and 96.4 % CKD in SG and LP modes of FinFET technology, respectively.It can be noted that the saving of standby power was very high in LP mode when compared with that in SG mode due to reverse bias of the pull down network which increased the threshold voltage of the transistor and reduced the leakage power of the circuit.
Furthermore, calculation of the Evalation delay revealed that the proposed circuit saved maximum delay (Tab.6), which increased the speed of the circuit.When CLK=1 the circuit entered the evaluation phase, the dynamic node tried to discharge through the evaluation network and the current flowed from minimum resistance path.The time taken by the dynamic node to discharge is known as evaluation delay.The proposed circuit presented improved evaluation delay when compared with other existing circuits in low-power circuit design.

Power Analysis
If there are many pulses, then buffer frequently turns on and off.The power consumption of the logic circuit in conventional circuit can be given as follows. where T on is the time when the input logic is on, T of f is the time when he input logic is off, K is the probability of the state that the input logic changes in a unit time, C dyn is the capacitor in dynamic node and V noise is the pulse in dynamic node.
Figure 13 shows the comparison of CMOS and Fin-FET Technology, from the Fig. 12.We observe that power consumption of CMOS technology is huge in comparison with SG and LP mode of FinFET technology this is because, FinFET technology has three dimensional structure, where current flows vertically, where CMOS is a planar device, where current flows horizontally with respect to the channel.In Fig. 14 it is observe that FinFET technique have lower delay than CMOS and proposed circuit save power and delay with other existing circuit for 8 input domino OR gate.

Conclusion
In this paper we discussed about FinFET and recent domino circuits design to enlighten our knowledge.
Here in UDSM technology FinFET based domino logic circuit is proposed.Various existing domino logic circuits along with our proposed circuit were simulated we observed that FinFET based domino circuit is faster and consume less power than the bulk CMOS device.The new circuit technique was found to reduce the power consumption up to 32 % and 38 % without sacrificing the speed of the circuit.The proposed nique can be applied on high performance, low power applications, where leakage is a major concern such as microprocessors, memory units, and other portable devices.Thus, FinFET technology can completely replace CMOS by maintaining the law of technology scaling.Moreover, FinFET technology reduces the size of the transistor by up to 10 nm, the process parameters such as voltage and temperature can be varied with the scaling of technology.In future, we can implement next-generation domino circuit using carbon nanotubes, which has advantages such as low power, high speed and smaller area of 10 nm -7 nm.
c 2016 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING

Fig. 12 :
Fig. 12: Transient characteristics of the proposed two input Domino OR using HSPICE in FinFET technology.
Results of I OF F and I ON of 4T N-FinFET for single Fin.
Tab. 4: Calculation of average power, delay and PDP for 8 input OR gate in SG and LP mode using FinFET technology.Calculation of average power, delay and PDP for 16 input OR gate in SG and LP mode using FinFET technology.Calculation of UNG, standby power and evaluation delay for 8 input OR gate in SG and LP mode using FinFET technology.