Analysis and Sliding Mode Control of Four-Wire Three-Leg Shunt Active Power Filter

In this paper, the analysis and the sliding mode control application for a shunt active filter is presented. The active filter is based on a three-leg split-capacitor voltage source inverter which is used to compensate harmonics and unbalance in the phase currents, and therefore to cancel neutral current. The proposed sliding mode control is formulated from the multivariable state model established in dq0 frames. The selection of the sliding mode functions takes in account simultaneously, the current tracking and the dc-bus regulation and balancing, without the need of outer loops for the dc-bus control. A particular attention is given to the sliding mode functions design in order to optimize the convergence of the zero-sequence error and the dc-bus voltage unbalance. The effectiveness of the proposed control has been verified through computer simulation where satisfactory results are obtained over different conditions.


Introduction
Three-phase four-wire active power filters are nowadays one of the most popular solutions for power quality conditioning in four-wire distribution power systems [1].
The purpose of using a four-wire active power filter is to perform harmonic current suppression, reactive power compensation.In addition, the active filter is called to compensate load unbalance and to mitigate harmonic current in the neutral wire [2], [3], [4], [5], [6].
The implementation of such a filter usually uses a four-leg full bridge voltage source inverter that provides neutral current through the fourth leg [1], [2], or a three-leg split-capacitor voltage source inverter providing the neutral current through the fourth wire connected to midpoint of the dc-bus formed by two cascade connected capacitors [4].This implementation can also be realized by three single-phase converters [6].In the present paper the split-capacitor configuration is preferred especially for its reduced number of semi-conductors, which is economically and technically an advantage.However, for this configuration it is often difficult to compensate all zero-sequence currents, and to cancel perfectly the dc-bus unbalance simultaneously.This is due to the fact that all the zero-sequence compensated current flows through the dc-bus capacitors causing rise to voltage unbalance between the capacitors in that bus [4], [7].This phenomenon is accentuated when compensated currents are highly distorted and unbalanced.
The control strategy is important to enhance the performances of the active filter.This control generally includes three steps: identification of the undesired components from the load currents, dc-bus voltage control and finally current tracking.A large number of control strategies have been reported in the literature for these different steps [8], [9], [10], [11], [12], [13].However, for current tracking the sliding mode control seems to be the most appropriate because of the time varying nature of the converters [14], [15], [16], [17].The main advantage of this kind of control resides in its very fast response, especially during the transient regimes even if the system state is so far to the desired surface.Consequently, the system dynamic is very high during the reaching phase.Furthermore, the simplicity and the robustness of the sliding mode for uncertain sys-tems make it particularly attractive in despite of the chattering phenomenon [18], [19].The sliding mode approach has proved its qualities for active filter applications in many contributions [20], [21], [22], [23], [24], [25]; however, most of these works deal with three-wire or four-wire four-leg active filters.
The dc-bus voltage control is of a crucial importance because it directly affects the performance of the active filter [26], [27], [28].In case of the three-leg splitcapacitor based active filter, this control consists in forcing the voltage source inverter to absorb additional currents from the mains to achieve voltage regulation and balancing in the dc-bus.Due to this effect the quality of the source current will depend strongly on the efficiency of the dc-bus control.
All along this paper, the attention is focused on the current tracking and the dc-bus control.A sliding mode control is proposed to control the three-leg four-wire shunt active filter.To formulate the sliding mode control, the space model of the active filter is developed in dq0 frames.The proposed approach in this paper avoids the use of multiple separate loops usually used to track the compensating currents and to regulate the dc-bus voltage.In fact, sliding mode functions are proposed to control the multivariable system as a whole including current tracking, dc-bus voltage regulation and dc-bus balancing.Thus the convergence of the state errors ensures all these objectives at the same time.Some difficulties have been encountered to satisfy simultaneously the zero-sequence tracking and dc-bus unbalance; however, by favoring the current convergence, this has been surmounted.
The layout of the paper is as follows: after this introduction, a description of the active filter is presented and a dynamic model is given.In section 3. , the active filter control is globally described while the aim contribution is presented in section 4. .The validation of the proposed control is carried out in section 5. through computer simulations under hard different load conditions.Finally the paper is ended by a conclusion.

Shunt Active Power Filter Description and Modeling
The three-phase four-wire active filter connected to the grid is shown in Fig. 1.The power circuit uses a threeleg voltage source inverter (VSI) coupled via inductor L c which supposed to have a small internal resistance r c .Two identical capacitors C are cascade connected to form the dc-side of the active filter.The midpoint of the dc-bus is connected to the neutral wire of the grid to form the fourth wire.The losses in each capacitor are represented by the resistance R. The nonlinear load is a combination of three-phase and single-phase rectifiers resulting in nonsinusoidal and unbalanced load current i Labc .Therefore, a distorted current i Ln flows in the neutral wire.
The role of the active filter can be resumed in two objectives: First, to inject in the point of common coupling three-phase compensating currents i cabc to cancel harmonics from the three-phase currents in the source side i sabc and to maintain the dc-bus voltage regulated at a predefined value.The second objectives is to inject a compensating current i cn from the midpoint of the dc-bus to cancel the neutral source current i sn , and to minimize voltage unbalance between the two capacitors of the dc-bus.The dynamic model of the shunt active filter of Fig. 1 in dq0 reference frames can be expressed by the following differential equations: where i cd , i cq , i c0 denote the dq0-axis compensating currents, v dc , the total dc-bus voltage, i.e v C1 + v C2 and ∆v dc , the dc bus voltage difference, i.e v C1 − v C2 .
The dq0 voltages at the point of common coupling are denoted by v d , v q and v 0 .ω represents the fundamental pulsation of the mains voltage, and finally u d , u q , u 0 denote the control variables of the system.

SAPF Control
In order to compensate correctly the undesired component, the references for active filter ac currents i cd , i cq , and i c0 must be identified first.A large number of contributions dealing with the computation of reference currents can be found in literature.The most common way is the time-based extracting from the load current, indirectly by using the pq-theory or directly by using the synchronous method [13].The last one seems more adequate since the state model and the control are designed in the dq0 frames.The principle of this method consists in transforming the abc load currents to dq0 load current at the fundamental frequency i Ld , i Lq , and i L0 , then except the continuous component on the d axis īLq , all the other components are to be compensated, or in other words, to be injected in the opposite phase.Thus, the current references in dq0 frames are i * cd = − ĩLd , i * cq = −i Lq , and i * c0 = −i L0 .In addition to these currents, necessary to cancel the harmonics and reactive power of the load, the active filter absorbs an additional active current to compensate its losses and to regulate dc-bus voltage v dc .This current is usually determined by a PI controller in outer loop which computes an additional active current added to the reference current on the d axis.As particularity for the split-capacitor active filter, the dc-bus balancing is also necessary to ensure compensation objectives [4], [8], [24], [26].In fact, if the active filter is called to compensate zero-sequence current, one must expect a dc-bus unbalance as shown by the last subequation in Eq. ( 1).This unbalance manifests as ripple which may contain average component.Consequently, a dc-term can be observed in the source currents, which increases certainly the THDs of the compensated currents.However, the same equation shows that, if the unbalance ∆v dc is forced to zero, the compensating zero-sequence current is also forced to zero, and then the neutral source current cannot be canceled, which contradicts the main objective.Thus, as conclusion, a compromise is necessary in the control design, by authorizing an acceptable ripple and possibly a slight dc-offset in dc-bus, all with compensating all the zero-sequence current.

Sliding Mode Control
For the formulation of the control design, the nonlinear multi-input multi-output (MIMO) model in Eq. ( 1) is rewritten as follows [15]: R 3 is the system output vector.The function f (x) ∈ R 5 is a smooth vector usually addressed as the drift vector field, and G(x) ∈ (R 5 × R 3 ) is called the input matrix, whose columns represent also smooth vector fields.Thereafter, the expressions of f (x) and G(x) are: To design the sliding mode control of the shunt active filter, recalling that the objective of this control is to track the reference currents on the axes dq0; i * cd , i * cq and i * c0 , and to maintain the absolute voltage v dc across the dc-bus constant in the steady state at its reference value v * dc , and finally to reduce as much as possible the dc-bus voltage difference ∆v dc without affecting the compensation of the zero-sequence current.
To accomplish the above mentioned objectives, we design three sliding mode functions with proportional actions as follows: where The sliding mode function on the d-axis takes in account the i * cd tracking, and the dc-bus voltage v dc regulation.Notice that this regulation, represented by the second term in σ d is often done by forcing the active filter to absorb or to inject an additional active current from or into the mains.The sliding mode function σ q is to track the reference i * cq , and finally, on 0-axis, the sliding mode function will be used to track the reference currents on that axis and to control the dc-bus voltage difference ∆v dc .Reformulating the problem, the objective now is to force the function σ to zero, thanks to the control actions u.In other words, to force the state trajectory to evolve over the sliding surface S given by: This objective is usually obtained by using a control law of the form: where û = −sign(σ) is a switching component that pulls the trajectory towards the sliding surface, and u eq is a smooth component that approximates a control law where the net change of the sliding surface is zero, then the last component is valid only on the sliding surface S.

Equivalent Control
The existence of the sliding mode control is conditioned by the existence of the sliding mode equivalent control.Assume that after a certain time, through the control actions, the state of the system reaches the surface defined by σ = 0 and stays on it at any time.Thus, the time derivative of the switching mode function σ must be also zero, and then, the following invariance condition is driven which can be written as: If this condition stills verified after reaching the sliding surface, then by solving Eq. ( 9) for u, a smooth control law defined as the equivalent control can be imagined and established as follows: where, As stated above, this smooth control is only defined when (σ, σ) = (0, 0), then it is valid only on the sliding surface, and can be seen as the approximation of the control u where the net change of the sliding surface around this one tends to zero.
To ensure the equivalent control existence, one must ensure that the matrix L G (x) is invertible.This one is given by: Thus, as condition for equivalent control existence, all the diagonal entries must be non zero, then, one can write: Moreover, each entry in the equivalent control vector must be bounded within [-1,1].

Sliding Mode Stability
To ensure sliding mode stability, the Lyapunov's approach is often used [15], [30], [31].In this way, let suppose the following candidate function: To ensure sliding mode stability the function V must verify the following conditions: The quantity V represents the distance of the state x to the sliding surface S.This distance is precisely zero over the surface, i.e when σ = 0 and positive otherwise, i. e. when σ = 0.In addition, this distance tends to infinity when |σ| tends to infinity.Thus, a sufficient condition for the stability in the sliding mode operation is that, when the distance V is not zero, it must be decreased.In other words, when V (σ) > 0, its time derivative must be negative, then one can write the necessary condition for the sliding mode stability as: Substituting Eq. ( 9) in Eq. ( 15): In other form: Substituting Eq. ( 10) in Eq. ( 17) the following condition is driven After development, this condition is written as: This can be rewritten more adequately as: c 2015 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING Since σ k sgn(σ k ) and v dc are positive, the last condition can be restricted to: Which can be always verified by choosing the gains k 1 and k 2 such that: According to Eq. ( 19), we can see that V (σ) < 0, which implies the attractiveness of the sliding surface.Moreover, we can see that lim σ→0 V (σ) = 0, and then the surface is invariant.
When the sliding mode occurs, σ = 0, the tracking behavior of the system dynamics on the d-axis is determined by the following equations: Thus, the dc-bus voltage convergence is proportional to the current convergence on the d-axis.However, it is preferable to set k 1 enough larger than k 2 to ensure fast convergence of the current.The condition Eq. (23) shows that the sliding mode stability is independent of the gain k 3 .Effectively, it has been observed through simulation tests that this gain does not affect the stability.However, the zero-sequence current tracking and the dc-bus unbalance are directly affected.To design this gain, let us consider the following equation, valid when the sliding mode occurs: Notice that it is assumed that ∆v * dc = 0.In this equation the gain k 1 is already fixed, thus, if k 3 > k 1 , the convergence of ∆v dc is faster than the convergence of (i * c0 − i c0 ).This will result in very small dc-bus unbalance (∆v dc → 0), but it is not the case for (i ) is faster, and will result in perfect zero-sequence current tracking (i s0 → 0), but a significant ripple and dc-offset remains in ∆v dc .Thus a possible strategy to design the gain k 3 consists in allowing an admissible dc-bus unbalance (∆v dc ) adm (for example 5% of v dc ), and a small current error (ε 0 ) adm = i * c0 − i c0 , and then in ensuring convergence of Eq. ( 25) to the point ((ε 0 ) adm , (∆v dc ) adm ).Thus the gain k 3 can be chosen as follows:  It is clear that the zero-sequence tracking error is necessary to design k 3 .Equation (26) shows also that naturally k 3 < k 1 , then zero-sequence error converges faster than dc-bus unbalance.

Results and Discussion
The effectiveness of the proposed control has been verified through computer simulations.The system parameters are given in the appendix.The load is con- stituted in a three-phase thyristor rectifier and single phase diode rectifiers, resulting in nonsinusoidal and unbalanced currents.The system control diagram is represented in Fig. 2. Two simulation tests are carried out; In the first test, the firing angle α of the thyristor rectifier is set to zero.For the second test this angle is set to 45 • , increasing therfore the THDs of the drawn currents.For the both tests, two load changes are voluntarily created at 0.1 and 0.2 s to verify the tracking performances.

Simulation Results (α = 0 • )
The dc-bus total voltage and unbalance are shown in Fig. 3. First, one can observe a very fast dynamic response during the transient state.When the load current increases suddenly, the dc-bus voltage decreases, and when the load current decreases this voltage increases.However, in both cases this voltage variation does not exceed 4 % of v dc .Moreover, it reaches the reference value in very short time (about one cycle).
During the steady state a slight ripple (about 5 V) endures in v dc , but the average value stays constant and equal to the reference value.The dc-bus unbalance ∆v dc is also, satisfactory.Although, during a transient period, the average value of this unbalance is not zero, its magnitude is insignificant (about 20 V).Moreover, this dc-term goes gradually to zero, and only a small ripple (less than 3 % of v dc ) remains after about 0.12 sec.Load, active filter and source currents are shown in Fig. 4. The load currents are nonsinusoidal and unbalanced resulting in neutral current.It can be seen that the proposed control is able to force the compensating current to track their references, during steady state and when the load changes.Thus, the objective of sinusoidal phase currents and canceled neutral one at the source side is ensured for different states of the load.In fact, in all cases the resulting THDs are less than 1.5 %, Tab. 1: Summarized simulation results obtained for α = 0   and the RMS value is almost the same for each phase.
For more details, the THD, the RMS values are summarized in Tab. 1, as well as the negative-sequence and the zero-sequence rates for different load conditions.The negative and zero-sequence rates are insignificant in the source currents; therefore, these currents are well balanced.Furthermore, in Fig. 5, the a-phase current and voltage are represented, to show that the source current is also in phase to the corresponding voltage.
Figure 6 shows current spectrums for different load changes.These spectrums show that the whole undesired harmonics are well canceled.However, during the period [0, 0.1 s], one can observe that a slight dc-term (harmonic 0) appears.This is due to the fact that during this period the dc-bus unbalance has non-zero average value.Notice also that due the dc-bus ripple, the third harmonic seems to be remaining, but with small value (about 1.5 %).

5.2.
Simulation Results (α = 45 • ) During this test, the firing angle is voluntarily increased to observe the effectiveness of the control under hard polluted load currents.The different results are shown in Fig. 7, Fig. 8, Fig. 9 and Fig. 10.Naturally, the load currents are now more distorted, resulting in  increased THDs; however, one can observe that almost the same performances are conserved as in the first test.The dc-bus voltage control conserves the same dynamic reponse during transient regime and against load change.It should be noticed that the dc-bus unbalance is relatively more significant during the transient regime, but remains acceptable (about 40 V) and it tends gradually to zero.For the phase and neutral currents, satisfactory results are also observed as shown in Fig. 8.All the THDs are less then 3.5 %, which agrees with the IEEE 519 standards.The currents spectrums in Fig. 10 show that the whole harmonics are canceled, and the dc-term appearing for t < 0.

Conclusion
The work presented in this paper proposes a sliding mode control for a three-leg voltage source inverter based four-wire active filter.The difficulties of the dc-bus voltage control in a split-capacitor active filter have been analyzed.The developed sliding mode control was aimed to be able to track compensating cur-rent reference, and to regulate the dc-bus voltage and unbalance simultaneously.All this without using any control loop for the dc-bus voltage.The performances of the proposed control have been studied under various conditions.The obtained results have shown very satisfactory performances to track the compensating reference currents and to reduce THDs of the source currents, and therefore to ensure a sinusoidal balanced current and a zero neutral current, even under hard polluted nonlinear currents.It is also shown that the controller is able to ensure very high dc-bus voltage dynamic in the transient state, and against load change.
During the steady state, excellent dc-bus voltage regulation has also been observed.Furthermore, the proposed control was able to make a compromise between the zero-sequence current tracking and dc-bus voltage unbalance compensation.

Fig. 2 :
Fig. 2: Control block diagram of the shunt active filter.

Fig. 4 :
Fig. 4: From the top to the bottom; three-phase load current, three-phase compensating current, three-phase source current, neutral load current and finally, neutral source current (α = 0 • ).

Fig. 6 :
Fig. 6: Current spectrums; from top to bottom, phases a, b and c.From left to right; before load change, after the first load change, and finally after the second load change (α = 0 • ).

Fig. 8 :
Fig. 8: From the top to the bottom; three-phase load current, three-phase compensating current, three-phase source current, neutral load current and finally, neutral source current (α = 45 • ).

Fig. 10 :
Fig. 10: Current spectrums; from top to bottom, phases a, b and c.From left to right; before load change, after the first load change, and finally after the second load change (α = 45 • ).
1 s remains acceptable.The detailled results for this test are recapitulated in Tab. 2. Tab.2: switch-mode power supplies.Journal of Circuit Systems.1995,vol.5,iss.3, pp.337-354.ISSN 0218-1266.DOI: 10.1142/S0218126695000217.as a teacher at the Institute of Electrical Engineering and Electronics, Boumerdes, Algeria, and since September 2013, he has been working as a senior lecturer and research team member in the LMER laboratory at the department of electrical engineering, university of Bejaia, Algeria.His research area includes active power filtering, FACTs and power system.He received the engineer diploma in electrical engineering from the University of Bejaia in 2005.In 2008 and 2012, he received the M.Sc.and the Ph.D. degrees respectively from the University of Batna, Algeria.Since February 2011, he has been working as a senior lecturer and a research team member in the LMER laboratory at the department of electrical engineering, university of Bejaia, Algeria.His research area includes electric machine control, renewable energies and FACTs.