Transition Based Synthesis with Modular Encoding of Petri Nets into FPGAs

The paper describes a new method for the synthesis of the application specific logic controllers, targeted into the FPGA. The initial steps of the proposed control algorithm rely on the notion of a Petri net, which is an easy way to describe parallel processes. The algorithm is oriented on transition based logic description. It allows easy analysis of dynamics and functioning of the circuit. The logic circuit is also decomposed into logic blocks responsible for particular functions. It leads to the compact implementation with usage of different kind of logic elements like. Additionally such decomposition allows easy analysis of circuit.


Introduction
A Petri net (PN) [10], [9] is one of the most popular models used in formal design and synthesis of the application specific logic controllers (ASLCs) [13], [15], [6].The digital design of such controllers is very often implemented using field programmable gate arrays (FPGAs) [1], [15], [2], [16].The most typical implementation of Petri nets in the FPGA devices uses the one-hot local state encoding method, where each place is represented by a flip-flop [11].Such approaches are oriented towards places based logic description.Additionally, this approach requires hardware implementation of a large number of logic functions and flip-flops included in logic blocks.
In this paper we propose a new method for the synthesis of a Petri net.To allow its effective synthesis, the Petri net is initially converted into Petri macronet [9], [14].The proposed algorithm is oriented towards transition based logic description.It means, that combinational equations describe transitions [5] in opposite to classical algorithms where they describe places [4].It easy allows to analyze the dynamics of logic controller by exporting variables that describes transition in Boolean algebra.Additionally, the operations are encoded with a minimal-length binary vector.This encoding allows the realization of logic circuit in compact way.A microoperation decoder can be implemented with the use of embedded memory blocks of an FPGA [12].It permits the stable work of whole controller.

Petri Net
A Petri net [10], [9] is defined as a triple: where: • P is a finite non-empty set of places, P = {p 1 , . . ., p M }, • T is a finite non-empty set of transitions, T = {t 1 , . . ., t S }, • F is a set of arcs (from places to transitions and from transitions to places): F ⊆ (P × T ) ∪ (T × P ), The sets of input and output transitions of a place p m ∈ P are defined respectively as follows: Sets of input and output places of a transition t s ∈ T are defined respectively as follows: A marking of a Petri net is defined as a function: For a given place p m the function M (p m ) returns the number of tokens in p m .A place or a set of places is marked if it contains a token.A transition t s can be fired if all its input places are marked.Firing a transition removes one token from each input place and puts one token in each output place.When the initial marking M 0 is additionally specified, the Petri net can be represented as a tuple: (2)

Interpreted Petri Net
A Petri net enhanced with an additional feature for information exchange is called an interpreted Petri net [9].This exchange is made by use of binary signals.
Interpreted Petri nets are used as models of concurrent logic controllers.
The Boolean variables occurring in the interpreted Petri net can be divided into three sets: • Z is the set of internal communication variables (usually not used, with Z = ∅).
An interpreted Petri net has a guard condition ϕ s associated with every transition t s .The guard condition ϕ s is defined to be a Boolean function of a subset of variables from the sets X and Z.In a special case, the condition ϕ s can be defined as 1 (always true).Now, a transition t s can be fired if all its input places are marked and the current value of the corresponding Boolean function ϕ s is equal to 1.
The conjunction ψ m associated with a place p m is an elementary conjunction of positive literals formed from output variables from the set Y .If the place p m is marked, the output variables from corresponding conjunction ψ m are set and other variables are reset.The conjunction ψ m correspond to microinstruction (µI).

Macro Petri Net
Macro Petri net is a Petri net where part of the net (subnet) is replaced by one macroplace [9].It allow to enhance Petri nets with hierarchy [7] and it simplifies algorithms of coloring and verification of Petri net.There are many classes of subnets that could be replaced by macroplace, for e.g.: • State machine subnets [10], • Two-pole blocks [9], • Parallel places [10], • P-blocks [9].
These classes create to many possibilities of merging Petri net into macro Petri net.For the synthesis purpose, the best solution is application of mono-active macroplaces [9].This is macroplaces that have one input and one output and consist of only sequential places.Only Petri macronets with such macroplaces will be used in this article.

Idea of Synthesis Method
The idea of proposed synthesis method is based on the modular encoding of places together with functional parallel decomposition of the Petri net-based logic circuit [4].The novelty of this approach is that places are encoded with use of minimal length code separately inside each macroplace and macroplaces are encoded with use of one-hot encoding.The state of Petri net is determined by concatenation of these codes.Combinational circuit is oriented towards transition generation, and output variables (names of particular microoperations) are placed in configured memories of FPGA.It leads to realization of a logic circuit in double-level architecture (Fig. 1), where the transition coder (TC) of first level is responsible for activation of the transitions: The register block (REG) holds a current state of Petri net in the register (RG).It also has additional custom combinational logic (LOGIC) connected to its inputs.This logic is responsible for generation of the next state based on active transitions and current state: where Q is the set of variables used to store the codes of currently marked places and macroplaces.The internal custom combinational logic of the register also generates the code of microoperation: where Z is the set of variables used to store the codes of currently executed microinstruction.The second level decoder (D) is responsible for generation of microoperations based on microinstruction code and it is implemented using memory blocks.Their functionality can be described by function: Such approach allows to use logic elements and embedded memory blocks available in modern FPGA devices.
The entry point to the synthesis method is the interpreted Petri macronet.The outline of synthesis process includes following steps: The total required number of variables for encoding is equal to: where r o is a required number of variables for o-th macroplace: where P o ⊆ P is a set of places that are placed inside macroplace mp o .
To store the macroplace code we use Q 0 = {q 1 , . . ., q O } variables and to store the local place codes we use The process of encoding begins from assigning the one-hot codes to macroplaces.Then, places receive minimal length codes inside each macroplace independently.• Formation of logic equations.Logic equations describe Eq. (3) and Eq. ( 5) of combinational circuit TC and custom combinational logic LOGIC of register REG.The characteristic function of transition is defined as conjunction of conjunctions of all its input global places and guard condition: The function to generate the code of next place calculated by the custom combinational logic LOGIC is defined as: and the function to generate code microoperation is defined as: where P zρ is a set of global places conjunctions that generate microoperations Y u represented by the C o (Y u ) that has variable z ρ set to 1.
• Formation of memory contents.The memory content can be described as tables or as equations according to the function Eq. ( 6).In case of tabular description there is required to create O tables.
The table consists of two columns.First column is an address and it is described by variables The second column is a binary value (vector) of operations.It is based on value of output variables form the set In each line of the table, there should be placed a binary value with only these bits y n set that are in microinstruction Y u represented by code C o (Y u ) that equals to the address from the first column of this line.
• Formation of logic circuit and implementation.
This step describes the rules of design of the Petri net HDL model and its implementation into FPGA device.Here is applied a bottom-up approach.Conjunctions of places can be described using standard bit-wise operators.Then logic equations can be described with the use of these conjunctions using continuous assignments or procedural assignments as well as bit-wise operators.
There should be created a module for circuit TC with inputs X and Q and outputs T .The register REG should be described as R-bits register with an asynchronous set.The typical synthesis template can be used [3]. the decoder D can be described as processes with the case statement.As, the embedded memory blocks are synchronous, the sensitivity list of such processes includes only clock signal.The reset has to be realized as a synchronous one because typical memory blocks do not support any asynchronous control signal.To ensure that such a described module could be synthesized as a memory block it is required to set the value of the special synthesis directive.The syntax of this directive depends on FPGA vendor.The top-level module should describe connections of all components according to the block diagram presented in Fig. 1.Additionally the global reset and clock signals are connected to set and clock inputs of register and reset and clock inputs of decoder.The edge that trigs the decoder has to be opposite to the edge that trigs the register, and then operations are generated during only one clock cycle.The created model of logic circuit can be passed into third-party synthesis tool.

Example of Method Application
The method of Petri net synthesis, described in the previous section, is illustrated by its application on Petri net PN 1 (Fig. 2a).This Petri net describes control process of an industrial mixer of aggregate content and water [8].This Petri net is not complicated and it is a good example to illustrated a synthesis steps.
For the synthesis purpose it was compacted into Petri macronet (Fig. 2b).
Firstly, the places have to be encoded (step Modular encoding of places).There is O = 6 macroplaces, so it is required to use r 0 = 6 variables Q 0 = {q 1 , . . ., q 6 } to encode macroplaces.Macroplaces contains respectively 2, 1, 3, 1, 2, and 2 places, so it is required to use r 1 = 1, r 2 = 1, r 3 = 2, r 4 = 1, r 5 = 1, and r 6 = 1 variables {q 12 }, and Q 6 = {q 13 } to encode places inside each macroplace.In total, it is required to use R = 13 variables Q = {q 1 , . . ., q 13 } to encode all places.Macroplaces receive following one-hot codes K(mp o ) using variables from Q 0 subset: and places receive following binary codes K o (p m ) inside each macroplace using variables from corresponding Q o subset: As an alternative, the Gray code can be applied also for places.
Finally, the logic circuit can be described (step Formation of logic circuit and implementation) In our approach the VHDL was used.But in similar way it can be also described with the use of Verilog.The module for circuit TC (Fig. 3) uses input variables and     The module of register REG (Fig. 4) describes the logic of code changes and generate code of microinstruction.It also requires definition of conjunctions as internal signals.
It can be synthesized as embedded memory block if there is added special synthesis directive.In this file, there is such directive for Xilnix devices that sets bram_map attribute to yes.The top-level module (Fig. 6) describes connections of all modules.In our case it is cerated in graphical editor of Active-HDL environment.
The designed circuit is verified in Active-HDL environment with use of a test-bench.The test-bench is described in VHDL and it emulate one cycle of work of an industrial mixer.The simulation results are sown in the Fig. 7.

Summary
The paper presents a method of realization of application specific logic controller.A formal description of the method is then accompanied with a simple example.The specification of the control algorithm uses the notion of a Petri net, which allows an easy description of parallel processes.We note that it is possible to apply formal verification methods to test the algorithm.The proposed method of synthesis is based on transition based logic description of the logic circuit and modular encoding of places.It allows to extend formal verification methods by additional analysis the dynamics of the circuit.Additionally the logic circuit is
Modular encoding of places.The purpose of this step is to assign the shortest binary local code K o (p m ) to each place p m inside each macroplace mp o , where o = 1, . . ., O and it is an number of macroplace.Macroplaces are encoded by assigning the one-hot code K(mp o ) to each macroplace mp o .The global code C(p m ) of global place p m is determined as concatenation of these codes:

•
Formation of microinstructions.Let all microoperations create U different microinstructions Y u ⊆ Y , Υ = {Y 1 , . . ., Y U } in the Petri net.Let create O subsets Υ o ⊆ Υ, where Υ o consists only of microinstructions associated with places from set P o .• Encoding of microinstructions.All microinstructions are encoded by binary code C o (Y u ) separately in each subset Υ o .The number of variables used is ρ o = log 2 (|Υ o | + 1) .(10) To store this code we use Z o = {z ρ+1 , . . ., z ρ+ρo } (ρ = o−1 j=1 ρ j ) variables and Z = O i=1 Z o .The process of encoding is trivial, and it required to assign binary code C o (Y u ) to each microinstruction Y u ∈ Υ o starting from value 1.The value 0 is reserved for situation where considered place do not generate any microinstruction.Let assume that particular one microinstruction Y u can belong to several subsets.In such situation it will receive several codes.• Formation of conjunctions.Conjunctions describe macroplaces, places and global places.They are needed for easier form of Eq. (3) and Eq.(5) that describe digital circuit.The conjunction describing the macroplace mp o equals to the affirmation of variable q o ∈ Q 0 .This variable is equal to 1 in the code K(mp o ).The conjunction describing the place p m consists of affirmation or negation of variables q r ∈ Q o that are used to store the code K o (p m ) of this place.If variable q r is equal to 1 in the code K o (p m ) then affirmation of this variable is used otherwise its negation is used.The conjunction describing the global place p m consists of the macroplace mp o and the place p m conjunction.It corresponds to the code C(p m ).
decomposed into three logic blocks responsible for particular functions: dynamic generation of transitions, store the state of the controller and generate output control signals.It allows the compact implementation of logic circuit into FPGA device with usage of different kind of logic elements like: LUTs, flip-flops and embedded memories.Additionally such decomposition allows easy analysis of circuit functioning.