IMPLEMENTATION OF DIFFERENT VARIANTS OF TABLE-BASED FREQUENCY SYNTHESIZERS WITH QUADRATURE OUTPUT IN VHDL

This article describes the modelling and implementation of two different variants of direct frequency synthesizer, and evaluation of the performance of the finished design, in terms of memory and speed efficiency. The frequency synthesizer requirement comes from our complex radio transmission system design. The research activity has been focused on finding an optimal balance between simplicity, speed and memory consumption. The modelling was done in MATLAB environment in floating-point and fixed-point arithmetic, and the actual design was implemented and synthesized using the Xilinx ISE suite. The output has been connected to our customized radio front-end built on the Texas Instruments TRF2443 chip. The front-end output signal has been captured and compared with simulation results.


Introduction
With improvements in the performance of FPGA (Field-Programmable Gate Array) devices, it becomes important to implement the basic radio system parts in a digital domain.This enhances circuit design simplicity and also offers numerous opportunities for the later modification of the entire system into specific real-world scenarios.Multiple parts of the radio system can be implemented in a single chip, thereby enhancing the overall efficiency in hardware design.
As a part of complex radio transmission system design, we have implemented a direct quadrature frequency synthesizer in VHDL language for the Xilinx Virtex6 FPGA device, i.e. a synthesizer with the fixed table (sine 1 st quadrant table and full sine table).The theoretical part of the paper is dedicated to the precise description of the synthesizer transformation into the fixed point arithmetic.The practical part describes the implementation of the designed synthesizer circuit structure in VHDL language.

Direct Frequency Synthesizer Model
The frequency synthesizer supports multiple functions in the radio front-end of the digital transmission system.In particular, it reduces the frequency offset on the detection side that arises when the transmitter f (t) (t), or receiver carrier's frequency, f (r) (t), is not absolutely stable and slightly fluctuates in time.The frequency difference, f Δ (t) = f (t) (t)-f (r) (t), causes that the received signal, r(t), to be parasitically modulated by a harmonic signal,   , 2 t t f j e   of low frequency, even after analog quadrature demodulation.The impact is, that in the case of linear digital modulations it results in the rotation of constellation plane around its center.In order to mitigate this problem, it is necessary to mix the received signal once more with the anti-phase frequency When this frequency is low, it is possible to perform the signal processing digitally in FPGA or in DSP directly, in the receiver (after sampling of signal r(t) at the frequency T P satisfying the sampling theorem).
The functional block in the digital domain that suppresses the undesirable parasitic modulation is called the frequency offset synchronizer; it is composed of three functional parts.The first part, a digital mixer, is simply a pair of two multipliers -one multiplier is for the in-phase signal component r [n], and the second one for the quadrature component.The second block is an offset estimator that performs the computation of f Δ [n]\ from the received signal using prior knowledge of stochastic properties of an implemented modulation.The last block is a frequency synthesizer.The phase increment samples of estimated parasitic frequency are taken on its input from the digital integrator output of the offset estimator.It generates from them the frequency which is then fed into a digital mixer.
Another application area is a frequency multiplexing system, for transmitting several signals.
Here, a set of digital synthesizers in the digital domain creates a hierarchy of sub-carriers that are modulated by different transmitted signals.The whole wave packet is then modulated onto a single carrier.There is a complementary receiver block of the same set of synthesizers that demodulate the received signal back to the original components.
The last major area of application is modeling of terrestrial flat or frequency selective Rayleigh channel with fading.The channel fading is simulated using Jake's simulator composed of a set of frequency synthesizers.
The synthesizer output can be described by Eq. ( 1): Where φ[n] is the current content of the phase accumulator that performs the following integration φ Δ [n] represents the input phase increments.Let us denote the initial accumulator value as φ Δ [0]=φ 0 .According to the method of calculating the nonlinearity   . j e , the direct synthesizers can either be the sine table or the polynomial ones.In both cases, the entire period of the harmonic function parts of the nonlinearity of   . j e is expressed using a quarter period of a sine function.Depending on the value of the highest two bit number φ[n], which is called as a quadrant indicator, the quarter period may be either mirrored or assigned a negative sign.
Values of the quarter period sampled by specifically selected phase step are stored in the table in the memory synthesizer.This implementation approach contributes mainly to the enhancement of the speed and simplicity of the system design.On the other hand, disadvantages include both higher memory requirements and certain restrictions on generated frequencies resulting from the fineness of the phase step.On the contrary, it is a case of polynomial variant, where the sinus quarter period is replaced by a solid or semi-continuous polynomial approximation.There is a greater delay between samples y[n] and φ[n], because the calculation of the polynomial values takes some time, but the frequency accuracy is much bigger.
We begin to describe the implementation of a simpler synthesizer with the sine table.We characterize the synthesizer whose phase accumulator has a bit width,  b N .For the output, the following relation holds, . The quarter period must have just 4 so that the entire signal comes out a total of M φ phase values.Equation (2) (in floating point operations) can also be expressed in an analogous form: for fixed point operations.
The input (in the form of phase increment) then allows to change the current value of the phase φ q [n] according to the sampling theorem at maximum half period forward or backward.The values of the quarter sine table stored in memory of the synthesizer are determined by the Eq. ( 4) where N b +1 is a number of bits for quantization of the output signal ( The functions f(.) and g(.) transform a stored quarter period b q [l] depending on which quadrant the synthesis is currently running at.The function f(.) mirrors a table if necessary, and function g(.) changes its sign.

Circuit Structure
The memory synthesizer together with a detailed description of its outputs is shown in Fig. 2. The circuit implementation is shown in Fig.  with a maximum width of 10 bits (the introduced scalar will be considered as a decimal representation of binary numbers in two's complement notation, i.e. as a whole positive number).It is described in the scheme as PhaseIncrementIn and subsequently it is added to the current content of the phase accumulator.Its 10 bits wide output is then split into two parts.Lower 8 bits are the bases for calculating the address of a sinus quarter period memory and upper two bits represent a quadrant pointer.Since the cosine is shifted to sine by one quadrant , it is necessary to increment its quadrant pointer in its branch.In contrast, the quadrant pointer is left unchanged in the sine branch.The value of the lowest bit of both quadrant pointers (9 th bit) decides in the calculation of address whether or not the 8-bit base   n a ub will be mirrored (the scalar will be considered as a decimal representation of an unsigned binary number, i.e. as an integer).When the 9 th bit has log.'1' the 8-bit base   n a ub is mirrored.The mirroring process is implemented by using the XOR gate, where the base is negated, and the adder that gets incremented.This will give the address . When the 9 th bit is log.'0 ' the base is left unchanged and becomes directly to be resulting address . The upper bit of both quadrant pointers (10 th ) indicates a sign.The top carry bits of adders are generated by mirroring the base   n a ub and they will be denoted as the saturation bits.When the saturation bit has log.'1', the corresponding part is just at its maximum, i.e., at +1 or -1.It is clear (from Eq. ( 4)) that in the memory is stored only the sine table from 0 to min 4     and the sine maximum +1 is missing there.It is therefore necessary to generate it, if necessary.The saturation bits connected to a pair of OR gates behind the output registers are there for that purpose.The rest of the structure performs a sign change of a function if corresponding sign bit is in log.'1'.The total delay of the signal in the synthesizer is two clocks of ComplexEnvelopeClock.

VHDL Implementation and ISim Simulation
We have implemented the design in VHDL [3], [4] and synthesized the design using the Xilinx ISE 12.3 design suite.
The We used the VHDL's feature of generic declarations.Therefore, the synthesizers can be easily modified for different bus widths and precision.The entity contains ports for input, quadrature output, clock and reset and buses for interfacing with memory containing sine samples, which is external to the synthesizer.
The two variants of main processes are shown: Both processes are typical clocked circuits with asynchronous reset.An important part of reset is the setting of memory addresses to zeros for both cases.It is necessary because the synthesizer needs the data from memory ready (the memory is clocked) in the very next cycle after the reset is released.
The simple variant is first and it is quite selfexplanatory -the ph variable holds the current phase pointer and is combined with the input to address the memory containing the whole period of sine signal.This solution contains only a minimum logic circuitry needed to perform the correct memory addressing and relaying of output.The main disadvantage is the requirement of a large memory size that is needed to contain the whole sine period.The size of the memory, of course, rises with added precision in both time and amplitude.
The second variant logic scheme is much more complex, but we only need one quarter of the sine which subsequently leads to lower memory requirement.The ph variable is used as in the first case, but it is not used to address the memory directly.Instead of that, the two most significant bits are used to determine which quarter of the sine should be used and whether to invert the result sign.We call it as the quadrant pointer.Corresponding variables have the _qp suffix.The temporary vectors are used because of VHDL's inability to perform some types of conversions.The usage of other variables is mainly given by the programming comfort and could be avoided, but the code's readability would drop.
In order to be able to communicate with the device, a set of memories and UART controller are also implemented.This fact, of course, raises the number of used flip-flops.The implementation contains a memory made of FPGA slices for simplicity.The final productiongrade system will contain the memory as a block-RAM.We also plan in the final design to slightly change the structure, so it can be implemented as a single-clock synchronous system.
The prepared data set from MATLAB has been downloaded to the synthesized design using a custom Python utility which communicates using our proprietary protocol over USB.

The TX Path Circuit Structure
A TX path is a transmitter part of transceiver on Fig. 5  and 6.The input signals are I, Q modulation data and output signal is a RF signal connected either directly to an antenna or to an up-converter.
The path consists of:   In order to achieve optimal performance of the DA converter, DA Clock generator with <1ps total clock jitter is used.Therefore, the TX path SNR degradation due to total clock jitter is negligible.
The I, Q signals pass through the 1st order lowpass filter to the IQ modulator.A TX carrier is generated by TX LO synthesiser, which is composed of a highfrequency voltage controlled oscillator (VCO, around 2720 MHz), integer phase locked loop (PLL) and programmable 8/16 output divider which generates TX carrier.It is possible to generate the TX carrier in the frequency range from 165 to 175 MHz, resp.from 330 to 350 MHz.
The IQ modulator drives a variable attenuator followed by the output amplifier.
All TX path blocks are controlled by the microcontroller, which provides following functions: (1) controls the TX path blocks, (2) communicates with FPGA, (3) provides TX path calibration, (4) allows connection to a PC for debugging purposes.

Results
The finished design was synthesized for the Xilinx Virtex 6 FPGA and tested on the real hardware.The final design contains approximately 3000 slice registers, 10000 slice LUTs -approximately 6000 is used as a memory for the memory-intensive case.For the quarter-sine version, the memory consumption is reduced by three fourths.The total number of LUTs used for either case is roughly comparable so the only real difference is the memory requirement.These numbers are skewed because of the peripheral structures we had to implement as well, in order to be able to communicate with the device and read/write memory contents.We have successfully verified the design using the measuring workbench shown in Fig. 5 and we consider it to be fully functional.
The operating frequency was 100 MHz, but the synthesizer in Xilinx ISE 12.3 timed the circuit to be able to run up to 320 MHz.The measured waveforms and spectra are shown in Fig. 7 and 8.We have verified the circuit functionality using Tektronix DPO 4032 oscilloscope and Rohde&Schwarz FSL6 spectral analyzer.

Conclusion
The key benefit of the described direct quadrature frequency synthesizer with a sine table is the speed (overall structure delay is 2 clocks for both variants) and the frequency stability which is, by the way, a positive feature of all direct synthesizers.However, it requires relatively large amount of memory.The memory should not only be large enough to accommodate a complete quarter period, but also sufficiently quick to be able to serve a double read requests on different addresses in one clock cycle.This is not possible in our Virtex6 FPGA so we opted for doubling the memory.In such way, we can accommodate the need for two reads in a single clock.It, of course, doubles the amount of needed memory.Another limitation arises from a selected minimum phase step, min   , that clearly sets a range of the generated frequencies.So when the required memory size and corresponding frequency accuracy is not appropriate or speed is not crucial the polynomial implementation is more convenient.This structure has overall delay 3 clocks in the case of quadrature approximation a 4 clocks with cubic approximation.

Fig. 3 :
Fig. 3: Signatures of control and data inputs and outputs of circuits used.

Fig. 6 :
Fig. 6: Back side of the radio front-end.Some TX path parameters are listed in Tab. 1.The digital I, Q modulation signals are transferred from the FPGA to the digital I/O interface in two's complement form.The functions of the I/O interface include: (1) terminating TX data bus to reduce digital noise, (2) distributing TX data clock and sync signals between DA converter and FPGA and (3) providing connection between the microcontroller and FPGA.TX data are then transferred to the Dual channel DA converter, which performs the digital 1x/2x/4x interpolation and conversion to analogue I, Q signals.Both DA converter channels have digital gain control, allowing compensation of gain mismatches of I, Q paths.
VHDL entity and signals are shown:

Reference frequency generator TXC 7C-20.000MBB-T
Technical University in Prague (CTU), in 2008, and M.Sc.degree in econometrics and operations research from the University of Economics in Prague, in 2010.He is now towards his Ph.D. in CTU.His research interests include wireless sensor networking and power management in radio systems.He is also active electronic circuit design.