Thermal budget reduction for spike anneals in conventional RTP

Abstract

Thermal budget reduction in rapid thermal processing (RTP) has been a requirement since the beginning. The temperature regime moved from several seconds, so called soak annealing, over spike annealing down to millisecond-annealing (Li in 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors-RTP 2005). The reason for thermal budget reduction is not only in limiting diffusion while on the other hand achieving high activation. In this paper we will focus on the spike anneal thermal budget reduction by means of decreasing the time at 50 K below peak temperature. This time t_T-50K is referred to as peak-width at T-50 K [Li in 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors-RTP 2005, Zhao in ECS Trans 34(1):769–774 (2011)]. There are several possibilities to reduce peak-width of spike anneals. Wafer cooling through conduction and convection can be increased via addition of 1.5 slm Helium to N₂ reducing the peak-width from > 2 s to 1.4 s for a 1090 °C spike anneal [Li in 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors-RTP 2005, Zhao in ECS Trans 34(1):769–774 (2011)]. The method for reducing peak-width in this paper is the use of a high absorptive lamp field which leads to increased absorption of emitted wafer and lamp radiation.

Graphical abstract

Thermal budget reduction in rapid thermal processing (RTP) has been a requirement since the beginning. In this paper we will focus on the spike anneal thermal budget reduction by means of decreasing the time at 50 K below peak temperature. This time t_T-50 K is referred to as peak-width at T-50 K [Li in 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors-RTP 2005, Zhao in ECS Trans 34(1):769–774 (2011)]. Wafer cooling through conduction and convection can be increased via addition of 1.5 slm Helium to N₂ reducing the peak-width from > 2 s to 1.4 s for a 1090 °C spike anneal [Li in 13th IEEE International Conference on Advanced Thermal Processing of Semiconductors-RTP 2005, Zhao in ECS Trans 34(1):769–774 (2011)]. In this work we investigated the activation and diffusion behavior of a 3 keV, 2E15 cm⁻² Boron implant which was annealed on both, a standard Helios®V RTP system and a Helios®V spike system with enhanced spike anneal sharpness. Peak temperatures investigated were 1050 °C and 1150 °C. Those two processes were compared with respect to activation and diffusion. In contrast to the standard Helios®V configuration, the tool with enhanced spike performance uses special temperature controller settings and a ‘high absorptive lamp field’. Sharper spike anneal temperature profiles originate from: (i) improved controller settings mainly influencing the ‘ramp-up slope’ and (ii) enhanced radiative wafer cooling after peak temperature due to increased absorption of the thermal radiation emitted from wafer and lamps. Since thermal radiation follows the Stefan-Boltzmann-Law and is proportional to ~ T⁴, the benefit from the ‘high absorptive lamp field’ is most pronounced at elevated temperatures. In (a) temperature profiles for 1050 & 1150 °C spike anneals are compared. For 1150 °C peak temperature, peak-width @ T-50 K can be reduced by 32%, from ~ 1.3 to ~ 0.9 s, while at 1050 °C peak temperature, peak-width is reduced by 25%, from 1.5 to 1.1 s (b). Due to smaller peak-width, sheet resistance is increased by 38% (b), whereas junction depth determined at a concentration of 1E19 cm⁻³ decreases by 10% at a peak temperature of 1050 °C (c). Despite the lower sensitivity of the implant at the higher process temperature of 1150 °C (b), sheet resistance is higher by 15% (b) and junction depth is smaller by 15% (c). Combining improved temperature controller parameters and a high absorptivity lamp field, the new Helios®V Spike system enhances spike anneal sharpness yielding 30% peak-width reduction and 15% junction depth reduction for the investigated B implant condition (3 keV, 2E15 cm⁻²).