FUNCTIONAL SWITCHING MATRIX FOR AUTOMATIC ANALOG CIRCUIT SYNTHESIS

Synthesis of analogue circuits, most commonly achieved by heuristic methods. In this paper we show that the circuit topology used in the development of what semi-automatic and automatic options available. In this article we'll show also how the many alternatives we can reduce the number of attempts, to make the process more efficient. Method described in this article illustrates the applicability of the solution using a simple example. This approach may be important later in the digitally configurable programmable analog circuits (FPAA) analog synthesis system perspective. The switch matrix as described by using the chances of these circuits may be extended.


INTRODUCTION
An analog electronic circuit function ( c  ) and behaviour (f) is determined by the parameters of the used components ( P ) and the connect topology (n), formal according to equation (1); ) , ( P n The circuit function is of course not an exact definition, but it can mean for example from input to output time domain determined amplitude function, frequencydomain amplitude characteristic and so on.The used circuit description depends on the suspected or the realized function of circuit [1][14] [17].In equation (1) the P parameter is a scalar vector, that contains the relevant parameters of used electronic parts in formal equation (2); where: p n the significant parameter of electronic part, for example resistance of a resistor, capacitance of the a capacitor, h 21 of a bipolar junction transistor…etc.
[15][16].On Fig. 1 is seen, as above example an integrator circuit.This circuit contains an operational amplifier (A 1 ), a square wave input generator; (V 1 , or X1) U pp =2V, U offset = -1V, two power source; (V 2 , V 3 or X2) with ±15V, a feedback capacitor (C 1 ) its value is 22F, and a resistor (R 1 ) it's value is 330.These parts lists and entering a value is defining of the P vector [18].
Table 1 The Integrator circuit connection network Tab. 1 shows a connection network in short form a netlist circuit's of Fig. 1.This net list describes the nods of circuits (N$1, N$3, N$5).The nods N$3 connect two parts, a capacitor (C 1 ), and the output of amplifier (A 1 ) with four pads of integrated circuit, and output of circuit to X 2 connector [2].(X 1 and X 2 input and output points which used in the simulation in timedomain.)Computing environment is possible to check by circuit simulation software the operation of the realized circuit.Fig. 2 shows in time domain the circuit operation from input to output [6].
So the traditional analog circuit developing methods we summarize in flowchart of Fig. 3.As shown the CAD development tools are used, but is fundamental to the existing electronic engineering knowledge, experience, the heuristic is dominant.From the result of created circuit's simulation we must often feedback to every level of developing and to the art of simulation as well and comparison with author's results should be given [7][8] [16] [17] [18].

ANALOG CIRCUIT REALIZATION BY A SWITCHING MATRIX
Theoretically, if we have n numerous electronic components each of them has got  i pins which are necessary to properly connect with a wished analog circuit.If every possible way we want to create a circuit network, we need a matrix that consists of o number of columns according the (3); where for A m(i,j) is true according (4); On Fig. 4 theoretical arrangement of a switching matrix is shown.This matrix consists of electronic part's dev 0 -dev n leg wires as columns c 00 -c n(-1) , and row wires for possible interconnections r 0 -r m-1 .
In (4) 0 means no connection between column and row wires, and 1 case is have got, this is actually a switch function, which is described of turned ON and OFF state.On Fig. 4 we signed this function by a switch k g [7] [8].It can be seen that the pins of electronic components and the interconnection wires formed from a matrix of mxn type, where m=n, so there is square matrix, which contains all the possible options of connections, according in equation ( 5):

Calculating values of parts
This square matrix from equation (3) contains numerous cross points according to (6)  Thus, the number of theoretically possible different topology (T n ) from equations ( 5) and ( 6) is; Fig. 4 layout and description of equations ( 5) and ( 6) are so perfectionist that includes abilities of all the parts legs wires the possibility of connecting a node, as well as the possibility of all parts foot stand-alone, a unique node [9][10].

OPTIMIZATION OF A SWITCHING MATRIX
In the previous paragraph the possibility formation of the theoretical switching matrix is shown.According to the described solution we generate from the circuit of Fig. 1 or net list of Tab. 1 in matrixes in Fig. 5.
On Fig. 5 it can followed that every nods of net list means a row of matrix; r 0 =GND, r 1 =N$1, r 2 =N$2, r 0 =N$3, r 0 =N$4, r 0 =N$5.You can see that the rest of any unused nods abilities from r 6 -r 16 .
The electro technical or physical reason of the not used abilities is understandable, because it is meaningless to connect, for example, two power supplies (N 2 , N 4 ), or output of operational amplifier (N 3 ) with input signal source (N 5 ).Of course one can find too much refusal of this kind.So our proposal is such structural switch matrixes which can not afford such unusual theoretical, often catastrophic result inflict solution.
On the other hand, it is necessary to minimize number of cross points, because the number of ability network according to the equation ( 7) easy to be huge combination.
These values at the proposed structural switch matrix are in order to form; C p =17•10, C p =170, and T n =2 170 , T n =1,49•10 51 .The different according T n parameter in ~10 35 .
Other mitigation options appropriate management of common GND node, and self-evident is providing of active device's power supply [11][12] A special heuristic approach is the elimination of not used rows of matrix, on Fig 6 from r 8 -r 16 .So the number of T c is "only" 1,2•10 24 .

AUTOMATIC SYNTHESIS BY SIMULATION FEEDBACK
In the paragraph 3 we showed how we are able to reduce the number of abilities analog circuit topology.We have shown that by choosing of appropriate structural switching matrix the number radical reduced.It is very important because we propose such a method that is automatically should generate different schemes of analog circuit.
In a "Generating of topology" block a C language program is generated by a combinatory method.We give in "Setting of relevant parameter" block one-one suitable parameter for the used electronic parts.
Then by means of a simulation program we check the behaviour of the created circuit for example in time domain we check.If the characteristic of simulated circuit does not fit, we generate a new one.
If the behaviour of circuit is suitable we need only to set the optimally values of parameters.

CONCLUSIONS
It is alleged that a well-designed matrix prevents the development of adverse topologies, and significantly reduces the number of possible conceptual networks.
The above process is relevant at application of Field Programmable Analog Array (FPAA) circuits and special programmable analog peripheries of PSoC technologies.This article provides a solution the applicability of high performance computers and advanced cross-bar switch circuits appearance.
The proposed methods are extendable for the system generated from functional blocks, and subsystems.

Fig. 2
Fig. 2 Time domain simulation of integrator circuit.Bottom input signal, above the output

Fig. 3
Fig.3Flowchart of an analog circuit developing with using of CAD abilities