Performance Analysis of Double Gate Junctionless Tunnel Field Effect Transistor: RF Stability Perspective

— This paper investigates the RF Stability performance of the Double Gate Junctionless Tunnel Field Effect Transistor (DGJL-TFET). The impact of the geometrical parameter, material and bias conditions on the key figure of merit (FoM) like Transconductance (g m ), Gate capacitance (C gg ) and RF parameters like Stern Stability Factor (K), Critical Frequency (f k ) are investigated. The analytical model provides the relation between f k and small signal parameters which provide guidelines for optimizing the device parameter. The results show improvement in ON current, g m , f t and f k for the optimized device structure. The optimized device parameters provide guidelines to operate DGJL-TFET for RF applications.


I. INTRODUCTION
For the past four decades, the semiconductor industry is supplemented with CMOS devices due to the continuous growth of Semiconductor Technology. During this regime, the silicon device physical dimensions were reduced to nanometre domain and further scaling (Tens of Nanometre) is limited by Short Channel Effects (SCE) posed by CMOS devices [1][2][3][4][5][6]. To overcome such challenges, Multi-gate devices are proposed, which shown excellent immunity to SCE and yielded better scalable operations [7][8][9]. Beyond 30nm, these Multi-gate devices also suffer SCE's and to overcome them, Tunnel Field Effect Transistor (TFET) is proposed which has gained wider significance because of its low subthreshold slope and small leakage current [1][2][10][11][12][13][14]. Moreover, the tunnel FET device suffers from low ON current and requires abrupt junctions for tunnelling [15]. To overcome the fabrication challenges posed by the MOS and TFET devices, a new transistor called Junctionless transistor (JL) with no doping gradients is proposed to achieve good ON and OFF states [16][17]. Even though the JL device has better scalable performance than the MOSFETs, still it suffers from the low subthreshold slope. To counter the above challenges, Junctionless Tunnel Field Effect Transistor (JL-TFET) is proposed, which exhibits better subthreshold slope of 24mV/decade and DIBL of 38mV/V as compared to conventional JLFET [18][19]. Further, most of the research is carried on investigating the analog performance metrics like Transconductance (gm), unity gain cut off frequency (fT), output conductance (gd) and Intrinsic gain (gm/gd) for the n-type and P-type Double Gate junction and Junctionless TFET [20][21]. Impact of geometrical variability's on the performance of JLTFET and Junctionless hetero structure TFETs (HJLTEFT) is investigated and proposed pocket oxide narrower source side HJTFETs (PNS-HJTFETs) for better performance [22]. The effect of the gate dual material (DMG) and gate engineering approach on the performance of DGJL-TFET is studied [23][24][25]. Comprehensive analysis on the 20nm HJLTFETs with high-k gate oxide material is presented [26]. The authors have investigated the influence of spacer on ION/IOFF ratio and gm of a DG JLTFET [27]. Impact of dual k spacer on the digital and analogue performances of JL TFET, formed with different substrates is analyzed [28][29]. Influence of parameter fluctuations caused by process variations on the RF stability of Double Gate Tunnel FET (DG-TFET) is reported by k.sivasankaran.et.al [30]. Influence of high-k material on the RF stability performance of Double Gate Junctionless FET is studied [31] and proposed an optimized structure for the better RF performance [32]. The impact of the high-k gate dielectric and dual spacer on the RF stability Performance of JLTFETs is not been studied before. Most of the studies [18][19][20][21][22][23][24][25][26][27] focused on analyzing the behaviour of JL-TFETs with and without high-k materials for improving the DC and analogue performance but not on the stability aspects of the device. In this work, we have evaluated the RF Stability performance of the DGJL-TFET for different gate oxide materials and different isolation spacers. Further, the effect of geometrical variations towards the critical frequency is also analyzed for proposing the optimized device.
The remainder of the paper is organized as follows: Section 2 describes the DGJL-TFET considered for simulation. Section 3 gives the device Calibration and DC characteristics. RF Stability performance of the DGJL-TFET for different gate oxide materials is presented in Section 4. The results are discussed in Section 5. The optimized device structure is proposed in Section 6. Finally, the conclusion of the work is presented in Section 7. Fig. 1 shows the schematic of the DGJL-TFET. The device is heavily n-type doped 20nm long Si-channel with Source/Drain extension of 20nm [18]. The gate oxide thickness (t ox ) is 2nm and device doping profile is maintained at 1x10 19 cm -3 for silicon body thickness of 5nm. The device is operated with two gates with different work functions: one gate called control-gate (CG) which is used to control the charge flow in the channel (ON and OFF of the device) by sweeping a control-gate voltage (V CG ) from 0V to V DD and another one is P-gate (PG), used to convert the N + source of DGJL-TFET to P-type by using gate work function engineering for tunnelling operation. The spacer width, which isolates the CG and PG of the device, is 5nm. All the simulations are performed using a 5.15.32.R version of Silvaco Atlas [33]. A non-local band to band (BTBT) tunnelling model is used to estimate the TFET device performance [18] by considering the tunnelling along the lateral direction between source and drain. Due to heavy doping of the channel, the band gap narrowing (BGN) model is considered and because of the high impurity atom present in the channel, the Shockley-Read-Hall (SRH) recombination model is enabled. Both quantum confinement effect, as well as interface trap effects in TFETs on the non-local band to band tunnelling, are considered by including quantum confinement (QC) model developed by Hansch [33] [34] and Schenk [33] [35] trap-assisted tunnelling (TAT) model. The work function of Control Gate is taken as 4.3eV for switching the layer under it as intrinsic and platinum metal [36] with a work function of 5.93eV is considered for P-Gate to make the layer under it as P-type region. Fig. 2(a) shows the OFF-state charge carrier concentration profile of DGJL-TFET (Drain Source Voltage, V DS =1V and Control Gate Source Voltage, V CGS =0). From Fig. 2(a) it is evident that the device is behaving like N + -I-P + device. Energy band profile of DGJL-TFET in OFF state is presented in Fig. 2(b). The energy gap between the valence band and conduction band is large, due to which tunneling probability of charge carriers through the tunneling region is negligible.

A. DC Characteristics
Hence, the current flowing in the off sate is small and is only due to the leakage current flowing in N + -I-P + diode.   Fig. 3(a), it is evident that when a voltage of 1V applied between CG and source, the layer beneath the CG is converted to N + , due to which electron concentration in the channel is increased. The rise in electron concentration is due to the increase of tunneling probability of the charge carriers moving from the source to channel. The energy band profile of DGJL-TFET in ON-state is shown in Fig. 3(b), it clearly shows that the narrow bandgap present between the channel and source, due to which tunneling width (λ) is small, subsequently the tunneling probability of the electrons flowing from source to channel is increased and thereby increasing the device ON current.
It is reported that for TFET devices, ON current can greatly improve with the use of high-k materials as gate dielectric [24]. So high k materials like TiO 2 (Ɛ r =80), HfO 2 (Ɛ r =25) and Al 2 O 3 (Ɛ r =9) as gate dielectrics [18] are considered for studying their impact on stability of the device with a fixed physical thickness of 2nm.

B. Transfer Characteristics
The transfer characteristics of DGJL-TFET (depicted in Fig. 1) for various gate dielectric materials are shown in Fig. 4. It is observed that the gate oxide with high-k material gives higher ON current and improved subthreshold swing. The improvement in ON current with high-k gate dielectrics mainly due to the reduction of tunneling width (λ), in return, increases the nonlocal tunneling probability according to the WKB approximation, given by equation 1 and also due to the increase of gate coupling with the channel. From Fig. 4, it is observed that the ON current of 34.5µA/µm for a TiO 2 gate dielectric and 0.295µA/µm for Al 2 O 3 gate dielectric, with both V CGS and V DS are at 1V. (1)

IV. RF STABILITY PERFORMANCE OF DGJL-TFET
An important phase in the overall analysis of transistor is to identify its potential stability. This may be achieved by calculating the Stern stability factor (K), which specifies the device is unconditionally stable or conditionally stable [37][38][39]. If K value is greater than one, then the transistor is unconditionally stable, otherwise, it is conditionally stable and which leads to oscillations at some frequency. Equation 2 given by P.Stern in terms of Y parameters is used to calculate the K value of a transistor.
Where Y 11 and Y 22 are admittances, Y 12 and Y 21 are known as transfer admittance of a two port network.
gd gs gd gd gs gs Substituting equations 3 to 6 in equation 2 will further simplify the K, which is given by equation 7.
Critical frequency (f k ) is one of the key RF performance parameter, specifies at what frequency device attains unconditionally stability. By substituting the K=1 in Equation 7 along with some approximations is simplified to equation 8 which is used to calculate the f k of the device in terms of various parameters [40].
where, f T is the Unity-gain cut-off frequency, which is one of important metric of analog characteristics of the device, specifies the frequency at which the current gain reaches to unity and is expressed as Cgs= Cgsi + Cfext + Cfin (12) Cgd= Cgdi + Cfext + Cfint (13) www.ijacsa.thesai.org The other parameters mentioned in equation 8 are outputconductance (g ds ), gate-source resistance (R gs ), gate-drain resistance (R gd ), gate-capacitance (C gg ), gate-source capacitance (C gs ) and gate-drain capacitance (C gd ) without taking into account of overlap capacitance [39]. The internal fringing field (C fint ) as well as external fringing field (C fext ) is expressed as: 15) Ɛ ox and Ɛ si are dielectric constants of gate oxide and silicon materials. Where W, t si , t ox and t g are width, silicon thickness, oxide thickness and gate material thickness, respectively. Φ f and V FB are Fermi potential and flat band voltage, respectively.
The stability factor is evaluated using equation 7 for DGJL-TFET with various gate oxide materials, whose dielectric values range from 9 to 80 is shown in Fig. 5. From the results, we can observe that the DGJL-TFET with a low-k gate oxide material (k=9) is attaining unconditional stable at a lower frequency at 6 GHz than the high-k gate dielectric (k=80) at a frequency of 130 GHz. Lower f k value is exhibited by low-k gate dielectrics is mainly due to low ON current, low gate capacitance and smaller gain associated with it.  Fig. 6(a) shows the gate dielectric material influence on the cut off frequency (f T ) and transconductance (g m ). Fig. 6(a) inset, it is observed that g m is increasing with increase of dielectric constant of gate oxide material. As with the increase of gate dielectric constant, the tunneling width reduces due to which the tunneling probability increases, thereby enhancing the I ON and thereby g m . Because of the increase of relative permittivity of the gate oxide material with the rise of the gate dielectric constant, the C gg also increases. Due to higher impact of g m over the C gg , f T which is calculated from simulation values g m and C gg using equation 9 is increasing with increase in gate dielectric value.

A. Impact of Gate Dielectric Material (k) on Critical Frequency (f k )
As discussed earlier, from Fig. 6(a), due to improved performance of f T , C gg and g m with a high-k gate dielectric, DGJL-TFET with high-k gate material (HfO 2 , TiO 2 ) yielded higher f k as compared to low-k gate material (SiO 2 ). From Fig. 6(b) f k which is calculated using equation 8 is 1.5GHz for low-k gate oxide material (SiO 2 ) and for 130GHz for high-k gate oxide material (TiO 2 ). Various parameters which has effect on the stability and f k for various oxide materials are presented in Table I.  B. Impact of Isolation Spacer Length (L sp ) on f k In the previous subsection, it is observed that the ON current of the DGJL-TFET is improved with the aid of high-k gate dielectrics. The other way to increase I ON is by scaling the isolation spacer length (L sp ), with the aid of charge plasma concept [24]. With scaling of spacer length (L sp ), the gate controllability over the source-channel region is increased, which reduces the tunneling barrier height, due to which the tunneling probability increases, subsequently increasing the I ON . However, this improved I ON is obtained at the expense of increased C gg , which is shown in Fig. 7(a).  Fig. 7(b) shows the f k variation with the scaling of isolation spacer (L sp ) of DGJL-TFET for different spacer material with 2nm TiO 2 as a gate dielectric. It is evident from Fig. 7(b) that, f k is increasing with the scaling of the L sp . While scaling the L sp from 10nm to 5nm, the impact of it on f k is not as much of for all the spacer materials, but further scaling of L sp below 5nm the impact is large. This impact is largely attributed by interface defects at high-k oxide and Si interface, the induced trapped charges and capacitive fringing field's associated with high-k spacers. For TiO 2 spacer, f k is varied from 3GHz to180GHz when L sp scaled from 10nm to 3nm. However, a large variation of f k nearly twice as that of the high-k spacer (TiO 2 ) is noticed with the low-k spacer (SiO 2 ). i.e., f k is varied from 6 GHz to 350 GHz, when L sp scaled from 10nm to 3nm.

C. Impact of Gate Oxide Thickness (t ox ) on f k
Tunneling process in T-FET devices is greatly affected by the variation gate oxide thickness (t ox ), this effect is noticed due to the variation of gate-capacitive coupling with variation of t ox . As per WKB approximation, oxide thickness affects the tunneling probability by modulating the tunneling width. Equation 16 gives the dependency of tunneling width in terms of gate oxide thickness and other parameters. A thinner gate oxide will have less tunneling width (λ) and vice versa for thicker gate oxides.
The ON current of device with t ox =5nm is smaller when compared to 2nm t ox device, since 5nm oxide thickness devices have low capacitive coupling, due to which it has a lesser influence on the tunneling phenomena. Through simulation, it is also observed that irrespective of gate oxide material, DGJL-TFET exhibits improved I ON with the scaling of the t ox. It is also observed that TiO 2 gate dielectric with t ox =5nm has better I ON (6.6 µA) than low-k gate dielectric (Al 2 O 3 ) with t ox = 2nm (0.35 µA) The simulated values effecting the stability and f k with t ox scaling for TiO 2 gate oxide material are given in Table II. Fig. 8(b) shows f k variation with the scaling of t ox for different gate oxide materials of a DGJL-TFET with 5nm SiO 2 isolation spacer. It is observed that, with the scaling of t ox , DGJL-TFET with lowk gate dielectric has lower f k then that of high-k gate dielectric. The simulation results illustrate that f k for TiO 2 is varied from 68 GHz to 130 GHz and 0.2GHz to 6GHz for the Al 2 O 3 with the scaling of t ox . When t ox scaled from 5nm to 2nm, nearly 50% increase in f k for TiO 2 material is noticed and it is because of the large variations in I ON , g m , and C gg with the scaling of t ox . Fig. 9(a) illustrates a comparative impact of drain side spacer materials on the stability of the DGJL-TFET with 2nm TiO 2 as gate oxide and 5nm SiO 2 as isolation spacer and at an L dsp of 15nm. It is observed that, drain spacer material has smaller impact on stability factor and almost same for all the spacers. As the drain spacer does not have tendency to affect the tunneling width, the current of the device and other stability parameters are virtually the same. www.ijacsa.thesai.org   Fig. 9(b), as L dsp is scaled from 15nm to 5nm, f k is increasing marginally for all the spacer materials and it is mainly because of the reduction spacer fringing fields and the capacitive area, thereby reducing the gate capacitance which is shown in the inset of Fig. 9(a). With the L dsp scaling, C gg is reduced largely for high k spacer and slightly varied for low k spacer. The parameters related to equation 3, like I ON , g m , f t , are almost constant with spacer material and spacer length but the variation in C gg , which is large for high k spacer is only impacting the f k . Therefore f k for TiO 2 spacer varied nearly 20 GHz, when L dsp is scaled from 15 nm to 5nm.   Fig. 10(a) shows the impact of control-gate voltage (V CGS ) on the f k for 5nm isolation spacer DGJL-TFET for different gate oxides at V DS of 1V. As gate bias V CGS varied from 0.4V to 0.8V, f k is increased for all gate oxides. since the device current, g m and C gg asscoiated with high-k gate oxide materials is large. Therfore the f k of TiO 2 material is increased at a much higher rate than that of Al 2 O 3 material. At higher gate bias, i.e., when V CGS is increased beyond0.8V, f k for Al 2 O 3 lies in the same order but for HfO 2 and TiO 2 material it decreases to a larger extent. The decreasing in f k for TiO 2 material is due to the large varition in C gg and smaller variations in I ON and g m with control gate bias beyond 0.8V. The lowest value of f k for TiO 2 material is 25 GHz at gate voltage of 1.2V. Finally, it is noticed that higher the controlgate voltage, lower the f k value.  Fig. 10(b) shows f k variation with respect to drain bias scaling for different gate oxide materials of DGJL-TFET with 5nm as isolation spacer. As drain voltage V DS changing from 0.7V to 0.9V, f k is of the same order and the insignificant difference is noticed for all the gate oxide. But for V DS above 0.9V, the f k of high-k gate dielectric (TiO 2 ) is much higher when compared to low-k gate dielectric (Al 2 O 3 ). This is attributed by the decrease of output conductance (g ds ) and an increase of I ON with the increase of drain voltage for TiO 2 gate oxide material. So, higher drain bias and high-k gate oxide material will yield higher f k and vice versa.

VI. RF PERFORMANCE OF OPTIMIZED DGJL-TFET
The device geometry parameters like gate oxide thickness, spacer material, spacer length, gate dielectric material, and supply voltages are identified from the preceding sections for the optimization of the device for better RF stability performance is shown in Fig. 11. From the preceding section results, TiO 2 material is taken as gate dielectric material for the optimized DGJL-TFET structure with t ox of 2nm. TiO 2 material is chosen as drain spacer and isolation spacer of a length 15nm and 3nm respectively. The structure is simulated with supply voltages at V CGS =1.2V and V DS =0.8V. Fig. 12 shows the stern stability factor (K) for the optimized structure. The device attaining stability at a lower frequency and yielding lower f k of 17.5GHz without degrading the I ON . The low value of f k is due to larger capacitance and larger fringing fields associated with TiO 2 gate oxide material. Since the optimized device exhibiting lower f k , hence at a lower frequency,the device becomes unconditionally stable thereby making it a best suitable device for high frequency applications.

VII. CONCLUSION
In this paper, we have investigated the influence of high-k gate dielectrics / high-k spacer on the RF stability performance of 20nm channel DGJL-TFET. From the simulation results, it is observed that the device with low-k gate dielectric attains stable at lower frequencies, but yielding low ON current. It is also noticed that high-k as an isolation spacer is responsible for the obtaining lower f k . In addition, the effect of geometrical variability's towards f k is studied and results showed decreasing trend with the increase of the spacer length, gate oxide thickness, but an increased trend for drain voltage. Finally, the optimized structure is proposed for yielding the better stability and lower f k , by which we can avoid the additional circuit. The proposed DGJL-TFET exhibits f k of 17.5GHz. In summary the DG-JTFET is promising device, suitable for low power and analog/RF applications.