Carbon Nanowall Field Effect Transistors Using a Self-Aligned Growth Process∗

Nano-carbons such as carbon nanotubes and graphenes are very promising as next-generation materials, and field effect transistors (FETs) can be used with nano-carbon channels. In these nano-carbon materials, carbon nanowalls (CNWs) are constructed with a few layers of graphene and exhibit properties similar to those of graphene. We have developed a self-aligned process for CNWs using grapho-epitaxy. We have grown CNW channels on several line and space patterns fabricated by electron beam lithography and reactive ion etching. When the line and space pattern is suitable, self-aligned CNWs can be made by plasma-enhanced CVD. We also discuss the electrical properties (IDS-VDS characteristics) of the self-aligned CNW-FETs resulting from several growth temperatures and deposition times. [DOI: 10.1380/ejssnt.2014.225]


I. INTRODUCTION
Low-dimensional materials are key materials for nextgeneration high-performance devices.Nano carbon materials are promising candidates since they naturally have two-dimensional carbon sheets such as graphene [1,2], which can be used to construct one-dimensional carbon nanotubes (CNT) [3] in a cylindrical structure of a graphene sheet.Many novel applications have been investigated for CNTs and several nano processes have been developed, such as those utilized in nano-size transistors, field emission devices, biosensors, and interconnections in large-scale circuits.One of the advantages of CNTs is that field effect transistors (FETs) can be fabricated by conventional lithography with the control of a catalyst.Thus, the FET structures and nano-processes of nano carbon materials should be important for applications.The carrier control of p-type and n-type conduction is also possible using a passivation layer [4,5].Furthermore, a single electron or hole transistor as a nano-sized device has been fabricated using nanotechnology [6], which has exhibited room-temperature operation [7].On the other hand, the carbon nanotube field effect transistor (CNT-FET) seems to be one of the promising candidates for use as highly sensitive sensors for gas or biomolecules.A NO 2 and Cl 2 gas sensor was reported using CNT thin films [8].
Recently, an aptamer-based novel biosensor has been developed that can be used for the label-free detection of IgE [9,10].We have also developed noise-enhanced nonlinear devices [11,12] and demonstrated controllability of operations [13,14].
Many superior properties such as high mobility and strength can be caused by the two-dimensional graphene sheets and the application of the 2D structure itself to achieve functional nano-carbon devices.Recently, many researchers concentrated on the development of nano processes for graphene, where exfoliation of graphenes [15] and CVD-grown products are used as graphene materials [16,17].Since a metal catalysis such as copper is used for graphene growth by CVD [18], development has focused mainly on the transfer processes to the insulating substrates as devices.Several CVD techniques have been used by many research groups [19][20][21][22].Direct growth of graphene devices seems to be important for future electronic devices [23] and many kinds of fabrication processes have been investigated [24][25][26][27][28][29].
Carbon nanowalls also have such 2D structures.CNWs can be constructed by a few layers of graphene and are also candidates as high-performance and low-dimensional materials [30].CNWs can also be grown by the CVD technique without catalysts [31], which is suitable for standard semiconductor fabrication processes.Therefore, several applications have been investigated such as templates for nano structures [32] and catalyst supports for fuel cells [33].The control of crystallinity and carriers seems to be important in electronic device applications, and the hydrogen process [34] and nitrogen doping [35] have been proposed for the quality control of CNWs.However, the position control of CNWs in the devices is difficult from the viewpoint of growth control.This is the limitation of CNWs in applications such as transistors.We have developed a self-aligned process for CNWs.In this paper, we discuss the grapho-epitaxy process.We prepared several line and space patterns fabricated by electron beam lithography and reactive ion etching (RIE).CNWs were grown by plasma-enhanced CVD on these patterns, and observations were made using the scanning electron microscope (SEM) to check the self-alignment.Furthermore, we have grown CNW channels on suitable line and space patterns using the self-aligned process, and fabricated a back-gate type FET structure.We then discuss the electrical properties (I DS -V DS characteristics) of the self-aligned CNW-FETs resulting from several growth temperatures and deposition times.

II. EXPERIMENTS
Si wafers were used as a substrate, and line and space patterns were made by electron beam lithography using ZEP-520A, and RIE using CF 4 .The fabricated patterns are summarized in Table I.The RIE etching time is 12 min with a plasma power of 100 W for patterns with a depth of 300 nm, and a deep etching of 600 nm was accomplished using the additional process gas of Ar.CNWs were grown by plasma-enhanced CVD using CH 4 with a carrier gas of H 2 .The growth temperatures were 500 and 600 • C for 30 min.
Si wafers with a 50-nm SiO 2 layer were used for CNW-FETs.We used convex patterns of 400 nm with a concave space of 600 nm for the FET.The RIE etching time was 12 min with a plasma power of 100 W. The etched depth was 300 nm.For plasma-enhanced CVD growth, CH 4 gas was used as the process gas with a carrier gas of H 2 .The growth temperatures were 400, 500 and 600 • C for 30 min.For experiments investigating dependence on deposition time, the samples were grown for 15 min and 30 min at 600 • C.After electrode fabrication, CNWs grown outside the channel region were etched out by O 2 plasma for 3 min with a plasma power of 100 W using photo lithography.
The current-voltage (I DS -V DS ) characteristics of CNW-FETs were measured using the semiconductor device analyzer B1500 (Agilent Technologies) in the range −1 V to 1 V for V DS .The gate voltage (V g ) was scanned from −5 V to 5 V in steps of 1 V.The V g dependence of I DS with constant V DS was also measured using the same experimental systems.

III. RESULTS AND DISCUSSION
We used substrates with several line and space patterns as summarized in Table I.Representative SEM images are shown in Fig. 1.Sample A has a narrow line and space as shown in Fig. 1(a).Sample C has widely drawn patterns and then the convex patterns are aligned with the wide distance as shown in Fig. 1(c).Sample B has a moderate line and space pattern as shown in Fig. 1(b), where 400nm width convex patterns aligned with the space distance of 600 nm.For all processed substrates in these figures, the depth of the processed patterns was 300 nm.
Figure 2 shows CNWs grown at 600 • C on the processed substrates.Figure 2(a) shows that the CNWs grown on Sample A have difficulty forming a parallel alignment.There is no growth between the convex patterns, but many CNWs bridge the processed patterns.Figure 2(b) shows the self-aligned CNWs on the processed patterns.We can also observe the self-aligned CNWs in Fig. 2(c), but there are many unintentionally grown CNWs between the convex patterns.The alignment status is summarized in Table I.We also used processed patterns with a depth of 600 nm and obtained similar results.
On the convex patterns, the corners have a higher sticking probability than the flat regions, as two surfaces merge at the corner.Therefore, the raw carbon materials could be concentrated on the corner.The carbon atoms can also diffuse on the surface and could accumulate on the corner because a considerable amount of carbon exists in this region, which could be the growth points.For the narrow patterns, two corners have almost equal sticking probability and many bridged CNWs can be observed.For suitable line and space pattern substrates, the carbons deposited between the convex patterns can diffuse to the corner and the growth of CNWs should be concentrated on the processed patterns.The self-aligned CNWs can then be grown in this region.For convex patterns wider than the diffusion length, the carbons deposited between the patterns cannot diffuse to the edge and then unintentional growth between the patterns occurs.The diffusion length is obviously changed by the growth temperature.When the sample was grown at 500 • C using the same patterns for sample A, the self-aligned CNWs can be grown on these narrow patterns.We will now discuss the electrical properties of the selfaligned CNWs.Using the self-aligned process, we can fabricate an FET structure, where the self-aligned CNWs can be used as channels in FET and the SiO 2 layers of Si substrates can act as a back-gate dielectric.When used a 500-nm SiO 2 layer and the etched depth was set to 300 nm.A representative CNW channel can be seen in Fig. 3 (a).The growth temperature for this CNW channel was 500 • C and its resulting height was low; however, the alignments seem to be perfect.Therefore, we can measure the electrical properties only for the self-aligned CNWs.-1 -0.5 0 0.5 1 plasma was not good for electrode deposition as shown in Fig. 3(b).We then skipped this O 2 plasma cleaning treatment for the device fabrication and found that the hydrogen treatments could also enhance the contact fabrication.In this paper, we mainly used samples without O 2 plasma treatments for the measurement of electrical properties because of the better electrode fabrication.We also checked the leak current outside the CNW channels.
If the CNW channels do not bridge the electrodes in the FET, I DS is zero as shown in Fig. 4. Therefore, in our device structure we can correctly measure I DS -V DS characteristics with V g dependence only for the self-aligned CNW channels.Figure 5(a) shows representative I DS -V DS characteris-tics for the sample grown at 500 • C. We show the nonlinear I DS -V DS characteristics with V g = 0 V. Our findings show enhancement of I DS at the positive V DS with the negative gate voltage.This feature means p-type conduction for the self-aligned CNW channels.The asymmetry of I DS might be caused by the interface defects at the electrodes.On the other hand, we observe enhancement of I DS at the negative V DS with the positive gate voltage.This means n-type conduction for the self-aligned CNW channels.We can therefore observe the bipolar I DS -V DS characteristics of the self-aligned CNW channels.Our results also demonstrated that the semiconductive I DS -V DS characteristics of samples grown at 400 • C are the same as those grown at 500 • C. In contrast, samples grown at the higher temperature of 600 • C reveal that all the self-aligned CNW channels have the metallic I DS -V DS characteristics as shown in Fig. 5(b).These samples did not exhibit the gate voltage dependence of I DS -V DS characteristics.However, for samples grown at 600 • C at 15 min, semiconductive channels (ntype) can also be observed as shown in Fig. 5(c).This means that the CNW channels in the initial growth stage have semiconductive electrical properties, and this characteristic changes following prolonged deposition.
We observe the semiconductive I DS -V DS characteristics for samples grown at low temperature (400 • C and 500 • C) and/or those grown with a short deposition time.The semiconductive characteristics in CNW-FETs could be caused by Schottky contacts similar to that reported for CNT-FETs [36,37].We know that defects and/or adsorbates have large effects on the electrical properties in CNTs [12,[38][39][40].Therefore, the semiconductive characteristics for CNW-FETs might be caused by the defects induced in the CNW channels.We also observe a reduction of the G/D ratio in Raman spectra mapping for the semiconductive CNW channels.The decrease in the G/D ratio could indicate an increase in the density of defects or shrinkage of the domain size of nanometer-size grains of crystalline graphite.In the latter scenario, when the size of the grain is smaller, the band gap can be modified due to the size effect of quantum confinement.However, the semiconductive electric properties are stochastically observed for about 30% of devices, and this ratio was enhanced by the self-alignment process.We can then conclude that a change of the grain boundary in the self-aligned CNWs could induce the defects in the CNW channels.Therefore, the defects induced by the strain seem to be the main cause of the semiconductive channels in CNW-FETs.A higher temperature and longer deposition time can cure the defects induced in the selfaligned CNW channels.Such CNW-FETs show metallic properties.

IV. CONCLUSION
We have developed a self-aligned process for CNWs using grapho-epitaxy.We have grown self-aligned CNWs on several line and space patterns fabricated by electron beam lithography and RIE.When the line and space pattern is suitable, the self-aligned CNWs can be made by plasma-enhanced CVD.CNWs bridge the patterns for narrow diffusion lengths, and random growth can be obhttp://www.sssj.org/ejssnt(J-Stage: http://www.jstage.jst.go.jp/browse/ejssnt/) e-Journal of Surface Science and Nanotechnology Volume 12 (2014) served between the patterns for wide lengths.We also discussed the electrical properties (I DS -V DS characteristics) of self-aligned CNW-FETs resulting from several growth temperatures and deposition times.For low-temperature growth at 400 • C and 500 • C, tens of semiconductive channels can be observed.In contrast, the sample grown at the high temperature of 600 • C exhibited metallic channels.However, semiconductive channels can also be observed for samples grown at 600 • C for 15 min.We also observed reduction of the G/D ratio in Raman spectra mapping of the semiconductive channels.Therefore, the defects induced by the strain seem to be the main cause of the semiconductive channels in CNW-FETs.

FIG. 2 :
FIG. 2: CNWs on the processed substrates.(a), (b) and (c) are for samples A, B, and C, respectively.Inset picture was taken with a tilted angle of 80 • .

Figure 3 ( 2 Volume 12
b) shows an example of an electrode (Ti/Au) for CNW channels.Surface cleaning treatment by O

FIG. 5 :
FIG. 5: IDS-VDS characteristics for CNW-FET.(a) is for a sample grown at 500 • C and (b) is for a sample grown at 600 • C, with a deposition time of 30 min.The sample in (c) was deposited for 15 min at 600 • C.

TABLE I :
Line and space patterns of Si substrates.