Bufferless 1.5 μm III-V lasers grown on Si-photonics 220 nm silicon-on-insulator platforms

Bufferless 1.5 μm III-V lasers grown on Si-photonics 220 nm silicon-on-insulator platforms Yu Han,1 Zhao Yan,1 Wai Kit Ng,2 Ying Xue,1 Kam Sing Wong,2 AND Kei May Lau*,1 Department of Electronic andComputer Engineering, Hong KongUniversity of Science and Technology, ClearWater Bay, Kowloon, Hong Kong, China Department of Physics andWilliamMong Institute of Nano Science and Technology, Hong KongUniversity of Science and Technology, ClearWater Bay, Kowloon, Hong Kong, China *Corresponding author: eekmlau@ust.hk


INTRODUCTION
Aiming at integrated circuits with higher functionality and lower cost, introducing foreign materials such as III-V, nitride, germanium, and polymers onto the industry-standard Si platform has received extensive investigation [1,2]. In particular, an efficient III-V-based light source on Si represents the crux for fully integrated Si photonics [3]. Practical applications demand these light emitters to be continuous-wave electrically pumped, seamlessly coupled with Si waveguides, and stably operated with a long lifetime. Currently, the wafer/die bonding technique can satisfy all these requirements and has yielded commercially available products [4]. In the long run, however, direct growth of III-V light sources on Si offers a monolithic integration scheme with potentially lower cost and higher scalability [5,6]. Two different approaches, namely, blanket epitaxy of III-V thin films on Si and selective area growth of III-V crystals on Si, have been developed for laser integration on the (001) Si platform. Equipped with quantum dots as the active medium and various defect reduction techniques, blanket epitaxial III-V thin films have produced electrically driven lasers with impressive lifetimes [7][8][9]. Nevertheless, the thick buffer required for defect management hampers the interconnection with Si waveguides, and practical solutions have yet to be demonstrated.
Besides, the dislocation density of the epitaxial thin films needs further reduction, especially for the InP-based material system wherein the 1.5 µm lasers are built [10]. As an alternative, selectively epitaxial III-V materials exhibit a buffer layer down to a few tens of nanometers and are generally dislocation free, resulting from the unique growth mechanisms and the defect necking effects [11][12][13][14][15][16]. Elimination of the thick buffers needed for III-V lasers on Si can significantly cut down the growth time and the production cost. The epitaxial alloys also extend beyond conventional GaAs and InP and reach highly lattice-mismatched materials such as GaSb and InAs [17,18]. Although electrically driven lasers have not been reported using these selectively grown III-V materials, optically pumped devices have been widely researched [19][20][21], with lasing demonstrated at both the 1.3 µm and the 1.5 µm band on the common InP material system grown by the conventional aspect ratio trapping (ART) method [22,23]. In addition, the intimate placement of the laser cavity and the Si substrate facilitates light coupling into the Si waveguides. Recently, an adiabatic tapered coupler has been designed for interfacing selectively epitaxial III-V light sources and Si waveguides processed on the SOI platform [24], highlighting the potential of using these laser sources as inter/intra chip interconnects in future Si-based photonics integrated circuits.
Selective growth of III-V semiconductors on (001)-oriented Si substrates usually starts with creating V-grooved Si trenches with {111}-oriented facets to prohibit the formation of anti-phase boundaries [25]. Depending on the targeted applications, the trench opening ranges from a few tens of nanometers for electronics to hundreds of nanometers for photonics [26][27][28][29]. The trench width determines the depth of the etched V-grooved Si pocket as schematically illustrated in Fig. 1(a), which imposes a lower limit on the thickness of the Si device layer. For the 220 nm SOI commonly used in Si-photonics foundries [see Fig. 1(b)], patterning Si trenches with a width larger than 310 nm results in trapezoidal troughs instead of V-grooved pockets [see Fig. 1(c)]. Efficient waveguiding at the 1500 nm band, however, necessitates a trench width larger than 450 nm. Under these conditions, the minimum aspect ratio of 1.4 required in the conventional ART technique can hardly be satisfied. Selective epitaxy of III-V alloys inside these trapezoidal troughs differs from that inside the V-grooved trenches using the conventional ART method, and specially designed growth strategies are thereby required. Indeed, the ability to grow III-V inside the trapezoidal troughs obviates the stricture on the thickness of the Si device layer and enables the flexible epitaxy of III-V compounds on various SOI platforms. Integration of III-V on thin SOI also brings closer the epitaxial III-V lasers and the processed Si waveguides and thus promotes efficient coupling.
In this work, we present the design and integration of bufferless III-V lasers on the Si-photonics standard 220 nm (001) SOI platforms. By combining the lateral ART and the conventional ART methods, we devised a unique metal organic chemical vapor deposition (MOCVD) growth scheme for the direct epitaxy of high-quality III-V materials inside trapezoidal troughs patterned on the 220 nm SOI. The designed growth technique promotes the formation of planar defects instead of threading dislocations and thus produces epitaxial III-V materials with greatly improved crystalline qualities. Consequently, we detected room-temperature lasing at the 900 nm band from the as-grown pure InP crystals and room-temperature stimulated emission at the 1500 nm band through embedded InGaAs quantum structures inside the InP. Direct growth of these bufferless 1.5 µm III-V lasers on Siphotonics 220 nm SOI wafers signals the imminent bridging with Si-based photonic devices and the subsequent realization of fully integrated Si-based photonic circuits.

GROWTH DESIGN AND LASER FABRICATION
The patterned (001)-oriented SOI wafers used in this experiment feature a 500 nm thick top oxide layer, a 230 ± 80 nm thick Si device layer, and a 2.0 ± 0.08 µm thick buried oxide layer.
[110]oriented oxide trenches with a width of 500 nm were patterned atop the substrate, followed by anisotropic wet etching to create trapezoidal troughs as shown in Fig. 1(c). Immediately after, the samples were loaded into a MOCVD system (AIXTRON 200/4) for III-V hetero-epitaxy on Si. Figure 1(d) schematically summarizes the designed growth scheme. Two symmetrical InP nanocrystals were first deposited onto the exposed {111} Si surfaces using the lateral ART method [30]. A three-step growth procedure was adopted, starting with a low-temperature GaAs wetting layer at 400 • C, a low-temperature InP nucleation layer at 430 • C, and a high-temperature InP main layer at 630 • C. The two symmetrical InP islands extended laterally, coalesced into a single InP crystal, and gradually filled up the trapezoidal trough. The growth temperature was kept at 630 • C at this stage. Finally, the InP crystal evolved vertically into a nanoridge structure with two convex {111} facets [31,32]. At this stage, the growth temperature was reduced to 600 • C for a uniform ridge morphology. The choice of InP grown on 220 nm SOI is to illustrate the efficacy of the growth scheme, which is also applicable for the epitaxy of other III-V compounds (e.g., GaAs, InAs, GaSb, etc.) on SOIs with different Si device layer thicknesses. Figure 2(a) displays a 70 • tilted-view scanning electron microscope (SEM) photo of the as-grown InP, showing in-plane and uniform nanoridge structures grown on the 220 nm SOI platform. Figure 2(b) presents a cross-sectional transmission electron microscopy (TEM) image of one InP nanoridge inside the etched trapezoidal trough. As designed, epitaxy initiates laterally from the two {111}-oriented Si surfaces. Lattice mismatch between III-V/Si is resolved through forming a highly twined region at the interface instead of threading dislocations [see the zoomedin TEM photo in Fig. 2(d)]. The two side InP islands evolve in opposite directions and start to merge together from the bottom tip as illustrated by the TEM image in Fig. 2(c). We detect a slight misalignment in the crystal orientations between the two InP islands, which leads to the formation of two symmetrical planar disordered regions during the coalescence process as shown by the close-up TEM photo in Fig. 2(e). These planar defects lie parallel to the trough direction, propagate upwards, and eventually terminate at the oxide sidewalls [see Fig. 2(b)]. As a result, the InP main layer after the coalescence, where the active region resides, exhibits an excellent crystalline quality. We also examined the as-grown InP nanoridge from the direction parallel to the trough [see the TEM image in Fig. 2(f )]. The TEM specimen was prepared using focus ion beam (FIB) milling and probed inside a JEOL2001F microscope. The lamella locates at the center of the InP nanoridge as the imaged InP lies right above the buried oxide layer. We detected the presence of threading dislocations at the bottom part of the nanoridge and significantly reduced density at the upper part due to the defect necking effect. Compared with InP nanoridges grown using the conventional ART method, our scheme here manifests a much lower defect density [33]. Although most of the area in the upper nanoridge where the active region resides is free of threading dislocations, we did observe one at the upper part across the 5.4 µm long TEM specimen [see the top blue arrow in Fig. 2(f )]. This is an unusual event considering that the aspect ratio is already higher than 1.4 at that position. Similar dislocation has also been observed in GaAs nanoridges grown inside V-grooved Si trenches [34]. Interestingly, the distribution of the threading dislocations is highly localized at the central part of the specimen. This feature suggests a different nucleation or coalescence condition at that position, and, in turn, indicates the possibility to eliminate these dislocations through fine-tuning the growth parameters. As shown by the yellow marker in Fig. 2(f ), we also detect a stacking fault, perpendicular to the trough direction, propagating upwards to the InP top surface [see Fig. 2(g)]. We investigate the density of this type of planar defects by selective wet etching (H 2 SO 4 : H 2 O 2 : H 2 O = 1 : 1 : 10), and we observe two different types of stacking faults in the (111) and the (111) directions as shown by the top-view SEM image in Fig. 2(h). The density is estimated to be around 0.18/per micrometer, almost an order of magnitude lower than those grown on Si using the conventional ART method [35]. Note that, unlike the case in blanket epitaxial thin films where one stacking fault is accompanied by two dislocations at the ends, stacking faults here extend across the entire nanoridge and terminate at the oxide sidewalls, and they therefore by no means introduce any unwanted nonradiative recombination centers in active photonic devices.
To evaluate the potential of the selectively epitaxial InP for on-chip light sources, we designed and fabricated both pure InP and InP/InGaAs lasers directly grown on the 220 nm SOI. The asgrown III-V nanoridges on SOI are inherently low-loss waveguides [36]. We can produce Fabry-Perot laser cavities through defining two end facets. Figure 3 the removal of oxide and undercut of Si to enhance optical mode confinement and the creation of end facets by FIB to provide optical feedback. We intentionally left two small Si pedestals to provide mechanical support for the laser cavity atop the buried oxide layer. The finalized laser array is manifested in the tilted-view SEM photo in Fig. 3 Fig. 3(c). The length of the laser cavity is controlled by the FIB process and varies from a few micrometers to tens of micrometers. Figure 3(d) presents a zoomed-in SEM image of the end facets, revealing the InP laser cavity, the two supporting Si pedestals, and the buried oxide layer.

RESULTS AND DISCUSSION
We optically probed the fabricated pure InP and InP/InGaAs lasers at room temperature using a micro-photoluminescence (PL) setup. The excitation laser features a wavelength of 800 nm, a pulse width of 100 fs, and a repetition rate of 76 MHz. The InGaAs detector is thermoelectrically cooled to −10 • C for higher sensitivity. Figure 4(a) presents the room-temperature emission spectra of one pure InP laser with a length of 25 µm. Below threshold, we observe a broad spontaneous emission superimposed with a few small resonance peaks. The probed InP laser cavity emits faint and incoherent light in all directions as shown in the lower inset of Fig. 4(a). Above threshold, the resonance peaks intensify and stand out from the background emission with a dominant peak at 953 nm. The emission from the end facets also brightens, dominates the emission over the laser cavity, and becomes coherent with distinctly identified fringe patterns [see the upper inset of Fig. 4(a)]. Figure 4(b) plots the evolution of the peak intensity and linewidth of the main peak as the excitation level strengthens. The clear kink of the light-light (L-L) curve together with the narrowing and subsequent saturation of the linewidth corroborates the room-temperature lasing behavior. The threshold is estimated to be around 220 µJ/cm 2 . Due to the lack of mode selection mechanism in these simple nanolasers, we only observed a multi-mode lasing phenomenon. The dominant mode is most likely to be the TE 01 mode [see the inset of Fig. 4(b)], as this mode exhibits the highest end-facet reflectivity. Despite the highly twined region at both the III-V/Si interface and the coalescence interface of the InP islands, we still observed room-temperature lasing from the pure InP crystals, which further attests to the excellent quality of the InP selectively grown on the 220 nm SOI. The as-grown InP can also serve as a buffer layer for the growth of lattice-matched InGaAs alloys and thereby enable more efficient telecom lasers to directly grow on the 220 nm SOI. We incorporated five In 0.53 Ga 0.47 As ridge quantum wells inside the multi-faceted InP ridge buffer using our developed cycled growth procedure [10]. The InGaAs quantum wells are positioned right above the twined region as shown by the TEM photo in Fig. 2(b). Figure 5(a) presents the room-temperature emission spectra of the as-grown InP/InGaAs nanoridges with the peak locating at 1500 nm. The broad emission spectrum results from the slight variation of the thickness and composition of the InGaAs quantum wells. Figure 5(b) displays the room-temperature emission spectra of one examined InP/InGaAs laser with a length of 38 µm. Under a low excitation level, we detected evenly spaced resonance peaks with the envelope centered at 1500 nm. Under higher excitation levels, the peak at 1511 nm reaches the threshold and dominates the emission spectra. A few side modes are also visible at the lefthand side of the main peak. Figure 5(c) shows the L-L curve of the mode at 1511 nm plotted in a logarithmic scale. The clear S shape indicates a strong lasing behavior. The linewidth plotted in a linear scale also narrows from 3.1 to 0.7 nm as the excitation level increases [see Fig. 5(c)]. As a result of the strong carrier confinement inside the quantum wells, the threshold of the probed InP/InGaAs laser is only around 16 µJ/cm 2 , a value more than an order of magnitude lower than the pure InP lasers. Figure 5(d) compares the confinement factors of the first three supported transverse modes: the HE 11a mode, the HE 11b mode, and the TE 01 mode. The TE 01 mode is most likely to be the dominant lasing mode, as it exhibits the largest electric field confinement factor within the quantum wells and the highest end-facet reflectivity. We also measured lasers with different cavity lengths. Generally speaking, the lasing peak red-shifts as the cavity length increases, while the lasing threshold gradually reduces as the cavity lengthens, as a longer cavity provides a lower material loss. Table 1 compares the differences between the laser integration scheme presented here and our previous lasers grown on SOI using the conventional ART method [37,38]. The different trench arrangements result in integration on different SOI platforms and subsequently different growth designs. With a synergy between the lateral ART and the conventional ART, we are able to reduce the defect densities and thus improve the laser performances. For our previous InP/InGaAs lasers grown on SOI by the conventional ART method, a cavity length larger than 50 µm is required for lasing at the 1500 nm band, and the lasing thresholds are around 40 µJ/cm 2 [38]. In contrast, for InP/InGaAs lasers grown on the 220 nm SOI using the devised method here, a cavity length as short as 28 µm can sustain lasing at the 1500 nm band, and the lasing thresholds are also more than 2 times lower. We attribute these improvements to the enhanced crystalline quality of the epitaxial InP crystals.
Compared with vertical III-V nanowire lasers grown on (111) Si or III-V native substrates [39,40], the major advantage of our devices is they make it easy to directly integrate in-plane and Si-photonics compatible light sources on the (001)-oriented Si substrates. Unlike the dislocation-free nanowires, the epitaxial III-V nanoridges on SOI still manifest some threading dislocations. As shown by the top inset in Fig. 5(d), the doughnut-shaped TE 01 mode exhibits a substantial overlap with the bottom defective III-V. The interplay of dislocations, intensive light field, and carrier recombination could produce dark line defects and jeopardize   [34]. We can deepen the lateral Si trenches to confine dislocations within the lateral InP crystals, and, at the same time, fine-tune the growth conditions to favor the formation of planar defects and minimize the formation of detrimental threading dislocations. Enabling lasing of the fundamental mode could also reduce the overlap of the light field with the defective layer and simultaneously facilitate light coupling into Si waveguides. Building from the pulse optically pumped 1.5 µm lasers here, future effort will be focused on the realization of continuous-wave (CW) operation and electrically driven lasers. CW lasing usually requires an optimal internal quantum efficiency and a decent heat dissipation. Possible solutions include optimizing the position, thickness, and number of the quantum wells, passivating the nanoridge sidewalls to minimize the nonradiative recombination via surface states, and providing a heat sink with partially etched Si device layers. Electrically driven lasing inside the small III-V cavities necessitates a strong mode confinement within the active region, a minimal optical loss via metal contacts, and a sufficient III-V surface area for low contact resistance and minimal heat generation. Current nanoridge structures might not be able to fulfill these requirements. Lateral overgrowth and special pattern designs could help to enlarge the III-V surface area for minimal optical loss and low-resistance metal contacts.

CONCLUSION
In conclusion, we demonstrated room-temperature, in-plane, and bufferless 1.5 µm III-V lasers directly grown on Si-photonics 220 nm SOI platforms. By synergizing the conventional ART and lateral ART techniques, we designed a growth scheme for the direct hetero-epitaxy of high-quality III-V alloys on the industrystandard 220 nm SOI wafers. Instead of epitaxy inside V-grooved pockets, as widely adopted by other research groups, epitaxy inside trapezoidal troughs eliminates the restriction on the Si device layer thickness and allows flexible integration of different III-V compounds on various SOI platforms. Lateral evolution of III-V alloys from {111} Si surfaces with reduced areas also promotes the formation of planar defects instead of detrimental threading dislocations. Consequently, we were able to demonstrate room-temperature lasing from pure InP nanoridges at the 900 nm band and from InP/InGaAs nanoridges at the 1500 nm band. The laser thresholds are also significantly lower than those grown by the conventional ART method on thicker SOI platforms. These results point to fully integrated photonic circuits processed on 220 nm SOI platforms.