Monolithically Integrated 940 nm VCSELs on Bulk Ge Substrates

This work successfully developed an independent Ge-VCSEL epitaxy and fabrication technology route. This is the second successful Ge-VCSEL technology reported worldwide, and the first Ge-VCSEL technology with key details disclosed, including Ge substrate specification, transition layer structure and composition, and fabrication process etc. Compared with the GaAs counterparts, after epitaxy optimization, the Ge-VCSEL wafer has a 40% lower surface root-mean square roughness and 72% lower average bow-warp. Additionally, the Ge-VCSEL has a 10% lower threshold current density and a 19% higher maximum slope efficiency than the GaAs-VCSEL.


I. INTRODUCTION
Vertical cavity surface emitting lasers (VCSEL) have seen a remarkable rise in demand as compact, low-cost, and scalable near-infrared illumination sources, driven by their integral roles in optical interconnects and 3D sensing.However, as the VCSEL market is expected to increase from $1.6 billion in 2022 to nearly $3.9 billion by 2027, the prevailing use of 4-to 6-inch GaAs wafers hinders production scalability [1].
A typical AlGaAs VCSEL structure heavily relies on AlxGa1-xAs/AlyGa1-yAs superlattice (y > x) Distributed Bragg Reflectors (DBRs).For epitaxy on GaAs substrates, the inherent growth strain, caused by the lattice mismatch between GaAs (5.653 Å) and AlAs (5.660 Å), presents a significant impediment to chip yield and reliability, especially on large GaAs wafers.Bulk Ge substrates emerges as a promising solution, offering a suitable lattice constant (5.658Å, between GaAs and AlAs), resulting in reduced strain (up to 40% less lattice mismatch than GaAs) and enhanced post-growth stability [2].Beyond this, Ge wafers offer enhanced mechanical resilience, reduced threading dislocations, and a competitive cost advantage, especially considering their availability in sizes up to 12 inches [3].
In 2020, IQE showcased the first 940 nm VCSELs on a 6inch Ge wafer, achieving performance similar to co-processed GaAs-based VCSELs [4].However, details on their Ge substrate, transition layer structure and composition, growth conditions and etc., were not disclosed.Our recent independent studies successfully integrated AlGaAs n-DBRs and MQWs on bulk Ge with GaAs/InGaAs/InGaP layers for good transitions.Our bulk Ge-based n-DBRs and half VCSELs structure (n-DBRs and MQWs) have comparable performance, compared to the same structures grown on co-processed bulk GaAs [5][6].
In this study, we successfully demonstrated the monolithic integration of full VCSELs (including n-DBRs, MQWs, and p-DBRs) on 4-inch Ge wafers with GaAs/InGaAs/InGaP layers for transitions.Our results show that the bulk Ge-based full VCSELs produced comparable epitaxy quality with less wafer bow-warp and better surface morphology.Successful lasing was achieved.A thorough discussion on materials, processing, materials characterizations, and electrical testing is as follows.

II. EXPERIMENT DESIGN AND EPITAXY GROWTH
A full VCSEL structure, targeting 940 nm at operation temperature, was designed and grown on Ge and GaAs wafers under optimized growth conditions as shown in Figure 1.
The Ge wafers in this work were n-type, 4-inch, 425 μm thick (100) Ge wafers from Umicore, which has a 6-degree off-cut towards <111> to avoids antiphase-domains (APDs) and enhances step-flow growth.The thickness of the Ge wafers is thinner than the GaAs counterparts due to the larger fracture roughness of Ge.A 100 nm backside SiN was deposed to prevent Ge sublimation.For better transition from Ge, an InGaP nucleation layer, a lattice-matched 950 nm n-Ga0.985In0.015Aslayer, and a 50 nm n-GaAs layer were grown successively on the frontside of Ge wafers.A few 4-inch 625 μm thick GaAs wafers with 2-degree off-cut towards <111> were used as the control samples for comparison.
Huawei Technologies Canada and The University of British Columbia, Vancouver are acknowledged for funding the research.

A. Surface and Cross-section Imaging
Surface morphology of Ge and GaAs wafers after full VCSEL growth was analyzed by atomic force microscopy (AFM) images in Figure 2. Compared to GaAs wafer, smoother surface with no cracks or APDs, and 40% less Ra and Rq values, was observed on Ge wafer, which indicates Ge wafer has better surface quality.Scanning electron microscope images of the cross-sections (not shown here) showed near identical epitaxy layer smoothness and thickness.

B. Wafer Bow-warp Maps
The bow-warp maps of Ge-and GaAs-VCSEL wafers were measured by FLX 2320 made from Toho Technology.The Ge wafer has a 72% less average bow-warp value (10.28 μm) than that of the GaAs wafer (36.59 μm), which resulted from the smaller lattice mismatches between Ge and AlxGa1-xAs DBRs.

C. Electrical and Optical Performance
The VCSEL fabrication began with the formation of p-type ohmic contacts made of Ti/Pt/Au.Subsequently, a nitride layer was deposited as a hard mask for precise dry etching.Circular mesa patterns were formed using inductively coupled plasma reactive ion etch to define the desired device structure.Then, the device underwent a furnace process with H2O and N2 gas, creating a 9.7 and 11.7 μm diameter oxide aperture for GaAsand Ge-VCSEL respectively.A Precision IV Analyzer was used to provide the bias current, and the optical output power was measured by a large-area photodetector at room temperature.Due to the small number of samples available, the VCSEL fabrication process recipe tuning was limited.Nevertheless, Ge-VCSELs achieved successful lasing with a lower threshold current density of 2.33 kA/cm 2 than 2.58 kA/cm 2 of the GaAs counterpart and the 2.39 kA/cm 2 of the IQE Ge-VCSELs [4].In addition, the Ge-VCSELs obtained a 19% higher maximum slope efficiency of 0.37 mW-kA -1 -cm 2 than GaAs-VCSEL.
Although the Ge-VCSEL has lower roll-over currents compared to the GaAs one, this may be due to higher defect density in the transition layers and the non-optimized fabrication process, which will be studied in the future.

IV. CONCLUSION
We independently developed 940 nm AlGaAs full VCSELs on bulk Ge substrates, which is the second successful Ge-VCSEL technology reported worldwide, and the first Ge-VCSEL technology with technology details disclosed.Before the VCSEL epitaxy growth, the process was optimized for Ge and GaAs substrates respectively to ensure good alignment between Fabry-Perot dip and peak emission.Thanks to Ge's much lower threading dislocation density and higher fracture toughness and the high quality of GaAs/InGaAs/InGaP transition layers, our Ge-VCSEL has 40% less surface roughness, 72% less bow-warp, 10% less threshold current density, and 19% higher maximum slope efficiency compared to the GaAs counterpart.This study not only demonstrated the feasibility and revealed the key details of fabricating VCSEL on Ge substrates for mass production, but also paved the way to integrate various III-V based structures on bulk Ge substrates for a wide range of optical and electrical applications.

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Figure 2 .Figure 3 .
Figure 2. AFM images and roughness measurement on 10 × 10 μm surfaces of full VCSELs on (a) Ge substrates and (b) GaAs substrates.Ra and Rq represent average roughness and root mean square roughness respectively.[7]

Figure 4 .
Figure 4. (a) Room temperature L-J-V curves for 940-nm VCSELs grown on GaAs (red line) and Ge (blue line) substrates.(b) Optical power and optical differential efficiency (slope efficiency) as a function of bias currents.[7]