Enhanced Polling and Infiltration for Highly-Efficient Electro-Optic Polymer-Based Mach-Zehnder Modulators

An ultra-narrow slot waveguide is fabricated for use in highly-efficient, electro-optic-polymer-based, integrated-optic modulators. Measurement results indicate that $V_\pi L$'s below 1.2 V.mm are possible for balanced Mach-Zehnder modulators using this ultra-narrow slot waveguide on a silicon-organic hybrid platform. Simulated $V_\pi L$'s of 0.35 V.mm have also been obtained. In addition to adapting standard recipes, we developed two novel fabrication processes for achieving miniaturized devices with high modulation sensitivity. To boost compactness and decrease the overall footprint, we use a fabrication approach based on air bridge interconnects on thick, thermally-reflowed, MaN 2410 E-beam resist protected by an alumina layer. To overcome the challenges of high currents and imperfect infiltration of polymers into ultra-narrow slots, we use a carefully designed, atomically-thin layer of TiO$_2$ as a carrier-barrier to enhance the polling efficiency of our electro-optic polymers. Additionally, finite-difference time-domain simulations are employed to optimize the effect of the thin layer of TiO$_2$. As compared to other, non-optimized, cases, our peak measured current is reduced by a factor of 3; scanning electron microscopy images also demonstrate that we achieve almost perfect infiltration. The anticipated increase in total capacitance due to the TiO$_2$ layer is shown to be negligible. In fact, applying our TiO$_2$ surface treatment to our ultra-narrow slot, allows us to obtain an improved phase shift efficiency ($\partial n / \partial V$) of $\sim$94% for a 10 nm TiO$_2$ layer.


Introduction
Integrated photonic devices have received significant attention during the last decade thanks to their mass production, low power consumption, small footprints, and large optical bandwidths. To meet the demand for ultra-high-speed optical modulation, versatile structures have been studied for optical modulators as key building blocks in various photonic systems including microwave links, optical interconnects, and optical frequency comb generators. Advanced modulators, such as ones based on the plasma dispersion and electro-absorption effects, have been the subject of much recent research due to their promising characteristics. Nevertheless, they are not free of challenges since the maximum frequencies of both types of modulators are limited by their capacitances.
While plasmonic structures have better optical field confinement (i.e., optical field confinement and propagation happens at the metallic surface), SOH has lower loss and is more compatible with CMOS foundry processes. When making EOP-based modulators using conventional strip waveguides, made with Si or other materials, the EOP typically covers the waveguide, and only the evanescent field experiences the change in the refractive index due to the electro-optic effect of the polymer [18]. Because of the large refractive index contrast between Si and EOP (n Si ≈ 3.42 vs n EOP ≈ 1.68), this type of SOH modulator suffers from poor optical-field/EOP overlap for conventional Si strip waveguides. On the other hand, in PC-based structures it is necessary for the EOP to penetrate the PC holes to modify the photonic bandgap properties. This necessitates a precise design and good fabrication robustness, which in turn imposes further costs and complexities. In polymer waveguides, interface layers, e.g., sol-gel silica layers, are commonly used to ensure that the DC electric field at the interface is uniform during polling. Each of the above-described devices has its shortcomings. In order to make low loss modulators with high modulation efficiencies, it has been proposed to use nano-slot Si waveguides in SOH structures. Vertical slots with slot widths from 75 nm to above 210 nm have been both theoretically and experimentally demonstrated to enhance the transverse electric (TE) mode intensity inside the Si nano-slots [19]. Indeed, in polymer-filled slots, the field overlap can be tailored to provide large electro-optic effects and, hence, allow one to make highly efficient modulators.
Si slot-waveguide modulators utilizing EOP have not been free of challenges. Generally speaking, within limits, narrowing of a slot results in a better field overlap and hence, a better modulation efficiency. Slots narrower than 75 nm, however, have not been demonstrated yet due to fabrication difficulties. Even for the case of a 75 nm slot, the necessary high polling current degrades the polling process. The maximum tolerated polling field, before breakdown, is limited due to the high leakage current. Additionally, complete infiltration of the EOP inside the slot is, by itself, a difficult task. Both of these factors deteriorate the in-device, electro-optic coefficient (i.e. r 33,in-device ), a crucial metric for the performance of a Mach-Zehnder modulator (MZM) and, hence, the overall modulation efficiency. These factors, i.e., polling and infiltration, have been widely investigated in Ref. [20][21][22].
To overcome these challenges, wider slots (up to 320 nm [2]) have been employed in conjunction with PC-based waveguides. However, they suffer from design complexity and limited bandwidth. Recently, researchers have proposed the deposition of thin Alumina (Al 2 O 3 ) as an interface for bulk layers of EOP on both Si and ITO (indium tin oxide) substrates [22]. However, this study is limited to bulk epitaxially-grown layers of material, and the authors do not extend it to an applied modulator. Surface passivation necessity has also been studied elsewhere [20], where the authors studied the effect of a titania (TiO 2 ) layer for passivation fabricated by ALD (atomic layer deposition). They concluded that addition of this layer not only decreases the leakage current but also increases the conductivity of Si pedestal and waveguides and hence improves polling efficiency. In this paper, we will focus on the other benefits of applying TiO 2 layers to very narrow slots.
In this paper, we present our approach for a Si-organic hybrid platform that uses EOPs in ultra-narrow slot waveguides to achieve high modulation efficiencies. We report a series of surface preparation and infiltration techniques specifically for narrow vertical slots. We show that our approaches can improve the breakdown polling field and, hence, the r 33,in-device . We also demonstrate near-perfect void-free infiltration to decrease the polling current inside an ultra-narrow 40 nm-wide Si slot. Moreover, we present fabrication details for implementing air bridge interconnects to minimize the device footprints. While the focus in this paper is more on the platform development and not high-speed modulation, our approach does not impose any noticeable bandwidth limitations. In Section 2, we describe the design criteria to obtain various performance metrics as functions of structural factors. Fabrication details are extensively covered in Section 3 while Section 4 presents a discussion of the simulation and experimental results. The paper ends with conclusions in Section 5 drawn from the studies presented.

Design Details
Since the early demonstrations of SOH-based slotted and PC-waveguide modulators, these structures have always suffered from poor Si-organic interfaces causing incomplete infiltration and/or inefficient polling [23]. Ideally, we need to establish a strong DC electric field (i.e., a polling field) inside the polymer without drawing any DC current. Indeed, the leakage current flows between the sidewalls (i.e., between the cathode and the anode), preventing the complete polling of the chromophore molecules and may cause permanent damage/degradation to the polymer. While there is no standard recipe for surface functionalization, we have developed a customized surface treatment that allows us to maintain large electric fields inside the slots required for polling (100 V/cm), and at the same time to avoid reaching the breakdown field of the EOP. This method also helps polymer infiltration, i.e., it blocks air bubble formation at slot sidewalls, due to better adhesion to the sidewalls [24][25][26][27][28][29].
Our proposed SOH-based MZM is depicted in Fig. 1. Among the many performance metrics for an MZM, the modulator sensitivity (i.e., the effective mode index change versus the applied voltage) is one of the most important properties, and it is given by where is the extraordinary refractive index of the EOP, Γ is the field overlap integral, slot is the slot width. The modulator drive voltage (V in ) and footprint are integrated into one single parameter called the modulation efficiency ( ), which is related to by = /2 , where is the optical wavelength, is the half-wave voltage (i.e., the applied voltage that results in an optical phase shift), and is the modulation length. While r 33,in-device is directly related to the maximum tolerable polling field, Γ/ slot is the device geometry factor, which is obtained from both the optical (modal) and DC (polling) fields inside the slot.
First, we need to evaluate the effect of our TiO 2 layer on the device speed. Being directly related to the length, the capacitance of the thin TiO 2 and EOP layers are found to be CTiO 2 ∼110 pF and CEOP∼0.7 pF based on simple, parallel plate approximations within the slots. Here, we neglect the direct capacitance between two rails, i.e., the outer edge of the slot. The total equivalent slot capacitance is dominated by that of the EOP layer, since the contribution of the TiO 2 layer in series with the EOP layer is minimal. On the other hand, the thin TiO 2 layer does not contribute to the total resistance. As a result, the total RC is not increased drastically. Table  1 summarizes the modeling parameters and device geometries that we have used. As reported in [4], adding TiO 2 may even reduce surface charges and, hence, reduce the pedestal resistance by functionalizing it; this would also help to improve the speed of the device. The added TiO 2 can slightly influence the voltage drop across the slot estimated by where is the total applied voltage across the device, is the structure factor, EOP and TiO 2 are the polymer and TiO 2 resistivities, respectively, and the widths EOP and TiO 2 are as shown in Fig. 1(b). Considering the proposed device in Fig. 1, we find ∼0.96. Evidently, one should not be concerned with the voltage drop across the thin oxide layer since it is only important when establishing a DC field for polling the EOP. The oxide interface forms an appropriate barrier for the carriers, which are responsible for the leakage current.
We have simulated the effect of the TiO 2 thickness, among other factors, to see how it impacts various aspects of the device performance. Due to the electric field discontinuity at the slot interfaces, it is well-known that the TE electric field inside the slot (i.e., in the polymer infiltrated region) will be enhanced by 2 Si / 2 EOP (≈3.42 2 /1.68 2 = 4.14 in our device) [5]. In the case of our thin TiO 2 layer, however, this ratio will be decreased to 2 Ti 2 / 2 EOP (≈ 2.61 2 /1.68 2 = 2.41), i.e., by a factor of 2 Si / 2 TiO 2 ≈ 1.717. It is worth noting that the maximum polling efficiency is only possible when two conditions are met simultaneously: 1) optimal field overlap between the polling (DC) field and the optical TE (modal) field is obtained; 2) uniform void-free infiltration of the polymer inside the slot is achieved. The field overlap can be calculated by [15,30] where eff is the effective mode index, 0 is the free space impedance, is the volume of integration,ˆandˆare the modal electric and magnetic fields, respectively,ˆis the applied  Iterative numerical methods are required to solve the coupled equations (3) and (4). Obviously, bothˆ(the electric field component of the optical TE mode) andˆplay important roles in device performance; here, we first examine the role ofˆ. The effect of the DC polling field is inherent in eff , which is calculated along withˆfor every single point inside the slot using frequency domain simulations. Additionally, the denominator in Eq. (3) can be estimated by the total power transmitted in the medium.
As seen from Fig. 2 finite-difference eigenmode (FDE) simulation results can be used to model the effect of the TiO 2 layer on the modal field distribution. For the sake of comparison, we have repeated the calculations for a 100 nm-wide slot. The advantage of the 40 nm structures is suggested by the increased optical field intensity |ˆ| in Fig. 2, and, hence, the increased resulting modulation efficiency ( ). Figure 2 also shows that in case of the 100 nm-wide slot more of the field resides outside the waveguide, where it reaches a maximum of 30 V/ m. The maximum field inside the 100 nm-wide slot is 48 V/ m which is significantly lower than that in the 40 nm-wide slot. Since the TE field inside the 100 nm-wide slot is distributed less uniformly, the average TE field intensity is even lower. Also, adding TiO 2 smooths out the field, which is more pronounced in the 100 nm-wide slot since it starts out less-uniformly distributed, .  the BOX layer Fig. 1(b)). Together with Fig. 2, one may identify two immediate effects of the added TiO 2 layer as: 1) the polling field is enhanced by factors of 30% and 80% for 5 nm and 10 nm of TiO 2 on each side of the 40 nm slot, respectively (that is important because the SEO125B polymer requires a minimum polling field of 100 V/ m for effective chromophore alignment) and 2) the uniformity of the modal field throughout the slot could be improved as shown in Fig. 2. This effect was previously reported in Ref. [23], where the authors employed an interface layer of TiO 2 to enhance polling-field uniformity albeit for non-slots electro-optic modulators. Fig. 3. Normalized (to 1 V applied) electric field distribution inside slots of width (left) 100 nm and (right) 40 nm. Higher polling field along with better field tolerance due to carrier-barrier behavior of the oxide interface result in higher 33,in-device and, hence, better modulation efficiency. Figure 4(a) shows the modal field intensity measured at the midpoint of the slot, where the infiltration of the EOP is most efficient. The thicker the buffer layer, the higher the TE field intensity. Figure 4(b) illustrates the power confinement factor ( ) in the slot. Depositing more TiO 2 into a smaller slot will result in less available space for the EOP. Figures 4(c) and 4(d) show a more intuitive figure of merit, |ˆa vg |, where |ˆa vg | is the average value of |ˆ| within the slot. The thicker the TiO 2 used, the higher the value of |ˆa vg |. Yet, as shown in Fig. 4(d), Γ is reduced by adding more oxide. It is worth noting that, while both are optical-electrical field overlap factors, Γ is different than |ˆa vg |, and it is the parameter that eventually defines the performance of the device.

Device
While 120 nm slots are commonly used in slotted-waveguide SOH modulators, fabricating narrower slots (e.g., 40 nm slots) is much more challenging. Next, we describe those challenges and provide our detailed process flow steps. The modulator fabrication flow diagram is shown in Fig. 5. We begin with a 250 nm / 3 m BOX SOI chip. The slotted waveguide was formed by E-beam lithography (EBL) and dry etching. A JEOL JBX-9300FS EBL System, with a resolution of 20 nm at 100 pA beam current, was utilized to create ultra-narrow slots. For the E-beam resist, our silicon slot was patterned using HSQ 6%, whereas MaN 2403 was used for our pedestals.
It is important to use a gentle, step-by-step etching process (etch rate equal to ∼75 nm/min) to make sure that vertical sidewalls are obtained with minimal surface roughness, especially when making such small slots that will have low optical losses. To succeed in this crucial step, a chlorine-based etch process was used in an inductively coupled plasma (ICP) etching system. The pedestals are designed to have low ohmic losses and to carry both polling and modulation signals to the slot sidewalls. After the formation of the MZM, 150 m x 150 m contact pads of are fabricated in a third EBL step, with ZEP as the E-beam resist. A Denton Explorer E-beam evaporation system is employed for metallization in which a titanium (Ti) layer (10 nm) followed by a copper (Cu) layer (250 nm) are deposited under moderate vacuum conditions (pressure < 3 × 10 −6 Torr). The metal lift-off is processed using 1165 at 80°C overnight for gentle, crack-free interconnects. Then the polymer is prepared and spin-coated according to our recipe (discussed later). The EOP on top of the contacts, formed in the last step, is removed at an elevated temperature (> 130°C) prior to polling. Additionally, we use tunable directional couplers instead of more common multi-mode interferometer (MMI) couplers or Y-splitters, because they allow for balancing of the MZM to maximize the extinction ratio. The 100 nm gap of the directional couplers is protected by an additional layer of flowable oxide (FoX), which otherwise could be filled with polymer during the EOP-deposition process.
To enable contacts for applying electrical signals (both RF and polling), vertical vias made of conducting materials, e.g., tungsten, are usually employed on top of the samples [31] and insulated with SiO 2 . Indeed, achieving metallic contact with the inner parts of the MZM is a challenge due to geometry limitations and demand for the optimum device footprints. Compared to conventional vias, we found that polymer infiltration could be more efficient using our air-bridge-over-photonic-waveguide interconnect approach shown in Fig. 6. This process starts by spin-coating a 1.3 m-thick E-beam resist (MaN 2410) on top of the already formed MZM. One should minimize electrical resistance of the air bridge, which directly affects the polling efficiency. This critical characteristic is achieved by a reflow process in which the sharp corners of the processed rectangles are reduced from ∼ 90°to ∼ 70°. We have determined that reflowing for 2 minutes at ∼ 145°C generates the best outcome. Employing the FDTD simulations, we have determined the geometry requirements of the air-bridge for minimal optical loss. Accordingly, our simulations show that minimum distances of 450 nm from the top of waveguide/slot region and 600 nm from each side of the waveguide are necessary to avoid considerable optical loss caused by the air bridge. In the next step, atomically thin layer of alumina is coated using ALD followed by one further step of E-beam lithography, copper sputtering and subsequent lift-off using Polymethyl methacrylate (PMMA) for metallization. Despite its nanoscale size, our developed process flow resulted in both mechanically-stable and reproducible results for the air-bridge. Depicted in Fig. 7 is the scanning electron microscopy (SEM) image of the fabricated metal air bridge on top of the waveguide.

Material
The most challenging step in making narrow-slot, EOP-filled waveguides is achieving void-free EOP infiltration of the slots [20][21][22]. In addition to the benefits mentioned previously, our TiO 2 surface treatment can help in this regard. We have tested various mechanisms to enhance the polymer-Si interface. First, we ran a customized oxygen plasma cleaning step on the surface (using advanced vacuum reactive ion etching (RIE)). Excessive plasma cleaning, however, damages the waveguides and should be avoided. As illustrated in Fig. 8, we deposited a thin layer (5 nm) of TiO 2 everywhere, including inside the slot, using a Cambridge atomic layer deposition (ALD) system. ALD is known to be the most precise deposition method for thin oxide films with desired thicknesses. ALD also produces a high-quality interface between the Si slot sidewalls and the oxide (TiO 2 ), as compared to alternative methods such as plasma-enhanced chemical vapor deposition (PECVD), and is known to provide conformal coatings even in confined spaces such as under our air-bridges. The ALD process temperature was set to 150°C and a layer of ≈ 0.7 Å was deposited in each cycle. The pulse and purge times in one ALD cycle were carefully monitored to maintain the quality of the oxide coating.
As compared to the standard recipe for SEO125B (6.72% by weight according to Soluxra Inc.), we deliberately diluted the solution by increasing the volume ratio of the solvent (Dibromomethane) to SEO125B by a factor of ∼ 1.5. We have also devised a method called "rotating bubble" for spin coating the EOP as a replacement for the conventional "dropping" method prescribed by the manufacturer. In this method, after dispensing a small amount of EOP onto an unused portion of the chip using a bulb pipette, by continuing to apply pressure to the dispensing pipette's bulb a small bubble of 2∼3 mm diameter is formed at the end of the pipette. This bubble can be used to deposit a thin layer of the polymer (a few hundred nanometers thick) across the surface of the chip by "pulling" the bubble through moving the pipette. Simply dropping the EOP onto the chip's surface leaves a bulky polymer that not only causes an additional loss but also complicates the opening of the windows and causes the EOP to develop harmful cracks. Using our optimized process, we have successfully developed a recipe for the spin coating that decreases the thickness of the EOP on top of the sample from > 3 m to ∼450 nm. During the spin-coating process, due to the viscosity of the EOP, the initial drop does not spread significantly but the thin layer, formed by our technique, flows enough to increase the uniformity of the EOP across the critical portions of the chip. The thickness obtained is adequate since the waveguide height is only 250 nm. It should be noted that our techniques for EOP dilution and "rotating deposition" also help to decrease the additional loss imposed on the input/output grating couplers by the polymer. Consequently, as will be demonstrated later, this should result in better extinction ratios (ERs), which are determined by the optical loss asymmetry of the two arms. Another benefit of our EOP deposition approach is the infiltration inside the slot. By waiting a few minutes after spinning, we allow for the polymer to be pulled into the by the capillary effect. Otherwise, the polymer may not penetrate the slot uniformly. Employing these techniques, we have succeeded in obtaining better polymer infiltrations compared to all reported alternatives [20][21][22].
The coated sample is then heated overnight in a vacuum oven at ∼75°C to remove leftover air gaps/voids from the slot. Figure 9 shows SEM images of the slot with (Figs. 9(a) and 9(b)) and without ( Fig. 9(c)) enhanced polymer infiltration method. Schulz et al. have previously studied the effect of an additive layer of alumina (Al 2 O 3 ) on the non-slotted waveguide [22]. For the sake of comparison, we have also deposited 5 nm of Al 2 O 3 and monitored the infiltration/adhesion of EOP into the slot/Si sidewalls. As seen in Fig. 9 (a), almost-perfect infiltration of the EOP is achieved for the TiO 2 deposited sample whereas for the Al 2 O 3 case (Fig. 9 (c)) only a portion of the slot volume is infiltrated. Figure 9 demonstrates the improvement obtained for the interface between TiO 2 and SEO125B as compared to that between conventional Al 2 O 3 and SEO125B.

Results and Discussion
The linear electro-optic (EO) effect (the Pockels effect) can be induced in the EOP by orienting its chromophore molecules in such a manner that the optical center of symmetry of the polymer is removed [32]. Generally speaking, the larger the polling field inside the slot, the larger the induced EO [32] effect. However, the maximum polling field is limited by the polymer breakdown. SEO125B has a standard polling recipe in which a polling field of at least 100 V/ m should be applied to the polymer. To obtain this field, we minimize the resistance of the 50 nm pedestal and the waveguide rail compared to the thin film EOP. Then, a temperature ramp of 10°C/min is applied, while maintaining the field, to reach a state in which chromophores can be readily aligned. The temperature is increased from 80°C to 150°C, given that the glass transition temperature of the polymer, Tg, is ∼ 145°C. The applied current drawn is recorded throughout this process. Figure 10(a) depicts the cold resistance while Fig. 10(b) shows the measured current versus temperature, for the temperature ramp used during the polling procedure, for a 40 (nm) slot waveguide with and without the TiO 2 layer. Fig. 10. (a) Cold (i.e., room temperature) resistance measurements and (b) the measured current versus time for the temperature ramp used during the polling procedure. Less than one-third of the peak measured current is observed when the thin-TiO 2 protection layer is applied. Fig. 11. Transmission spectra of a slotted, SOH MZM with a TiO 2 passivated surface, a 40 nm slot width, and a 1 mm arm length.
Evidently, our TiO 2 surface functionalization results in a peak current, which is less than onethird of that in the non-treated surface case. Considering a surface area of 250 × 10 −9 × 3 × 10 −3 m 2 , the peak current of 206 nA observed for the TiO 2 -protected case ( Fig. 10(b)) is equivalent to a current density of ≈ 275 A/m 2 . This number is within the range that was reported in Ref. [19], albeit with a 75 nm slot size. Since our device has a 40 nm slot, it is anticipated that a higher , and hence modulation gain, should be achieved. We believe that this improvement is due to the thin TiO 2 layer acting as a "carrier-stopper", along with our improved EOP infiltration. In other words, the high r33,in-device reported in [19] (associated with the higher optical field overlap thanks to PC-based structure) could be even more enhanced using our proposed TiO 2 addition layer. (and hence ) changes in different directions, depending on the TiO 2 thickness. Indeed, the TiO 2 protection layer results in larger possible polling fields with lower currents, and hence better chromophore orientation, i.e., enhanced polling efficiency. To obtain the range of slot widths in which the performance is boosted by adding TiO 2 , we study 33,in-device , shown in Fig. 13. Rewriting Eq. (1), this factor is calculated by 33,in- The benefits of using a 40 nm slot is evident from Fig. 13 in which low values, high 33,in-device values, and large field overlap integrals are predicted. This region is indicated by the yellow band. However, for 33,in-device to be increased, the enhancements that the TiO 2 brings are required. Figure 13(d) illustrates the most fundamental figure of merit, i.e., the modulation sensitivity, , while clearly showing the advantage of using the TiO 2 layer with thin slots. In these estimations, we used the maximum value of 33 ∼ 100 pm/v for TiO 2 -added devices (with close-to-perfect EOP infiltration), and a correction factor of ∼ 0.77 was applied to the case of devices with no TiO 2 layer based on our previous work [33] ( = 3.125 V.mm without TiO 2 compared to 2.39 V.mm with 5 nm TiO 2 , both with 40 nm slots). The advantage of the 40 nm slot along with our surface treatment is clear from Fig. 13. Since the modulation gain is directly proportional to , smaller slots can simultaneously result in higher modulation gains and modulation efficiencies when appropriate TiO 2 layers are added to improve the polling efficiency. Indeed, another advantage of our oxide surface treatment is that it can result in higher  modulation sensitivity for smaller (and hence more challenging, fabrication-wise) slot widths because of better polling (represented by 33,in-device ). In other words, instead of using a 40 nm slot, one can use a 50 nm one and add 5 nm TiO 2 to obtain the same level of field enhancement.
We should also point out that, in this work, we only focused on enhanced polling and infiltration, so lightly doped Si has been used. Applying properly doped Si for the pedestal and waveguide ridges, one may obtain high-speed operation. As investigated in Ref. [20], surface passivation with TiO 2 might result in enhanced conductivity of the pedestals, hence improving the polling efficiency and speed, indicating that we might get two benefits from applying an oxide interface. Even though we have focused on polling efficiency, our electrostatic and electric simulations (using COMSOL Multiphysics) predict a bandwidth of 39 GHz along with a significantly low modulation efficiency of ≈ 0.35 V.mm when carefully doped Si is utilized. Also, the lower drive voltages obtained in this paper can result in reduced transmittance noise figures. Finally, further studies are required to determine the effectiveness of alternate passivation materials, including hafnia (HfO 2 ).

Conclusion
An MZM implemented on the SOH platform was introduced in which we utilized the well-known advantages of slot waveguides and the large electro-optic effects of polymers. To improve the modulation efficiency, slot widths as small as 40 nm were fabricated for the first time. To overcome the challenge posed by the high polling current, which adversely affects the modulation efficiency, we developed a series of fabrication steps to passivate the surface and to improve EOP infiltration based on using atomically-thin layers of TiO 2 . Both FDTD and electrostatic simulations were employed to optimize the geometry of the surface-treated device. For narrow slots featuring TiO 2 passivation layers, we demonstrated a factor > 3 reduction in the polling current as well as a larger polling field, a uniformly-distributed, highly-confined, in-slot modal (optical) field. As a result, we have achieved a larger 33,in-device compared to the case with no surface passivation. Also, almost perfect infiltration, with a very thin (< 450 nm) final EOP layer inside the ultra-thin slot was obtained using our modified polymer spin-coating technique. This study shows that an increase in the polling/RF field inside of the 40 nm (100 nm) slots of 30 (10%) is easily obtained with a buffer layer of only 5 nm of TiO 2 . In other words, without the oxide interface layer, the required polling voltage must be higher to obtain the minimum required field of 100 V/ m for the SEO125B polymer. As discussed in Ref. [22], the maximum field that can be withstood by the EOP can be greatly enhanced beyond the nominal value of 100 V/ m, thus further increasing the modulation efficiency. Also, we have studied the various figures of merit, among which is , and we found that is improved from 1.7 V −1 to 2.07 V −1 for the 5 nm TiO 2 layer and from 1.7 V −1 to 3.3 V −1 for the 10 nm TiO 2 layer inside our 40 nm slot-waveguide modulators. To improve compactness, we have also developed fabrication steps to create air-bridge interconnects to carry electrical signals, instead of using conventional vias. Further studies are required to determine the effectiveness of other alternative materials including HfO 2 . Even though we have focused on the polling efficiency, our simulations show a bandwidth of 39 GHz and a modulation efficiency of ≈ 0.35 V.mm should be obtainable. The lower drive voltages that are made possible using our approaches toward designing, and our methods for fabricating, ultra-narrow EOP-infiltrated slot waveguides will also lead to reduced transmittance noise figures for photonic integrated circuits.

Author Contributions
The main idea of the demonstrated slot modulators along with all designs and fabrication processes were developed and implemented by I.T., A.A.E., and A.A at Georgi Tech. R.D., H.M., and T.F. participated in the fabrication process implemented by I.T., S. S., L. C., and N. A. F. J. and A.T. participated in the simulations. All authors contributed to the manuscript All authors have given approval to the final version of the manuscript.