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Abstract
The high-quality growth of midwave infrared light emitters on silicon substrates will advance their incorporation into photonic integrated circuits, and also introduce manufacturing advantages over conventional devices grown on lattice-matched GaSb. Here we report interband cascade light emitting devices (ICLEDs) grown on 4 degree offcut silicon with 12% lattice mismatch. Four wafers produced functioning devices, with variations from wafer to wafer but uniform performance of devices from a given wafer. The full width at half maxima for the (004) GaSb rocking curves were as narrow as ∼ 163 arc seconds, and the root mean square surface roughness as small as 3.2 nm. Devices from the four wafers, as well as from a control structure grown to the same design on GaSb, were mounted epitaxial-side-up (epi-up). While core heating severely limited continuous wave (cw) emission from the control devices at relatively modest currents, efficient heat dissipation via the substrate allowed output from the devices on silicon to increase up to much higher currents. Although the devices on silicon had higher leakage currents, probably occurring primarily at dislocations resulting from the lattice-mismatched growth, accounting for differences in architecture the efficiency at high cw current was approximately 75% of that of our previous best-performing standard epi-down ICLEDs grown on GaSb. At 100 mA injection current, 200-µm-diameter mesas produced 184 µW of cw output power when operated at T = 25 °C, and 140 µW at 85°C. Epi-up mid-IR light emitters grown on silicon will be far simpler to process and much less expensive to manufacture than conventional devices grown on GaSb and mounted epi-down.
© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
Midwave-infrared (mid-IR) interband cascade lasers (ICLs) [1–8] have demonstrated continuous-wave (cw) operation at temperatures well above ambient and at drive powers considerably lower than for the alternative quantum cascade laser (QCL) [9,10]. These are attractive for low-footprint chemical sensing systems operating at mid-IR wavelengths between 3 and 6 µm [11]. However, a less expensive broadband incoherent mid-IR source such as a light emitting diode (LED), with continuous rather than abrupt light-current (L-I) response (i.e., no threshold), is sometimes preferred for spectroscopy [12–15] or dynamic IR scene projection [16]. Although mid-IR LEDs have been investigated for several decades [12,17,18], until quite recently the maximum continuous wave (cw) output powers for packaged commercial devices operating at room temperature were ≤ 300 µW. Interband cascade LEDs (ICLEDs) have considerably advanced this state of the art, with demonstrated cw output powers of 1–5 mW at 25 °C for devices with peak wavelengths as long as 4.1 µm [19–24].
In parallel to this development of mid-IR LEDs has been a strong push within the community to monolithically integrate mid-IR emitters based on III-V materials with a silicon photonic chip in order to realize on-chip sensors. Because silicon is transparent to wavelengths as long as λ ∼ 8 µm, the silicon-based photonic integrated circuit (PIC) promises a low-cost platform for future integrated MIR sensors. It also offers more attractive thermal properties than the III-V native substrate for ICLEDs (GaSb), allowing the potential for a simpler epitaxial-side-up mounting geometry as we will see in the following sections. The two primary approaches to integrating active III-V devices on silicon platforms are: (1) grow the epitaxial device structure on the native III-V substrate, for example by molecular beam epitaxy (MBE) or metalorganic chemical vapor deposition (MOCVD), and then heterogeneously bond or transfer print the III-V device material to a pre-patterned silicon chip [25–27], or (2) grow the III-V epitaxial device layers directly on a silicon substrate [28,29]. For the mid-IR, both InAs- [30,31] and InP-based [32] QCLs, as well as GaSb-based laser diodes emitting at λ = 2.3 µm [33], grown on silicon have been reported recently. An InAsSb alloy LED grown on a GaSb buffer on Si emitted 6 µW quasi cw with peak wavelength ≈ 4.5 µm at room temperature [34].
For this work, we have pursued the latter strategy to realize the first ICLEDs to be integrated on silicon by growing III-V device structures directly on silicon substrates. The process begins with the preliminary growth of a GaSb buffer layer on an offcut silicon substrate, using the expertise developed at the University of New Mexico which employs a thin AlSb seed layer to assist the formation of a 90° interfacial dislocations array that relaxes the strain in the GaSb epitaxial layer [35]. High-quality ICLED structures are then grown on the prepared GaSb-on-Si substrates, using designs and MBE growth procedures developed at the Naval Research Laboratory [19,21,24].
2. Growth of GaSb buffer layer on silicon at UNM
The GaSb buffer layers with 12% lattice constant mismatch to the (001) silicon substrate were grown in a Veeco Gen 10 MBE system. The silicon wafers acquired from Addison Engineering Inc. were offcut by 4° towards (111). Offcuts in the 2.5–5° range serve to promote the formation of double steps in the silicon when it is annealed in the growth chamber prior to growth. The double steps facilitate registration of the III and V sub-lattices on the (001) plane [35]. Although the chemical-mechanical polished silicon wafer is suitable for III-V epitaxy, it is not specifically designed for this purpose as is in the case of epi-ready III-V substrates. The Si wafer is treated with dilute HF to remove the native oxide and to achieve hydrogen surface passivation. It is then thermally cycled in vacuum to remove hydrogen and any residual oxides. Using procedures developed at UNM, a thin (≈ 10 nm) AlSb layer was then deposited at 500 °C [35]. The AlSb experiences > 98% relaxation by the formation of misfit dislocations that are confined primarily to the (100) plane. The GaSb deposition was then initiated, during which a pure (3×3) reflection high electron energy diffraction (RHEED) pattern after ≈ 150 Å confirmed that a planar growth mode was achieved [36]. The RHEED pattern gradually transitioned from (3 × 3) to (1 × 3) over the first 250 nm of growth, indicating the annihilation of anti-phase domains and the formation of a single-domain GaSb surface. Following completion of the 1-µm-thick not intentionally doped (nid) GaSb buffer layer, the substrate was cooled under antimony overpressure and Sb was allowed to cap the surface. The diminishing intensity of the RHEED pattern indicated onset of the Sb coating when the substrate temperature reached ≈ 150°C. Continuation of the Sb deposition for another 10 minutes resulted in a net cap thickness of 10–15 nm with a sawtooth profile. The silicon wafers with GaSb buffer layers were then packaged and shipped to NRL for growth of the ICLED structures.
3. ICLED design
The active stages were grown to an optimized design used in ICLs that exhibit low threshold current density and high slope efficiency [3,19]. Each ICLED incorporated either 15 or 22 active stages that were grown as a single group. We have previously demonstrated that an ICLED can emit higher maximum cw power with higher wallplug efficiency when the active stages are separated into groups positioned at antinodes of the optical electric field and the device is mounted epitaxial-side-down (epi-down) on a highly-reflective metal contact layer [21]. However, there is no advantage to grouping the stages of devices mounted epitaxial-side-up (epi-up) as in the present case, since most of the top surface is not metallized for high reflectivity.
The same active-stage design was used for all four of the ICLED structures grown on silicon substrates (labeled below as Wafers A-D), apart from the number of stages (15 or 22). A control structure (Wafer E) was also grown to the same 22-stage design on a GaSb substrate. An n-doped InAs-AlSb transition region (total thickness 20 nm) was grown between the active stages and the bottom n+-GaSb contact to smooth the conduction band profile for lower series resistance [37]. A similar InAs-AlSb region (25 nm) also provided a smooth transition from the active stages to an upper n-InAs-AlSb spacer layer (500 nm). The spacer was capped with a thin (20 nm) n+-InAs top contact layer. Further details concerning this baseline design can be found in [8].
4. Growth of the ICLED at NRL
At NRL the GaSb/Si wafers were introduced into a RIBER Compact 21 T MBE system equipped with As and Sb valved crackers from Veeco Mark V, and dual-indium effusion cells specifically designed for growing structures containing complex antimonide/arsenide short-period-superlattices. The onset for desorption of the Sb cap was identified by monitoring the RHEED pattern as the substrate slowly heated, at which point the surface was flooded with Sb. The initial RHEED pattern indicated an amorphous surface (haze with diffuse rings), which persisted until the temperature reached ∼ 420–430°C. The nominal value was consistent from wafer to wafer, although we do not expect this temperature to be accurate because the pyrometer was calibrated for a thick GaSb layer, whereas the present heterostructure stack containing only 1 µm of GaSb transmitted ∼ 35% at the detection wavelength (∼ 1.6 µm). Above 430°C, spots began to appear in the RHEED pattern along with some streakiness. However, a diffuse haze persisted up to much higher temperatures, which was most likely due to oxidation of the Sb cap layer following storage of the substrate for > 9 months. Baking at ∼ 600°C for 10 minutes produced a streaky RHEED pattern that indicated a high-temperature GaSb surface with (1 × 3) surface reconstruction.
The wafer was then cooled to ∼ 530°C, where an additional GaSb buffer thickness of 2–3 µm was grown (300 nm nid followed by the rest with low Te doping) to further decrease the density of threading dislocations. The pyrometer reading drifted slowly downward during the GaSb buffer layer growth before finally leveling at ∼ 490°C. This was due in part to the structure’s changing emissivity (thicker GaSb reduced the transmission to < 5%, which eventually aligned the pyrometer reading with our standard calibration), and also a slight reduction of the heater power to compensate for the thicker GaSb’s higher absorption of the heater radiation. Several calibration growths were performed initially, to assure that the buffer layer would be grown at a temperature roughly consistent with that used for our standard growth of GaSb smoothing layers on GaSb substrates. During this growth, the Sb flux was set ∼ 20% over the stoichiometric condition to promote surface adatom mobility and surface smoothing Next we verified the pyrometer calibration by cooling to the (1 × 5) to (1 × 3) surface reconstruction point and confirming the transition with temperature under standard Sb flux conditions. The wafer was then cooled and moved into the buffer chamber overnight (or removed from the chamber entirely for validation of the process by examining the surface condition). The following day, after a quick thermal cycling to 530°C under Sb flux, a heavily-Te-doped GaSb bottom contact layer was deposited to a thickness of 700–800 nm. This was followed by growth of the ICLED active layers, using standard procedures described previously [38].
Table 1 lists five ICLED samples in the order they were grown. Wafers A-D were grown on offcut Si substrates, while Wafer E was the control sample grown to the same design on a (001) ± 0.1° GaSb substrate from Wafer Technologies. The only substantial difference between the designs is that Wafers C and D had 15 active stages while Wafers A, B, and E had 22 stages. The thicknesses of the bottom GaSb buffer layers grown at NRL also varied slightly, from 2 µm in Wafers A-C to 3 µm in Wafer D, although this difference had no obvious effect on the material characteristics or device performance.
Table 1. ICLEDs grown to the same design on offcut Si (Wafers A-D) and GaSb (E) substrates, with various design and material attributes.
5. Material characterization
Figure 1 shows high-resolution x-ray diffraction spectra for Wafer B. The data were collected using a 3 kW Smartlab Rigaku θ-θ X-ray Diffraction system equipped with a Ge (220) 4-Bounce incidence monochromator. Figure 1(a) is a rocking curve (ω-scan) of the (004) GaSb reflection. Standard analysis [39] of the measured FWHM of 163 arcseconds implies an upper bound on the dislocation density in the low 108 cm−2 range (we assume that the angular component of dislocation broadening dominates). Also shown for comparison is the much narrower rocking curve (FWHM only 21 arcseconds) for Wafer E, the control wafer grown pseudomorphically on a GaSb substrate. The ω−2θ coupled scans in Fig. 1(b) indicate that both wafers display well-defined satellite peaks associated with the periodicity of the ICLED stages. The pseudomorphic growth on GaSb shows sharp clearly-defined satellite peaks to beyond n = 20, which yield a superlattice period of Λ ∼ 425.5 Å (within 1.5% of the designed value of 431.5 Å). The zeroth order SL peak is separated by ∼ 13 arcseconds from the (004) GaSb peak. In contrast, the satellite peaks for the highly-mismatched growth on silicon are broader and weaker, with clear definition only out to orders n = −6 and n = +2. A fit to the peak positions implies a superlattice period of Λ ∼ 410.5 Å, or ≈ 5% less than the design value. Table 1 indicates that all of the growths on silicon (Wafers A-D) had slightly shorter periods, which may have been caused by the vicinal surfaces, the surface undulations, or some other factor. For Wafer B the separation of the zeroth order SL peak, which appears as a weak shoulder to the right of the (004) GaSb peak, is ∼ 72 arcseconds.
Fig. 1. a) Rocking curve for the (004) GaSb peak of Wafer B, which was grown on a highly mismatched Si substrate. The inset shows the analogous rocking curve for Wafer E which was grown pseudomorphically on GaSb. b) Coupled ω−2Θ scan that highlights the periodicity of the ICL stages for Wafer B, where the x-axis is referenced to the (004) GaSb reflection. The inset shows the analogous scan for Wafer E.
Figure 2 shows Nomarski microscope images of the surface morphologies for two growths on offcut silicon (A and B), as well as the control sample grown on GaSb (E) for comparison. The surfaces of Samples A and B are clearly rougher than Sample E, as expected given the 12% lattice mismatch between Si and GaSb. The images for Wafers A and B appear comparable at this scale, and are representative of the 4 samples grown on Si. This similarity contrasts differences in the atomic force microscopy (AFM) images for Samples A-D that will be discussed below.
Fig. 2. Nomarski microscope images of the surface morphology for two samples grown on offcut silicon (A and B) and the control sample grown on GaSb (E).
AFM was performed on each ICLED wafer using a Bruker Dimension Fastscan system. The images were processed and analyzed using the native Nanoscope Analysis software. Figure 3 shows AFM images corresponding to 5 and 20 µm2 scans taken in the center of Samples A, B, and E, with scan direction 45° from the major flat to better capture features parallel to the <110> directions. The control Sample E, grown on GaSb, appears defect-free at this scale; Figs. 3(c) and 3(f) reveal a very smooth surface (RMS ∼ 0.20 nm) with clearly-defined step edges. The samples grown on Si have rougher surfaces (RMS 4 ± 1 nm) with obvious undulations and some defects, as is expected for lattice-mismatched III-V epitaxy on Si. The undulations result from the coalescence of AlSb islands during the initial stages of growth [35]. We first note a defect parallel to the major flat (circled in red) with density ∼1.5×10−1 µm−2 on the surface of Sample A. These defects were also observed in samples C and D (not shown) at comparable densities. However, Sample B, which had a device structure nominally identical to Sample A, was free of these defects over the 3 × 20 µm2 images taken across the sample from center to edge. As such, we hypothesize that these defects are twins or stacking faults originating at the AlSb/Si interface due to variability of the Si wafer surface roughness, caused by a lack of Si homo-epitaxy or from residual oxide on the surface from the HF etch. Figure 2(e) reveals a different, pitted defect (circled in green) present in Sample B at depths up to 25 nm. These pitted defects occur at a density of ∼2.25×10−1 µm−2, which is nearly an order-of-magnitude less than that of the defects parallel to the major flat in Samples A, C, and D. Again, the differences in defect morphology across nominally identical device structures points to different starting morphologies between the III-V/Si virtual substrates. We discuss the impact of these defects on device performance in Section VIII below.
Fig. 3. AFM images of 5 µm2 scans for Samples (a) A and (b) B grown on Si, and (c) Sample E grown on GaSb. (d)-(f) show 20 µm2 AFM images for the same Wafers (corresponding to the images directly above). The Z axis ranges from −15 to 15 nm for Samples A and B and −1 to 1 nm for Sample E. Two different defects are identified for growth on Si, which are circled in red and green
6. Device processing
Figure 4(a) schematically illustrates the circular mesas processed on 10 mm × 11 mm die from Wafers A-E, using standard optical lithography and wet etching techniques. Mesas with diameters (d) of 200, 400, 600, and 800 µm and designed for epi-up emission were first established by wet etching that stopped in the 700-nm-thick bottom contact layer. Then top and bottom contacts were defined in the same step by optical lithography. Both contacts were Ti(20 nm)/Pt(150 nm)/Au(300 nm) metal stacks formed by e-beam evaporation followed by lift-off. Each top contact was a 100-µm-diameter pad at the center of the mesa that blocked a fraction of the ICLED emission from the top. The bottom contact, which was common to all the devices, was formed on the etched bottom surface with 25-µm-perimeter offset from all the mesa sidewalls. Use of the same top and bottom contact metals, as well as lateral injection from the bottom contact, were chosen for convenience in this initial demonstration. Although both are non-optimal because Ti/Pt/Au on GaSb:Te induces an additional barrier voltage of ≈ 0.5 V, and lateral current injection to a large mesa may be non-uniform, future ICLEDs grown on silicon can employ a more optimal contacting architecture. The device contacts were rapid annealed at 300°C for 1 min. Figure 4(b) schematically shows the cross section of a single ICLED with diameter 800 µm.
Fig. 4. (a) Schematic of circular mesas with four different diameters processed on the 10 mm × 11 mm die using optical lithography and wet etching. A Ti/Pt/Au top contact with diameter 100 µm is patterned at the center of each mesa, while the Ti/Pt/Au bottom contact is common. (b) Cross-sectional schematic of a single ICLED.
7. Measurement technique
Following preliminary I-V characterization using a probe station, each die was mounted epi-up by Pb/Sn soldering to a Kovar chip carrier. Wire bonds contacted the individual devices that emitted from the top for spectral and light-current-voltage (L-I-V) measurements.
All measurements were performed with cw current injection. The total output power emitted by a given device was calibrated from the collected power by assuming the incoherent light is emitted in a Lambertian distribution, which was confirmed by measurements on earlier ICLEDs [19]. The emission was collimated with an f/1 ZnSe lens and then focused onto a calibrated Gooch and Housego thermal detector with an f/2 ZnSe lens after passing through a 3.0 to 5.0 µm bandpass filter to reject thermal emission. Both lenses were broadband AR coated, with transmissions of 97% in the spectral range of interest. Spectral characterization was performed by a Bruker Vertex 80 FTIR without the bandpass filter.
8. Device characterization
Devices from all four of the wafers grown on silicon (A-D) functioned as ICLEDs with relatively high yield. In fact, the best devices (from Wafer B) performed comparably to the ICLEDs processed from the control wafer grown on GaSb (E). Sister devices from a given wafer, e.g., 8 of the ICLEDs with 200 µm diameter from Wafer A, 9 devices from Wafer B, 12 devices from Wafer C, and 6 devices from Wafer D displayed very similar L-I-V characteristics, although other devices from these wafers damaged as the voltage increased. The overall device yield for the 200 µm devices was ≈ 75%.
Lateral current spreading, due to anisotropic transport in the thick short-period superlattices comprising the cladding layers and electron injectors, has been observed in ICLs [40]. However, for ICLEDs having no optical cladding layers we do not expect full current spreading from the single 100-µm-diameter contact at the middle of each mesa. This was confirmed by comparing the L-I-V characteristics for devices with different mesa diameters. The larger devices (400–800 µm diameter) were also more prone to damage during testing. Therefore, the detailed characterization results reported below focus almost entirely on the smallest devices with 200 µm diameter, with the caveat that even those data may be affected by non-uniform current injection.
Figure 5 plots the cw I-V characteristics at room temperature for multiple 200-µm-diameter devices from all the processed wafers grown on silicon (A-D), and also a control device grown on GaSb (E). The three devices with 22 stages naturally operate at higher voltage than the two with 15 stages. Note that as the bias becomes sufficient for the interband cascade stages to conduct current and emit light, the devices grown on Si have softer turn-on characteristics than the control device. This may be attributed to leakage currents associated with dislocations. However, the device from Wafer B maintains low current to a higher voltage per stage than the others grown on Si, indicating a lower density of the particular defects that induce leakage (consistent with the lower defect density apparent in the AFM images from Fig. 3). The inset to Fig. 5 plots the J-V characteristics for multiple devices with all four mesa diameters processed from Wafer C. The figure illustrates that higher voltage is required to inject a given current density when the mesa diameter is larger, which is attributable to higher series resistance when current spreading is inadequate to uniformly inject the carriers. We emphasize that whereas dislocations clearly affect the electrical properties of all the devices grown on silicon, the degradation is relatively modest because full shorting by severe damage would lead to linear I-V characteristics and no light emission.
Fig. 5. – Cw I-V characteristics at room temperature for ICLEDs with 200 µm diameters processed from Wafers A-D grown on offcut silicon, as well as a device from the control Wafer E. The inset shows J-V characteristics for multiple devices with all four mesa diameters processed from Wafer C.
Despite the more abrupt I-V turn-on and lower leakage in the control device grown on GaSb, that device damaged at I ≈ 50 mA, due to severe heating and the onset of negative differential resistance associated with the GaSb substrate’s higher thermal resistance compared to Si. This contrasts the case of 22-stage ICLEDs with 200 µm diameter grown on GaSb from [21], which were mounted epi-down for substantially better heat dissipation. Those devices displayed I-V characteristics very similar to those for Sample E up to 50 mA but then continued to follow a nearly flat dependence on voltage up to much higher injection currents.
Figure 6 plots the cw emission spectra at room temperature for representative 200-µm-diameter devices from (a) Wafers A and B and (b) Wafers C and D grown on offcut silicon, along with the spectrum for the control Wafer E grown on GaSb shown on both figures. The undulations in the spectra for devices grown on Si (but not the control device) are Fabry-Perot fringes with period inversely proportional to the total III-V epitaxial layer thickness. These are induced by reflections at the interface between the silicon substrate and the GaSb buffer layer. Note that the spectrum for the ICLED from Wafer B is nearly identical to that of the control device (apart from the Fabry-Perot fringes). This contrasts the roughly Gaussian spectra for the other three devices grown on silicon, which indicate inhomogeneous broadening. The full-width-at-half-maximum (FWHM) linewidth for sample B increases gradually with temperature, from 720 cm−1 at 25°C to 800 cm−1 at 85°C.
Fig. 6. – Normalized cw emission spectra at T = 25°C from representative ICLEDs with 200 µm diameters processed from offcut silicon Wafers (a) A and B (22 stages) at current 100 mA and (b) C and D (15 stages) at current 140 mA. Both plots include the spectrum for a device processed from the control Wafer E grown on GaSb at current 50 mA. The undulations in the spectra for devices grown on Si are Fabry-Perot fringes.
Figure 7(a) plots the cw output powers vs. current at room temperature for epi-up-mounted ICLEDs with 200 µm diameter mesas processed from Wafers A-D grown on offcut silicon, and also the control Wafer E grown on GaSb. All of the devices had 100-µm-diameter top contacts that blocked a portion of the output. Note first that the L-I characteristics shown for devices processed from a given wafer are quite uniform. We also observe a soft L-I turn-on for all the devices grown on silicon, which like the soft I-V turn-on indicates significant current leakage. Nonetheless, at low injection currents where heating is relatively modest, the slope efficiency of 3.3 µW/mA for the ICLED from Wafer B is 65% of the value 5.1 µW/mA for Wafer E grown on GaSb. At higher currents where more heat must be dissipated, the device on GaSb rolls over much more rapidly and then damages, owing to the much lower thermal conductivity of the GaSb substrate, as discussed below. For the devices grown on Wafers A, C, and D, the slope efficiencies ranging from 0.47 to 0.95 mW/A, as well as the cw powers at also 90 mA, are at least a factor of 2.5 lower than those of Sample B. Since those devices also displayed much broader (Gaussian) spectra (Fig. 6), this may be due in part to more rapid Auger decay in material regions where the energy gap is much narrower than the nominal average value.
Fig. 7. (a) Cw L-I characteristics at room temperature for multiple 200-µm-diameter ICLEDs processed from Wafers A-E; (b) Cw L-I characteristics for a device from Wafer B at a series of temperatures.
Figure 7(b) plots the L-I characteristics of an ICLED from Wafer B at a series of temperatures between 25 and 85°C. Note that the output power at I = 100 mA decreases only a factor of 1.3 as the temperature increases by 60°C. This is even less than the decrease of output power by 1.4 over the same temperature range for the epi-down mounted ICLED grown on GaSb that was reported in [21].
Figure 8 compares the cw output power vs. current at room temperature for several ICLEDs from Wafer B to that of an epi-down and AR-coated device reported in [21]. The latter structure was grown on GaSb with 22 active stages divided into 4 groups positioned at antinodes of the optical field. In order to directly compare the different devices, the right and left power scales of this figure differ by a factor of 1/3.3 to account for the combined effects of: (1) 30% lower emission from the AR-coated output surface of the earlier device; (2) at least 25% blockage of the emission by the top metal contact of the devices on Si (non-uniform current injection due to incomplete spreading may make this factor larger); and (3) minimal reflection of downward-emitted and multiply-reflected light at the unpolished Si substrate to the top output surface, as compared to the Ag top contact of the epi-down device that redirected ≈ 90% to the bottom output surface. We find that within this factor of 3.3, the difference in output powers is primarily attributable to current leakage.
Fig. 8. – Cw L-I characteristics at room temperature for ICLEDs from Wafer B, compared to an epi-down and AR-coated device from [21] that was grown on GaSb with the active stages divided into 4 groups positioned at antinodes of the optical field. The right power scales is adjusted by a factor of 3.3 relative to the left to account for the combined disadvantages of no AR coating on the device from Wafer C, partial blockage of output by the top metal contact, and minimal reflection from the unpolished Si substrate.
To quantify the core heating in the epi-up devices, we monitored emission from a 250-µm-diameter area centered on a 200-µm-diameter mesa by placing a 500 µm aperture and an 8–12 µm bandpass filter in front of the thermal detector. Figure 9 plots the thermal detector’s lock-in voltage as a function of heat sink temperature for Wafer B at zero bias (black points) and when operated at ≈ 100 mA (red points), which corresponds to 1 W of injected electrical power (32 kW/cm2). The curves are fits to the data. The observed temperature increase of ≈ 26°C at room temperature yields a thermal insulance of ≈ 8°C-cm2/kW. We expect the core heating in the device grown on GaSb to be higher by ≈ 4.7, the thermal conductivity ratio for Si vs. GaSb [41]. We have not experimentally characterized the corresponding thermal insulance for devices grown on GaSb and mounted epi-down, as in [21]. However, the thermal spreading resistance of the CuW heat sink is estimated to be only 33% lower than that of Si based on the ratio of thermal conductivities. Epi-down devices must also overcome the insulance of the solder and any thermal contact barriers, although these should be much smaller than the thermal spreading resistance. Thus we estimate that the thermal resistance penalty for growing on silicon and mounting epi-up, as compared to growing on GaSb and mounting epi-down, is no more than 20–30%. This is consistent with the observation that in Fig. 8, the thermal rollovers of the devices from Wafer B do not appear substantially worse than that of the device from [21].
Fig. 9. – Lock-in voltage measured by a thermal detector (8–12 µm bandpass filter) surface probe of an ICLED processed from Wafer B as a function of heat sink temperature, at zero bias (black points) and with 1 W of injected electrical power (red points). The curves are fits to the data.
9. Conclusions
We have demonstrated the first successful growth of interband cascade LEDs on silicon. Performance approaching that of devices grown on GaSb substrates has been demonstrated, despite rougher surfaces (apparent from the Nomarski images) and a softer turn-on of the I-V characteristics.
The silicon substrates with 4° offcut toward (111) were prepared at UNM by first growing a thin AlSb layer that confines most of the dislocations to the (100) plane, where they are benign to device performance. A 1-µm-thick GaSb buffer was then grown, which was capped with a thin Sb layer. At NRL the Sb cap was desorbed and then a 2–3 µm GaSb buffer layer grown before storage overnight under vacuum. Growth on the next day began with an n+-doped GaSb bottom contact layer of thickness 700–800 nm, the active ICLED stages, and finally an n+-InAs top contacting layer. Four ICLED structures with 15 or 22 active stages were grown on silicon substrates (Wafers A-D), and a fifth control wafer (E) was grown on GaSb to the same active stage design.
The ICLEDs processed from Wafers A-D all operated with relatively high yield. Moreover, the cw powers of devices processed from Wafer B were comparable to those of prior epi-down-mounted devices grown on GaSb [21] when differences in architecture are taken into account. This contrasts the efficiencies of devices processed on Wafers A, C, and D, which were more than 2.5× lower. Furthermore, the emission spectrum of an ICLED from Wafer B was nearly identical to that from the control wafer, whereas the spectra of devices from Wafers A, C, and D had nearly Gaussian profiles that indicated inhomogeneous broadening. AFM images of the latter three wafers revealed defects running parallel to the major flat, which did not appear in any probed region of Wafer B. In all cases, sister devices processed on any given wafer displayed similar performance.
There appears to be correlation between the densities and types of defects revealed by AFM characterization (Fig. 3) and the performance of devices processed from a given wafer, although the physical nature of the defects and the mechanisms governing their effects on performance have yet to be explored. Since nearly identical protocols were used at NRL to grow all the active structures, we suspect that the substantial differences in ICLED performance resulted from differing qualities of the GaSb buffer layers deposited on Si, or the Si wafer itself. It will be critical to devise a method for pre-screening the GaSb-on-Si wafers for the presence of detrimental defects before device structures are grown on them. Future work will focus on positive identification of the defects responsible for current leakage, the relation of those defects to dislocations, the step at which the defects are introduced, and how the substrate selection, GaSb buffer growth, and/or device growth must be altered to reproducibly mitigate the defects. The present demonstration may be viewed as an encouraging proof of concept that this is possible.
An advantage of ICLED growth on Si is that waste heat can be dissipated nearly as efficiently with epi-up mounting as for epi-down devices grown on GaSb. This is significant because epi-up processing is far simpler, higher-yield, and potentially less expensive. For example, it would not require thick gold plating on top of the mesa, or a bottom metal patterned with an emission window for contacting the substrate, which are both needed to process epi-down devices. In addition, Si substrates would be much less expensive than GaSb. These benefits may potentially extend to epi-up-mounted interband cascade lasers grown on Si that will provide a similar thermal advantage.
We also emphasize that all three of the factors mentioned in Section VIII that reduce the efficiency of the present epi-up ICLEDs grown on Si can be mitigated. First, the bottom surface of the Si substrate can be polished and metallized to provide reflection that redirects light upward to the output surface at the top of the mesa. Second, the 100-µm-diameter top metal contact that blocks a substantial fraction of the emission can be replaced by a low-fill grid of metallized strips that blocks a much smaller fraction of the light. Furthermore, the grid can be applied to an arbitrarily-large surface area that allows uniform current injection into mesas with diameters much larger than 200 µm. And third, an AR coating can be deposited on a top emission surface that has already been contacted by the metal grid. These relatively straightforward modifications should substantially improve the out-coupling efficiency.
For enhanced efficiency and output power per unit area, epi-down mounting will also be possible using two top contacts. The active stages could then be grouped and positioned at the antinodes of the optical field as in [21], and the output surface on the bottom of the silicon substrate could be patterned with a motheye structure that suppresses total internal reflection for enhanced out-coupling efficiency [42].
Funding
Amethyst Research, Inc. (NCRADA-NRL-18-642); Air Force Research Laboratory (FA8651-17-C-0070).
Acknowledgments
None
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time, but may be obtained from the authors upon reasonable request.
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