High-speed Si / GeSi heterostructure Electro Absorption Modulator

The ever-increasing demand for integrated, low power interconnect systems is pushing the bandwidth density of CMOS photonic devices. Taking advantage of the strong Franz-Keldysh effect in the C and L communication bands, electro-absorption modulators in Ge and GeSi are setting a new standard in terms of device footprint and power consumption for next generation photonics interconnect arrays. In this paper, we present a compact, low power electro-absorption modulator (EAM) Si/GeSi hetero-structure based on an 800 nm SOI overlayer with a modulation bandwidth of 56 GHz. The device design and fabrication tolerant process are presented, followed by the measurement analysis. Eye diagram measurements show a dynamic ER of 5.2 dB at a data rate of 56 Gb/s at 1566 nm, and calculated modulator power is 44 fJ/bit. Published by The Optical Society under the terms of the Creative Commons Attribution 4.0 License. Further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation,


Introduction
It has been shown [1] that the Annual Global IP traffic is expected to exceed a zettabyte (1 trillion gigabytes) in 2017 and then double by 2019.An integrated photonic system based on CMOS based silicon photonics circuitry is considered to be a key enabling technology for highly integrated optical interconnects providing a means to cope with the rising data rate requirements and associated costs.Over the last two decades, research efforts have been pursued to develop integrated silicon and multilayer based systems [2][3][4][5][6] including high speed photodetectors [7][8][9][10], wavelength division multiplexing (WDM) filters [11,12] and modulators [13][14][15].Often the modulator is seen as the workhorse at the heart of an optical transmission link.In group IV based materials, especially silicon, the free carrier dispersion effect is the most commonly used physical mechanism to enable phase modulation.Amplitude modulation is therefore obtained with interferometric devices such as Mach-Zehnder Interferometers (MZI) [16][17][18].Nowadays MZI-based device [19,20] are reaching maturity in terms of fabrication stability and performance nevertheless a common and inevitable issue of this class of modulators is the intrinsic footprint that remains on the order of mm 2 , leading to power consumption levels of the order of the ~pJ/bit.The power consumption can be reduced dramatically using resonant devices such as ring resonators [21,22] or photonic crystals [23], but the advantages have to be mitigated by issues linked to fabrication and temperature tolerance as well as reduced operational optical bandwidth.To alleviate some of these issues whilst increasing bandwidth density, low power consumption, optical bandwidth and switching speed; Ge and/or GeSi electro absorption modulators (EAM) based on the Franz-Keldysh (FK) [24,25] effect can be envisioned.
Progress in GeSi deposition onto Si [26,27] makes these alloys suitable, in particular, for large scale integration and pushes further the limits of modern telecommunication systems.In a recent work, we have also demonstrated [28] the possibility of fine wavelength tuning over 40 nm by means of rapid thermal annealing, enabling the possibility of tunability of modulators arrays working at specific wavelengths.Therefore, covering some of the requirements for WDM in telecommunication [29] whilst providing a platform enabling channel number scalability.
In this paper, we present an innovative Si/GeSi hetero-structure modulator developed on an 800 nm thick Silicon-On-Insulator platform.The device, is formed by a wrap-around PIN hetero junction in a rib waveguide with dimensions of 1.5 µm x 40 µm.The advantage of the structure is provided by the wrap-around diode structure enabling a better control of the junction width whilst alleviating the constraint linked to the width of the waveguide.The coupling scheme chosen between the SiGe waveguide and the Si waveguide grants selfalignment of the waveguide between the two materials simplifying the fabrication process.The customizable device structure and simple manufacturing process also allow high speed performance and large manufacturing tolerances.
The device eye is measured at a data rate of 56.2 Gb/s and shows a dynamic ER of 5.2 dB and modulator power of 44 fJ/bit.The 3 dB bandwidth of 56 GHz demonstrates a leading capability of this design for high speed applications.

Modulator design
The fabricated modulator is based on the FK effect, where an applied electric field modifies the optical properties of direct bandgap semiconductors by increasing the absorption of photon with energies near the material bandgap.The absorption change is reached in less than a picosecond [30] allowing fabrication of amplitude modulators where data rate can exceed 50 Gb/s.
A wrap-around PIN Si/GeSi hetero-structure is chosen for the modulator and implemented in an 800 nm platform.The heterostructure design in Fig. 1 shows the diode configuration integrated in a 1.5 μm wide rib waveguide, where the P doping is defined in a 100 nm thick silicon layer (light green), the intrinsic region (total thickness of 600 nm) is defined by a bottom Ge seed layer (black) and a GeSi area (gold) where the N doping (thickness ~100 nm) follows the contour of the top of the rib waveguide (orange/red area).Compared to previous works, this solution is advantageous because the waveguide width does not interfere or limit the strength of the electric field distribution and can also be tailored to improve, if required, the propagation of both polarizations and optical confinement of the optical mode.Electro-optical simulations, using Silvaco and Matlab tools, were carried out to engineer the cross-section parameters such as the rib waveguide dimensions, the doping profiles and levels for maximizing the electric field and series resistance.The optical model for GeSi is based on the pioneering work from Liu et al. [31] to exploit the FK effect and find the best trade-off between optical loss and device speed.Indeed, whilst high doping levels can lead to low resistance, making the device potentially very fast, they can also induce strong optical losses.On the other hand, low doping level reducing the optical loss at the cost of higher resistance is not suitable for high-speed operation purposes.The engineering of the doping profile is, also, of critical importance as N+/P + doping species diffusing in the intrinsic region increase the optical loss.
In Fig. 2(a) the TE mode distribution from the optical simulation is overlaid with the electric field distribution at −2 V, in the area delimited by the dashed line of Fig. 1.However, for an applied voltage of 2 volts, the electric field remains strong (~40 kV/cm) in the core of the rib waveguide, ensuring a good electro-optical overlap.In Fig. 2(b), a horizontal cut of the electric field distribution along the dashed line of Fig. 2(a) is compared to electric field distributions found in [32,33].We can take note that, unlike our wrap-around geometry, these demonstrations are based on lateral pin implantations that inherently limit the width of the waveguide as a larger width is likely to decrease the field strength over the optical mode.For this reason, the fabrication tolerances and the effect of the waveguide width on the electric field is lowered dramatically.Another aspect of this concept is the possibility to tune the polarisation sensitivity of the modulator without affecting the electric field strength.Finally, because Si and GeSi can be dry etched using a single etch step, it is here possible to simplify the fabrication process by defining the SOI waveguide and the Si/GeSi device at the same time, hence avoiding overlay misalignments.The interface loss between Si and the Si/Ge/GeSi stack for a wider waveguide configuration is estimated to be up to 0.3 dB loss per facet for TE polarisation.

Fabrication
The main process steps are shown in Fig. 3.The fabrication is performed on an 800 nm thick Silicon on insulator wafer with 3 µm buried oxide.Trenches of 50x40 µm 2 are defined by etching the top silicon layer leaving 100 nm of silicon at the bottom of the cavity.Then, the bottom P + doping area is formed using a Boron implant Fig. 3(a) and doped to a concentration of ∼10 18 cm −3 .The GeSi layer is selectively grown in the cavity using RPCVD by growing ~100 nm of low temperature Ge buffer layer followed by an overgrowth of GeSi with a Si nominal composition of about 1.5%.The thin Ge layer is used as a low temperature "seed" for the growth of high quality GeSi layer at high temperature.The GeSi layer is then overgrown to make sure the cavities are filled with the compound material over the whole wafer.The wafer is then put through Chemical mechanical polishing (CMP) to planarize the GeSi structures and remove the excess of GeSi above the Si layer.
The wrap-around PIN rib junction is then formed by a two-step etch.First, only the left hand side of the cavity is etched by about 200 nm Fig. 3(b), then another 400 nm etching is performed for defining the waveguide rib and the coupling gratings Fig. 3(c).For optical normalisation purposes, a silicon waveguide with identical length is etched next to every device.On the left hand side of the rib, the total etch depth of the trench is 600 nm, ensuring the highly doped P + + layer could be defined across the whole 100 nm Ge buffer layer.On the right hand side of the rib, the 400 nm etch depth ensures the formation of the rib waveguide.Once the rib doping regions have been defined, high dose ion implantation steps are performed, P + + using BF2 on the left side in the germanium recess Fig. 3(d) and N + + (Phosphorus) on the right hand side, in the GeSi slab Fig. 3(e).The target doping concentrations are ∼10 20 cm −3 and ∼10 19 cm −3 , respectively.The last implantation step Fig. 3(f) is performed at 45° to define the wrap-around junction formed by the N + phosphorus doped surface layer with a concentration target of ∼10 18 cm −3 .Finally, RTA activation at 650 °C, oxide deposition, VIAS definition and metal deposition/etch conclude the fabrication run.A FIB cross section, highlighting the two-step etch result, and metallisation is shown in Fig. 4.

DC measurements
The performances of our device are first measured in DC using the setup illustrated in Fig. 5.Each device is electrically probed using tungsten tip DC probes from Cascade Microtech.A Matlab routine allows to measure the optical and electrical behaviours of the EAM independently.The major contributions to the dark current are estimated to originate from surface current and crystal defects and to increase the static power consumption.For this device, the dark current level is measured to be below 1 µA at a reverse bias of 2 V, further reduction of the leakage current could be achieved by improving the epitaxial seed layer and the surface passivation step.
Optical transmission spectra are then measured in DC in order to determine the modulator performances which, in EAM, are a compromise between loss without electric field (IL) and absorption variation for a given voltage swing (ER).In Fig. 6(a), the Insertion Loss (IL) and the Extinction Ratio (ER) for different applied voltages are depicted, respectively.For the proposed structure, the IL is due to the Ge direct bandgap and GeSi indirect bandgap absorption and extra loss linked to the built-in electric field, coupled to doping loss and waveguide loss.The simulated loss at the interface between the Si and GeSi waveguide is removed.It is important to point out that the total insertion loss is increased by the presence of the underlying Ge layer that is intrinsic to the adopted process rather than the design and introduces a second ER peak for wavelengths above 1570 nm.Therefore, it is expected that an improved epitaxial growth recipe would improve dramatically the IL.
The ER spectrum reaches a maximum peak of 3 dB for a reverse bias of 1 V at 1540 nm.For higher reverse biases, the ER increases up to 7.5 dB (bias = −4 V); this translate to a calculated incremental ER rate of about 1.5 dB/V around 1540-1545 nm.
To assess the EAM performance across the C and part of the L band, we define the FOM = ER/IL as the ratio between the losses with and without reverse bias.The FOM, depicted in Fig. 6

High-Speed measurements
The high-speed measurements setup includes a 56 Gbps pseudorandom binary sequence (PRBS) generator coupled to an RF amplifier where the signal is attenuated (using in line RF attenuators) to the require swing voltage.A bias T sets the reverse voltage and the signal is fed to GS probes, which are not 50 ohms terminated.A low noise EDFA coupled to a bandpass filter is also used to amplify the modulated optical signal to the DCA, the fixed wavelength optical signal is generated by an Agilent tunable laser coupled to the EAM using grating couplers.The overall diagram of the setup is shown in Fig. 7.The RF signal has a voltage swing of 2.2 V peak-to-peak or ~2.7 V rail-to-rail while the DC reverse bias is 2.7 V. Figure 8 shows the input electrical eye diagram and Fig. 9 shows the measured optical eye diagram from the device operating at 1566 nm.This wavelength is chosen to obtain the best trade-off between the FOM and the optical measurement limitation of our setup.The observed open eye has a dynamic ER of 5.2 dB at a speed of 56.2 Gbps.In this case the data rate is limited by the pattern generator and setup at our disposal.It must be noted that, since the GS probes are not 50 ohms terminated, there is a signal increase of the RF peak to peak voltage applied to the device.The estimated voltage at the device ports, reaches a ~4 V peak-to-peak.The RF reflection is successfully attenuated by a 6dB in-line microwave attenuator.As shown in Figs. 8 and 9 below, the rise time of the optical eye is τo = 16.8 ps whilst the rise time of the electrical input eye is τ e = 15.6 ps.The device rise time can be defined by: From Eq. ( 1), we calculate τ r for the available readings (Table 1), which indicates an analogue EO modulation bandwidth ranging from 42 GHz up to 66 GHz, with a current value of 56 GHz.Measuring the S11 and parameters, the EAM electrical equivalent circuit (Fig. 10) is modelled.The equivalent electrical circuit consists of the pad capacitance C pd , the series resistance R S , the p-i-n junction resistance R J , the p-i-n junction capacitance C J , the capacitance due to the BOX layer C ox , and the resistance due to the SOI and substrate R Si .Using the Sparameters model available in Agilent Advance Design System, we found the lumped element values of the equivalent electrical circuit to match the experimental data, as shown in Fig. 11.We calculated C pd = 5 fF, R S = 150 Ω, R J = 1500 Ω, C J = 11 fF, C ox = 30 fF and R Si = 350 Ω.We can, then, calculate the power of the EAM at 56 Gbps to be  In Table 2 our device is compared to devices found in the literature [32][33][34].The first iteration of the Si/Ge/GeSi heterostructure device demonstrated here, is a transitional device that is currently affected by epitaxy constraints and the extra insertion losses generated by the Ge seeding layer.Future work will therefore focus on either direct GeSi-on-Si growth or Si diffusion into Ge to achieve a uniform GeSi layer throughout the entire cavity with an aim to reduce the IL.Nevertheless, the compact footprint, the low energy per bit, and the high bitrate demonstrate the capability of this design.Furthermore, we believe that the proposed design provides important advantages such as simpler, and more tolerant fabrication due to the possibility to fabricate a diode in a wider GeSi waveguide with a simple self-alignment of the GeSi waveguide to the Si waveguide.The concept also provides a better control of the junction width due to the low dependence on implantation depth enabled by the wrap-around doping profile whilst the opposite doping type (n-type) is being contained within the bottom silicon layer.

Conclusion
We have designed, fabricated and characterized a high-speed GeSi EAM developed on an 800 nm SOI platform, built in a 1.5 μm wide rib waveguide.Operating at a wavelength of 1566 nm, we have demonstrated a data rate, limited by the measurement setup, of 56.2 Gb/s, with a dynamic ER of 5.2 dB.With a small device footprint of 60 µm 2 , the modulator power consumption and EO modulation bandwidth have been calculated to be 44 fJ/bit and 56 GHz, respectively.The wrap-around junction design enables, a simple, tolerant, and customizable fabrication process for high-speed and compact electro absorption modulators.Finally, the high EO modulation bandwidth and bandwidth density (~1 Pbit/s/mm 2 ) demonstrated by this device, coupled with the ability to vary the waveguide width without sacrificing the electric distribution, should ensure this concept to be one of the leading candidates for the next generation highly integrated WDM based telecommunication systems.

Fig. 2 .
Fig. 2. (a) Overlay of the TE mode distribution (grey contour) and the electric field distribution (coloured contour) at −2 V. (b), the extrapolated electric field along the dashed line compared with different works [32,33].
(b), is a good indicator of the trade-off between extinction ratio and insertion losses for a voltage swing from −1 V to −4 V.It is clear that the FOM is affected by the IL of the device nevertheless the modulated ER between −1 and −4 volts stays constant across the whole C band and part of the L band enabling the FOM to reach a value of 1 at 1590 nm.

Fig. 6 .
Fig. 6.(a) Measured Insertion Loss and Extinction Ratio for different reverse biases, (b) ER, IL ratio for the selected high speed modulation voltage swing.

2 J
Vpp /4 = 44 fJ/bit C with the swing voltage Vpp = 4 V (taking into account the signal increase due to GS probe without termination).