High-alignment-accuracy transfer printing of passive silicon waveguide structures

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.


Introduction
Photonic integration is a rapidly evolving technology and finds applications in many different fields including telecommunication and sensing [1]. The use of silicon-on-insulator (SOI) provides a platform with high refractive index contrast and a CMOS compatible fabrication process, which results in potentially high-yield and low-cost, high volume fabricated devices. Over the years efficient passive components (e.g. waveguide structures and gratings [2]) and active devices (Ge photodiodes [3], Si [4] and Ge modulators [5]) have been developed on this platform, including their monolithic co-integration, demonstrating advanced optical transceivers [6]. However, a full process flow for monolithic integration involves more than 30 mask level processing steps in a fab, which impacts the turn-around time, and hence the photonic integrated circuit (PIC) product development cycle time.
A possible solution is to apply a novel integration technology called micro-transfer-printing (μTP or transfer printing [7] [8]). It is based on patterning dense arrays of devices on a source wafer and selectively picking and printing the devices on a target wafer with high yield using an elastometric polydimethylsiloxane (PDMS) stamp, potentially in a massively parallel fashion. The concept is illustrated in Fig. 1.
Using such an approach, one can consider printing active devices, but potentially also passive devices, on a silicon photonics target wafer. This way, a new PIC device generation only requires the reiteration of the passive waveguide circuitry, substantially shortening the turnaround time. Moreover, active and passive device integration with other PIC platforms (e.g. silicon nitride [9]) now becomes feasible. We recently demonstrated the use of the technology to integrate waveguide-coupled Ge photodetectors on a silicon photonics platform [10] using a divinyl-siloxane-bis-benzocyclobutene (DVS-BCB) adhesive bonding layer. The approach can also be applied to other types of source wafers, such as III-V semiconductors. This approach then also enables the wafer-scale integration of III-V opto-electronic components such as lasers and photodetectors on a silicon photonics platform [11][12][13].
In this paper we present the development of the transfer printing of passive silicon devices on a passive silicon-on-insulator (SOI) waveguide circuit as a stepping stone towards the realization of 3D photonic integrated circuits and active/passive integrated waveguide circuits based on transfer printing. For this one needs to design alignment-tolerant optical interfaces that allow high-efficiency optical coupling between the target SOI waveguide structure and the silicon device coupon, in order to accommodate for misalignment during the printing. In section 2, these alignment-tolerant interfaces are discussed. Section 3 deals with the technological development of the release of passive silicon devices from their silicon handle wafer and their transfer-printing. In section 4 the measurement results of the optical coupling between the SOI target waveguide circuit and the silicon device coupon are discussed.

Alignment-tolerant coupling structures
When a silicon device is transfer printed on top of and coupled to an SOI target circuit, the point of interest is to develop a Si-to-Si coupling scheme which is compact (as short as possible) and broadband (efficient operation over the telecommunication wavelength range), while being alignment tolerant (efficient operation at ±1 μm misalignment).
An adiabatic taper can be considered for this purpose. Such a coupling structure is schematically depicted in Fig. 2a), including the DVS-BCB adhesive layer that will be used in the transfer printing experiments discussed later in the paper. A structure with a two-step transition is proposed. The first transition consists of coupling the transverse electric (TE) fundamental mode of a 220 nm fully-etched (WG) input waveguide on the target wafer to a 150 nm thick, 80 nm etched waveguide (150 nm SK) on the printed device coupon. The silicon waveguide on the target wafer tapers from 800 nm to 150 nm width over a length of 100 μm, while the waveguide on the silicon coupon tapers from 150 nm width to a width w2 over a length of 25 µm. The second transition happens in the printed coupon, from a 150 nm thick silicon waveguide (150 nm SK) to a 220 nm thick 150 nm etched silicon waveguide (220 nm SK).
As a second option a vertical directional coupler structure can be considered as well as a Sito-Si coupling scheme. Two identical waveguides placed in close proximity can result in a complete optical power exchange between the two waveguides. We can implement this by using two identical 220 nm SK silicon waveguides, the schematics of which is depicted in Fig.  2b). In this case the vertical directional coupler is implemented in waveguides with a width w that is substantially wider than a single mode 220 nm SK waveguide, this in order to improve the misalignment tolerance. A parabolic taper structure with length L2 can then be used to transition to a single mode 220 nm SK waveguide on both target and coupon.
The coupling efficiency of the adiabatic taper structure is simulated using a finite difference time domain (FDTD) software. The directional coupler structures were analyzed using eigenmode expansion simulations. A 150 nm thick DVS-BCB layer is assumed in the simulation. The coupling efficiency critically depends on the waveguide width w2 and w for the taper structure and the directional coupler respectively, especially when the lateral misalignment tolerance is considered as shown in Fig. 3a). A 1310 nm TE polarized input mode is assumed in these simulations. For the directional coupler structure a coupling length L of 20 μm was used.
For the adiabatic taper structure with a waveguide width w2 of 4 μm one can achieve >75% coupling efficiency at ±1 μm misalignment. In the case of a directional coupler structure, using a 4 μm wide waveguide, one can achieve about around 80% coupling efficiency at ±0.6 μm. The efficiency slightly increases to 85% for lateral misalignment of ±1 µm what can be explained by excitation of higher order modes that can combine for higher coupling efficiency at the fundamental mode. ±1 µm longitudinal misalignment has no substantial impact on the coupling efficiency both for the parabolic taper and for the directional coupler. The other fixed parameters were studied but have less influence on the device performance.
Bandwidth simulations (Fig. 3b)) show that the adiabatic taper structure is optically broadband, covering all the telecommunication bands. For the case of directional couplers two bands couple efficiently for L = 20 μm (around 1330 nm and 1600 nm).

Layout of the silicon device coupons and target waveguide structures
Silicon device coupons and target waveguide structures were designed on imec's passive 220 nm silicon photonics platform, comprising a full (220 nm), shallow (70 nm) and socket etch (150 nm). The layout of the device coupons is schematically illustrated in Fig. 4. The design contains two couplers per coupon and a waveguide loop. For the experiments discussed in the remainder of the paper, an adiabatic taper structure with w2 = 4 µm and a directional coupler structure with w = 4 µm, L = 20 µm and L2 = 70 µm was selected.  The layout of the silicon photonic target waveguide structures is shown in Fig. 5. Using two grating couplers on the silicon target chip, one can couple the light in and out of the silicon device coupon to extract the coupling losses. To achieve precise alignment during transfer printing, it is crucial to add transfer printing (TP) alignment markers both on the silicon target waveguide structure as on the device coupon.

Layout of the tether structures
In order to make a device transfer printable, one has to release the device from the handle wafer. This is achieved by etching a release layer, while protecting the device. In order to still keep the devices attached to the substrate after the etching of the release layer, tether structures are designed that keep the device coupons in place. Several tether shapes and pitches were evaluated. We conclude that triangular tether structures breake at the narrowest points during device pick-up and therefore work most efficiently for the considered silicon devices. The layout of the tether structures used in the experiments is shown in Fig. 6, both for a 300 µm long coupon (for the adiabatic taper structures) and for the 150 µm long coupons. The most optimal tether width is about 1.2 -1.5 µm for efficient break avoiding any contamination, damage or debris on the source chip during device pick-up. The tether pitch is set 75 µm for the directional coupler and 100 µm for the adiabatic taper coupons. The tether pitch does not have a significant impact on coupon pick up yield.

Device release
For the SOI devices discussed in this paper, the release layer is the buried oxide (2 μm), which is etched using hydrofluoric (HF) acid. As our silicon device coupons have a SiO2 top cladding, this top cladding needs to be protected during the device release. Amorphous silicon (a-Si) can act as a good protection layer for this purpose. Depositing thick (~1 μm) amorphous silicon using plasma enhanced chemical vapor deposition (PECVD) at 180 o C can effectively encapsulate the device. Moreover, using dry etching (SF6:CF4:H2) one can uniformly remove the a-Si after release without damaging the device, nor the tethers. We used no full etch in the coupon area, therefore at the bottom side, the device coupons are protected by the silicon device layer, which is uniformly present over the entire coupon area. After the release process is completed, silicon devices become thin suspended membranes attached to the surrounding silicon by the tether structures. This implies that stress inside the released device can cause bending of the coupons causing devices to collapse onto the substrate or the thin silicon device layer to break, causing penetration of HF into the top device layer. Therefore proper stress management is required. The stress in the top oxide cladding was measured to be 153 MPa compressive, while the stress in the a-Si encapsulation was measured to be 20 MPa compressive. In order to compensate for this compressive stress a tensile strain PECVD SiNx is used. The used SiNx has a tensile stress of 170 MPa. Thinning down the top silicon oxide layer to 100 nm, depositing 170 nm tensile strain SiNx and using a 1 μm thick encapsulation layer allows for a proper release of the device.
The complete process flow for releasing silicon passive devices is schematically displayed in Fig. 7. Devices were fabricated on a standard silicon-on-insulator (SOI) substrate with 1.1 μm top oxide cladding (Fig. 7a)). We start with thinning the top oxide to 100 nm using buffered hydrofluoric acid (BHF) (Fig. 7b)). 170 nm thick SiNx (slightly thicker than needed in order to offer tolerance to over-etching in the following wet and dry etching steps) is deposited (Fig.  7c)). Rectangular coupons are defined by dry etching (SF6:CF4:H2) the dielectric back-end and slightly etching into the 220 nm silicon device layer, (Fig. 7d)). Then 1 μm of a-Si protection layer is deposited at 180 o C (Fig. 7e)), which is then patterned. Tethers are defined using dry etching, thereby also exposing the buried oxide (Fig. 7f)). By dipping structures in 40% HF for about 13 minutes, the buried oxide is removed underneath the membrane rendering the passive silicon devices free-hanging, attached to the surrounding silicon by the tethers (Fig.  7g)). Finally, the encapsulating a-Si is removed using dry etching, slightly over etching into the top SiNx layer (Fig. 7h)).

Transfer printing process
The transfer-printing was implemented using an X-Celeprint micro-TP100 lab-scale printer. The process sequence is shown in Fig. 8. By laminating a structured viscoelastic PDMS stamp with the same dimensions as the device coupons (300 × 50 μm for the adiabatic taper coupons and 150 × 50 μm for directional coupler coupons) to the suspended silicon coupon and quickly moving it in the vertical direction, one is able to break the silicon tethers in the narrowest points and hence pick up the released coupon (Fig. 8a)). Printing is performed by laminating the picked coupon against a DVS-BCB coated (soft-cured at 180 o C) SOI target substrate (Fig. 8b)). By slowly moving the stamp up in the vertical direction the coupon remains attached to the SOI target wafer (Fig. 8c)). Finally, the DVS-BCB is cured at 280 o C. In the current experiments, one coupon is printed at a time. The cycle time for printing is approximately 30 seconds. The approach is however directly scalable to massively parallel printing of 100s of devices. Alignment is performed using COGNEX™ image recognition software [14] and for this purpose markers were designed on the source coupon and on the target wafer, as shown in Fig. 4 and 5. One can train the software to identify these structures and align their geometric centers, eventually with an additional offset (a so-called off-center auto alignment method). By picking the coupon and bringing it in close proximity to the target wafer, the software can recognize both sets of markers and automatically align the coupon with respect to the target with high precision. Previously we demonstrated that alignment accuracy better than +/-1 μm can be obtained [10].

Experiments
In Fig. 9 we demonstrate transfer printing of two silicon coupons with passive optical coupling structures: the adiabatic taper structure for 1310 nm operation (Fig. 9a)) and the directional coupler structure that operates at 1600 nm (Fig. 9b)). One can identify the tethers that broke during the pick process. Clean prints with no contamination on the target substrate are obtained.
Transmission measurements were carried out by using a pair of single mode optical fibers connected to the grating couplers on the target waveguide circuit. Using a HP8153A power meter and a Santec TSL-510 O-band tunable laser and a Santec TSL-510 C-Band tunable laser  the transmission of both types of coupons could be measured. Reference structures on the target waveguide circuit were used to calibrate out the grating coupler losses. The extracted coupling efficiency for a single adiabatic taper interface is extracted in Fig. 10a). Coupling losses below 3 dB are obtained in the complete 1300 nm wavelength range with -1.5 +/-0.5 dB coupling loss at 1310 nm. The coupling loss for the directional coupler structure is depicted in Fig. 10b). Here one can see that we obtained a peak transmission at 1600 nm with a coupling loss of 0.5 +/-0.5 dB per coupler. The measured coupling efficiency spectrum is in line with the simulation in Fig. 3b). Using focused ion beam (FIB) we evaluated the cross-section of the directional coupler interface and it is displayed in Fig. 11. From this figure we measure a DVS-BCB thickness of 140 nm as well as a lateral misalignment of 700 nm.

Conclusions
For the first time, we demonstrate the transfer printing of passive silicon photonic devices on a silicon photonic target waveguide substrate. We designed compact alignment tolerant coupling schemesan adiabatic taper and directional coupler structure -that both can efficiently operate at ±1 μm misalignment in the 1310 nm and 1600 nm wavelength range respectively. A coupon release scheme was developed by under etching the buried oxide layer, while protecting the top device layers using amorphous silicon. Using an optimized tether design clean device picking and printing is demonstrated. The coupling loss of a single interface was -1.5 +/-0.5 dB for the adiabatic taper coupler at 1310 nm and -0.5 +/-0.5 dB for the directional coupler at 1600 nm. This demonstrates the high potential of the transfer printing technology for SOI photonic integrated circuit development and its potential to improve the turnaround time for fabricating such circuits.

Funding
This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No 645314 (H2020 TOPHIT project).