40 Gb/s all-optical unicast and multicast wavelength converter array on an InP monolithically integrated chip fabricated by MPW technology

We present an InP monolithically integrated all-optical wavelength converter array chip and experimentally validate its performance for unicast (single output wavelength) and multicast (multiple output wavelengths) wavelength conversion. The monolithically integrated chip includes four semiconductor optical amplifiers with an arrayed-waveguide grating and two delayed interferometers. The chip is fabricated on a multi-project wafer (MPW) platform, which allows multiple designers to share space on the same wafer exploiting a generic integration platform. We demonstrate error-free non-return-to-zero (NRZ) unicast wavelength conversions using 2-1 pseudorandom bit sequence data at 10 Gb/s, 20 Gb/s and 40 Gb/s with a 25-nm conversion range. Power penalties as low as 2.3 dB and 2.7 dB for NRZ and return-to-zero (RZ) unicast wavelength conversion at 40 Gb/s are obtained, respectively. Additionally, power penalties of 2.5 dB for NRZ and 3.2 dB for RZ signals at 40 Gb/s 1 × 2 multicast wavelength conversions are also achieved. © 2017 Optical Society of America OCIS codes: (250.5300) Photonic integrated circuits; (130.7405) Wavelength conversion devices; (250.5980) Semiconductor optical amplifiers.


Introduction
The rapid increase in data traffic volumes in telecom and datacom networks attracts interest in optical switching solutions which can potentially support much higher speeds, capacities and dynamicity [1]. All-optical wavelength conversion (AOWC) is a critical building block for optical switching solutions. Using wavelength conversion we can increase bandwidth utilization and avoid channel contention under dynamic traffic patterns for future wavelength division multiplexing (WDM) networks [2,3]. Semiconductor optical amplifiers (SOAs) are particularly suitable for AOWC in terms of their photonic integration potential, small footprint and low power consumption. The study of SOA-based AOWC using discrete components has matured for systems operating at 10-40 Gb/s [4] and several demonstrations at higher bit rates operation (up to 320 Gb/s [5][6][7]) have taken place. Schemes for integrated wavelength converters have begun to attract increasing interest as they benefit from the small footprint photonic integrated circuits (PICs) offer as well as the eliminated component-tocomponent coupling losses [8,9].
Various techniques for monolithically integrated wavelength converter based on SOAs have been demonstrated in recent years. Among all the techniques exploiting SOA dynamics, the cross-gain modulation (XGM) effect is relatively the simplest. However, SOA-based wavelength conversion presents several drawbacks due to the slow carrier recovery time of the SOA which limits the operation speed, the resulting inverse polarity of the converted signal, and the poor extinction ratio (ER) [10]. To overcome these issues, different integrated schemes have been proposed by exploiting fully integrated SOA delayed-interferometer (DI) configuration [11], monolithically integrated SOA assisted by a blue-shifted filter [12], and double-stage SOAs [13]. Most schemes were used to demonstrate operation for return-to-zero (RZ) or non-return-to-zero (NRZ) signals only. In [13], both unicast and multicast wavelength conversions were performed for only NRZ signal, and no operations at bit rates exceeding 10 Gb/s was demonstrated. Combining the schemes of blue-shifted filter and DI, exploiting the XGM effect as well as cross-phase modulation (XPM) effect in a single SOA, we have proposed a novel indium phosphide (InP)-based wavelength converter array. Our suggested PIC can be used for both unicast and multicast wavelength conversions of RZ and NRZ modulation format at speeds up to 40 Gb/s. Preliminary results for multicast wavelength conversion at 40 Gb/s using this chip has previously been reported in [14].
The monolithically integrated wavelength converter array, consisting of four SOAs, an arrayed-waveguide grating (AWG) and two DIs, has been fabricated via a multi-project wafer (MPW) run on a generic platform by integrating standard building blocks, including passive waveguide devices, SOAs and electro-optical phase modulators (EOPMs).
In this paper, we present a comprehensive description of the PIC design followed by systematic experimental assessment of the performances of the integrated wavelength converter array for NRZ on-off-keying (OOK) data at 10 Gb/s, 20 Gb/s and 40 Gb/s, and RZ OOK data at 40 Gb/s. The behavior of the device in terms of the supported wavelength range of the input signal, the conversion efficiency and the power penalty variations under different conditions is analyzed. Also the performance difference between unicast wavelength conversion (UWC) and 1 × 2 multicast wavelength conversion (MWC) is compared.

Device design and operation
As shown in Fig. 1(a), the integrated wavelength converter array consists of four wavelength converters. Each wavelength converter design exploits both XGM and XPM effects in a single nonlinear long SOA combined with a shared AWG, which acts as a blue-shifted bandpass filter (BPF). Firstly, the modulated input pump signal at wavelength λ s and a continuouswave (CW) probe light at wavelength λ c are coupled and sent to one of the input ports of the PIC. Then, the pump signal modulates the gain of the SOA to produce an inverted copy of the data signal at λ c based on XGM effect. At the same time, a phase shift is induced on the inverted signal by means of XPM effect, which results in a chirped converted signal. The AWG has two functions in the PIC. Firstly it filters the residual pump signal, acting as a periodic BPF. Secondly it routes the converted signal to a different output with respect to the input CW wavelength. One of the AWG center wavelengths is designed to be aligned with blue-shifted sideband of the CW light. In this way the gain saturation is compensated by extracting the ultrafast chirp components, avoiding patterning effects [15]. Two of the AWG output ports are connected to the two DI configurations for further operation. Each of the DIs consists of one 1 × 2 multi-mode interference (MMI) splitter, one EOPM in each branch, and one 2 × 2 MMI coupler. For NRZ wavelength conversion, the DI is used to further filter the residual pump signal. Thus, the converted signal out of the chip is still inverted. While for RZ wavelength conversion, the DI is used to flip over the signal polarity by translating the phase change of the inverted converted signal into amplitude change. By tuning the notch wavelength of the DI to λ c , the logical "1" level in the inverted signal has a high attenuation and the logical "0" level has a large transmittance. As a consequence, an RZ converted signal with an optimized ER and non-inverted polarity is achieved [11]. The circuit is designed for realizing a 4 × 4 all-optical wavelength router as well, in which case we need four SOAs simultaneously. However, in this paper we focus on its wavelength conversion function. The layout of the PIC is shown in Fig. 1(b), which is designed by utilizing PhoeniX Software. Fabrication is done by SMART Photonics, the Netherlands, in an MPW run, which allows the multiple designers to share space on the same wafer. The fabricated wafer with 2-inch footprint is shown in Fig. 2(a). The platform is InP-based and all design cells are measured to be 4.6 × 4 mm 2 . The active layer of the SOAs consists of four quantum wells with an emitting wavelength of 1.55 μm. Figure 2(b) shows the photograph of our design cell, consisting of several different structures and testing parts. In this paper, only the wavelength converter array shown in Fig. 2(c) will be discussed. This chip has a footprint of 4.6 × 1.85 mm 2 , in which each output of four 2-μm-wide, 2-mm-long SOAs is connected to one input of a 4 × 4 AWG, respectively. The designed AWG has 625-GHz channel spacing, 2500-GHz free-spectral range (FSR), and a center wavelength of 1550 nm with overall size around 400 × 300 μm 2 . Two outputs of the AWG are connected to two 1 × 2 DIs with 3.5-ps delay (DI1) and 2.5-ps delay (DI2), respectively, while the other two outputs are directly connected to the chip output ports. Some 2-μm-width shallow-etched waveguides with 3.5 dB/cm loss and 1.5μm-width deep-etched waveguides with 5 dB/cm loss are utilized for the connections. Antireflection (AR) coatings and 7-degree angled input ports are used to reduce the facet reflections. Besides, offsets between curved waveguides and transitions between deep and shallow waveguides are used to reduce the propagation loss and feedback. All the components are from the standard building blocks of the foundry.

Experimental characterization
As shown in Fig. 3, the chip is soldered to a copper mount and wire bounded to a printed circuit board to replace the use of probe needles. Besides, two tapered fibers with a focused spot size of 0.8 μm are used for coupling light in and out of the chip by utilizing two 6-axis flexure platforms. The operation temperature is maintained at 19 °C by using a thermoelectric cooler for fast cooling combined with a water cooler for slow cooling during testing. In order to perform a systematic analysis of the chip performance, experiments of unicast and multicast wavelength conversion for both NRZ and RZ signals are carried out. All components employed in the experimental setups, except the integrated wavelength converter array chip, are commercially available. The 3-dB gain bandwidth and the contact resistance of the 2-mm long SOA are measured using a test device of SOA. They are around 31 nm and 2.7 Ω, respectively.

Performance assessment of the NRZ wavelength conversion
The experimental setup is depicted in Fig. 4, and is used for both unicast wavelength conversion and 1 × 2 multicast wavelength conversion experiments. The input NRZ on-offkeying (OOK) data signal is generated by externally modulating a tunable CW laser source (λ s in nm) with a 2 31 -1 pseudorandom bit sequence (PRBS) data stream at 10 Gb/s, 20 Gb/s and 40 Gb/s, respectively. The signal is then amplified with an erbium-doped fiber amplifier (EDFA) and filtered by a 2.92 nm BPF to remove the amplified spontaneous emission (ASE). A polarization controller (PC) is employed on each arm to set proper polarizations of the signal and CW lights before coupling them into one chip input port via 3 dB couplers. After on-chip wavelength conversion, the converted signal collected from output port is further investigated using either an optical spectrum analyzer (OSA), a digital sampling oscilloscope with a 100 GHz optical head, or bit error rate (BER) system consisting of a variable optical attenuator (VOA), a 40 GHz receiver and a 40 Gb/s error detector (BERT). Back to back BER measurements are also made by connecting the input signal directly to the BERT.  . AWG performance measured at output port #6 by biasing SOA2, while SOA2 ASE is measured at input port #2 (measured on 0.06-nm resolution bandwidth). For UWC, only one CW probe is switched on and then coupled with the modulated pump signal into the chip input port #2. In this experiment, wavelength conversion from input port #2 to output port #6 is tested. Figure 5 depicts the band-pass characteristics of one channel of the AWG when SOA2 is forward biased to generate amplified spontaneous emission (ASE). According to the measured central wavelength of the AWG channel, we have chosen the wavelength of the CW light to be 1542.2 nm, which is red-shifted by 0.7 nm with respect to one of the AWG center wavelengths. The wavelengths of the pump signal are selected from 1531.1 nm to 1537.1 nm and from 1547.1 nm to 1556.1 nm for up-conversion and downconversion, respectively, giving in total a 25 nm conversion range which is larger than an FSR of the AWG (20 nm). The parameter values used for UWCs are given in Table 1. The input power of the pump signal (P s in dBm) and the input power of CW probe light (P c in dBm) are measured after the 3 dB coupler, while I 2 is the forward biased current applied to SOA2 in mA.      Fig. 9(c). The conversion efficiency at 40 Gb/s at pump wavelength of 1550.1 nm is lower than at other pump wavelengths. As from the eye diagram for this case, the "0" level of the converted signal is very close to the "ground" level, thus the ER is higher compared to the other cases as shown in Fig. 9(b). However, the eye is not opener, which means the voltage of the "1" level is also small, leading to a low output power and thus a low conversion efficiency. Besides, the low conversion efficiencies in Fig. 9(c) are also caused by coupling losses and the propagating loss of InP chip. By a conservative assumption of 4 dB coupling loss per facet (total 8 dB coupling loss of the chip), the on-chip conversion efficiencies range from 0.4 dB to 3.7 dB at 40 Gb/s, 1.9 dB to 4 dB at 20 Gb/s, and 1.75 dB to 3.1 dB at 10 Gb/s.
The power penalties at 40 Gb/s ranging from 2.7 dB to 4.7 dB could be attributed to any of the following factors. Firstly, compared with the results of 10 Gb/s and 20 Gb/s UWCs, the eye diagrams at 40 Gb/s are less open than those at 10 Gb/s and 20 Gb/s, which results in higher power penalties. This is caused by the limited gain recovery speed of the SOA. Although using the blue-shifted filtering of the AWG has compensated some of the gain recovery, the ~2 nm bandwidth of AWG is not narrow enough to have a proper shape with respect to the blue-shifted BPF with 1.4 nm bandwidth in [6], resulting in partial gain recovery. In future PIC designs, optimized AWGs are planned to further improve gain recovery and lower penalties. Secondly, as depicted in Fig. 9(a), up-conversions have higher power penalties than down-conversions. This is due to the asymmetry of gain and carrier density of the SOA, leading to lower ERs for up-conversions, as shown in Fig. 9(b). Thirdly, the pattern dependence of longer pattern length (2 31 -1) also causes a larger power penalty compared with pattern length of 2 7 -1. Finally, the output ports of the chip are not angled due to a design mistake, resulting in higher facet reflections with respect to the angled ones. Other reflections might occur between the input and output tapered fibers during coupling. Due to these reflection, an increase in SOA current which should have shortened carrier lifetime, was not possible as it led to lasing. These reflection issues are planned to be solved by redesigning the output ports to have a 7-degree angle and fully packaging the chip with pigtailed fibers.
For MWC, two CW probes (shown in Fig. 4) and the 40 Gb/s pump signal are used. Wavelength conversion using the SOA connected to input port #3 is performed with the converted signals coming out of ports #5 and #6. According to the frequency response of the AWG measured at output ports #5 and #6, the wavelengths of the two CW probes and the pump signal are set to λ c1 = 1537.1 nm, λ c2 = 1542.2 nm and λ s = 1550.2 nm, respectively. λ c1 is red-shifted by 1 nm while λ c2 is red-shifted by 0.8 nm. The DI2 here is used as another periodic filter centered at λ c2 . In order to compare the differences between UWC and MWC, three steps are followed in the experiment.
Step 1: only probe light at λ c1 (CW1) is switched on. In order to achieve the best performance (low power penalty), input powers (pump: P s ; probe: P c1 ) and polarizations state of both pump and CW1 signals, as well as the current of SOA3 (I 3 in mA) are tuned.
Step 2: only probe light at λ c2 (CW2) is switched on. Then, only the input power (P c2 ) and the polarization of CW2, as well as I 3 are tuned for optimal results.
Step 3: both CW1 and CW2 are switched on, without changing the other parameters, only I 3 is tuned to achieve the smallest power penalty. The values used for all steps are shown in Table 2. Figure 10 shows the optical spectra before and after on-chip 40 Gb/s NRZ wavelength conversions, as well as the corresponding eye diagrams for all steps. The final BER performances are depicted in Fig. 10(d). Step 1: λ s to λ c1 8.6 3.8 -400 Step 2: λ s to λ c2 8.6 -1.4 410 Step 3: λ s to λ c1 and λ c2 8. As described in Fig. 10(c), the input signal has been simultaneously copied to the two CW probes. Besides, comparing the parameters used for UWCs and MWC, only the injected current of SOA3 is changed, which is less than 20 mA. What's more, as shown in Fig. 10(d), the power penalties are 2.3 dB and 2.9 dB for 40 Gb/s UWC from 1550.2 nm to 1542.2 nm and from 1550.2 nm to 1537.1 nm, respectively. And the power penalties at output port #5 and #6 for MWC are 2.5 dB and 3 dB, respectively. It means that the 1 × 2 NRZ MWC at 40 Gb/s introduces less than 0.5 dB extra power penalty with respect to NRZ UWC .

RZ wavelength conversion
In order to validate the chip performance for RZ wavelength conversion, experiments for both 40 Gb/s UWCs and MWC are carried out. The experimental setup is depicted in Fig. 11. The 40 Gb/s RZ signal is generated by modulating a tunable mode-locked laser (TMLL), which is emitting a 2.5 ps width pulse train at central wavelength of λ s = 1550.1 nm with a 2 31 -1 PRBS data stream at 39.812 GHz. The modulated pump signal is then amplified by an EDFA and filtered by a 4.9 nm BPF. The DI2 is adjusted to maximize the filtering out of the DC component of the converted signal at the output port #5 to insure that the obtained output signal is no longer inverted. The strong suppression of the DC component leads to low output power. In order to retain sufficient optical power for BER measurements an additional EDFA and a 5.1 nm BPF are employed before the BERT configuration. Back to back BER performances are also measured by connecting the input modulated signal directly to the BERT configuration. Table 3 shows the experimental parameter values used for both the 40 Gb/s RZ UWCs and MWC.  RZ UWC was tested using the SOA connected to input port #3 and testing output port #6. The center wavelengths of the pump signal and the CW probe are set to λ s = 1550.1 nm and λ c1 = 1537.1 nm (CW1), respectively. The average optical input powers of the pump signal (P s ) and the CW1 (P c1 ), as well as the biased current of SOA3 (I 3 in mA) are reported in Table  3. The optical spectra, the eye diagrams and the BER performances for both the back-to-back signal and the converted signal are shown in Figs. 12(a)-12(c). The converted signal is still inverted with a power penalty of 8.2 dB.
RZ UWC was also tested to output ports #4 and #5 with the center wavelengths of the pump signal and the CW probe set to λ s = 1550.1 nm and λ c2 = 1542.2 nm (CW2), respectively. The used experimental parameter values are shown in Table 3. A biased voltage (V DI2 in V) is applied to DI2 to set the central wavelength of the notch filter to 1542.2 nm. The average power of the non-inverted converted signal at port #5 is around −16 dBm, which means a conversion efficiency of around −25 dB, including an averaged coupling loss of around −8 dB. The extra losses are from on-chip components, which could be mainly attributed to the strong suppression of the DC component by DI2. The experimental results are shown in Figs. 12(d)-12(f), in which the performances from the monitoring port #4 are also measured. Comparing the eye diagrams obtained from ports #4 and #5, it is clear that the DI2 successfully flips the signal resulting in a non-inverted converted signal. The power penalty is greatly improved from the 8.1 dB at output port #4 to be the 2.7 dB at output port #5. For the 40 Gb/s 1 × 2 RZ MWC, wavelength conversion from input port #3 to output ports #5 and #6 is tested (in addition the inverted signal at port #4 is measured). The center wavelengths of the pump signal and the two CW probes are set to λ s = 1550.1 nm, λ c1 = 1537.1 nm and λ c2 = 1542.2 nm, respectively, while the other parameter values are shown in Table 3. According to the optical spectra described in Fig. 12(g), the input signal has been simultaneously copied to the two input probe lights. As shown in Figs. 12(h)-12(i), the power penalty of the converted signal (non-inverted polarity) is 3.2 dB at output port #5, while the converted signal from output port #6 has inverted polarity and a power penalty of 8.5 dB. Compared with the converted signal from output port #4 with an 8.3 dB power penalty, it is clear that the DI2 works efficiently to RZ pattern to optimize the ER and to obtain a noninverted signal. The incurred extra power penalty is less than 0.5 dB from 40 Gb/s RZ UWC to 1 × 2 40 Gb/s RZ MWC. Compared with the power penalties of 8 dB and 10 dB for inverted and non-inverted 2 × 40 Gb/s RZ AOWC in [12], respectively, the presented wavelength converter in this paper has a relatively improved performance. One reason is the longer active length and larger biased current of SOA can speed up the slow gain recovery. The other reason is the full integration of SOA, AWG and DI can eliminate off-chip coupling losses.

Conclusions
A systematic performance assessment of an InP-based integrated wavelength converter array chip for both NRZ-OOK and RZ-OOK signals is presented in this paper. The chip contains several active and passive components, and is fabricated on a MPW platform. Error-free 10 Gb/s, 20 Gb/s and 40 Gb/s NRZ all-optical UWCs with a 25 nm conversion range are demonstrated. The performances of 1 × 2 40 Gb/s MWCs for both NRZ-OOK and RZ-OOK signals are analyzed and discussed. Good BER performances are obtained. The power penalties range from 2.3 dB to 4.7 dB, 1.9 dB to 2.9 dB and 1.7 dB to 3 dB for 40 Gb/s, 20 Gb/s and 10 Gb/s NRZ UWC, respectively, with on-chip conversion efficiencies higher than 0 dB. Power penalty as low as 2.7 dB for 40 Gb/s RZ UWC is also achieved for the first time. Additionally, less than 0.5 dB extra power penalty is required to move from UWC to 1 × 2 MWC at 40 Gb/s. The power penalties are as low as 2.5 dB for NRZ signal and 3.2 dB for RZ signal at 40 Gb/s MWCs. Improved power penalty is expected with future designs by exploiting all angled ports and optimized AWG. Besides, it is better to make all input ports and output ports at different side of the chip, which is easy for future 1 × 4 MWCs testing.