Subwavelength index engineered surface grating coupler with sub-decibel efficiency for 220-nm silicon-on-insulator waveguides

Surface grating couplers are fundamental components in chip-based photonic devices to couple light between photonic integrated circuits and optical fibers. In this work, we report on a grating coupler with sub-decibel experimental coupling efficiency using a single etch process in a standard 220-nm silicon-on-insulator (SOI) platform. We specifically demonstrate a subwavelength metamaterial refractive index engineered nanostructure with backside metal reflector, with the measured peak fiber-chip coupling efficiency of −0.69 dB (85.3%) and 3 dB bandwidth of 60 nm. This is the highest coupling efficiency hitherto experimentally achieved for a surface grating coupler implemented in 220-nm SOI platform. © 2015 Optical Society of America OCIS codes: (130.0130) Integrated optics; (050.1950) Diffraction gratings; (250.5300) Photonic integrated circuits; (050.6624) Subwavelength structures. References and links 1. A. Rickman, “The commercialization of silicon photonics,” Nat. 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Introduction
Silicon photonics is poised to enable new types of nanophotonic applications, including optical interconnects for data communications and ultra-fast optical communications systems [1][2][3][4]. Practical deployment of nanophotonic technologies is greatly facilitated by the availability of a common silicon-on-insulator (SOI) platform used in publicly accessible foundries [5,6]. Efficient optical coupling interfaces are one of the critical functional elements in SOI photonic circuits [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. Coupling of light to and from photonic circuits has been recognized as a major practical challenge since the early years of integrated optics. The coupling is particularly difficult for SOI waveguides, since the cross-sectional area of silicon wire waveguides is more than two orders of magnitude smaller than that of a standard single-mode fiber. The mode mismatch problem can be efficiently circumvented by using vertical surface grating couplers. This coupling solution also allows a flexible placing of the optical interface at specific locations on the chip surface and automated wafer scale testing [10-26].
The efficiency of surface grating couplers is determined by two main factors, namely the field matching and grating diffraction efficiency. The field mismatch between the beam diffracted by the grating and the near-Gaussian mode of an optical fiber can be mitigated by grating apodization [8]. This is typically achieved by varying the grating geometry however often requiring small minimum feature sizes at or beyond the limit of deep-ultraviolet (DUV) lithography [7]. Grating diffraction efficiency is strongly affected by the thickness of Si and the buried oxide (BOX) layers in SOI substrate. SOI with 220 nm Si is typically used in silicon photonics foundries [6,9]. However, this Si thickness is not optimal for the maximum diffraction efficiency [9-11, 21]. Furthermore, BOX layer thickness needs to be modified to achieve constructive interference towards the optical fiber. In order to improve the grating directionality and the overall coupling efficiency, two main solutions have been explored. One solution is to optimize intrinsic grating directionality [10][11][12][13][14][15][16]. This can be achieved by breaking the vertical symmetry to increase the fraction of optical power diffracted towards the superstrate, while reducing the radiation into the silicon substrate. High directionalities have been reported, typically based on adjusting the etch depth [11-13], depositing high-index overlays [14], or using the blazing effect [15,16]. However, none of these approaches have yet been implemented with a sub-decibel (sub-dB) coupling efficiency experimentally. As an alternative approach, the coupling efficiency is increased by making use of the light diffracted down (towards the substrate), that is by reflecting it and combining in-phase (modulo 2π) with the beam diffracted upwards. This was achieved by forming mirrors underneath the grating, using backside substrate engineering [17-23]. The latter can employ metal deposition [17,18] or flip-chip wafer-to-wafer bonding [19][20][21][22][23]. At the present time, the use of a backside mirror is the only solution yet successfully implemented for achieving a sub-decibel fiber-chip coupling efficiency experimentally. High coupling efficiencies have been reported [17, 21, 23], but to achieve optimal coupling performance, SOI wafers with Si thickness greater than 220 nm were required. In addition, two-step etch process [17, 21], double-SOI [21], or BOX thinning [23], critical for maximizing coupling efficiency, were required. Here we report for the first time sub-decibel experimental coupling efficiency for a standard 220-nm SOI substrate and single etch fabrication process.

Grating coupler design
Our grating coupler design utilizes the effective homogeneous metamaterial in grating trenches, exploiting the principle of subwavelength grating (SWG) refractive index engineering [8,27]. According to effective medium theory [27], the effective homogeneous medium is characterized by an intermediate refractive index between that of the alternating material segments, here silicon and air. Compared to SOI couplers with shallow etch grating region, the present approach has two important practical benefits: i) both grating coupler and interconnecting waveguide are defined in a single-etch step down to the depth of the BOX layer and ii) the SWG structure allows to control the coupling strength and apodize the grating profile. The subwavelength grating is implemented as a periodic structure oriented perpendicular to the light propagation direction and with periodicity below the Bragg limit, therefore frustrating diffraction effects [8,27]. This unique approach of subwavelength material index engineering was first proposed in the context of surface grating couplers in [24][25][26] Here the performance of the surface grating coupler is optimized using a comprehensive multi-parameter design strategy. The couplers are implemented in a standard SOI wafer, comprising 220-nm-thick Si layer with refractive index n Si = 3.476 and 3-μm-thick BOX with refractive index n SiO 2 = 1.444. The superstrate medium is air. The coupler is designed to operate in the transverse electric (TE) polarization at a spectral region near 1550 nm. The overall design strategy is based on de-coupled two-dimensional  We first designed a reference uniform (non-apodized) grating coupler structure without the bottom mirror. We calculated that the coupler radiates with a coupling angle of 10 • for the following grating parameters: diffraction period diffraction period Λ z = 718 nm, duty cycle DC z = 55%, and number of periods NP = 25. An effective medium index n SW G = 2.40 is used in grating trenches to optimize the coupling strength, yielding a field overlap with optical fiber mode of 74%. The effective medium index has been obtained by treating the SWG structure as a 2-D multilayer slab waveguide in the x − z plane [24], and calculating the effective index of its fundamental TE-polarized mode [19,24]. The geometrical layout dimensions, yielding the effective medium index of 2.40 are: air gap width G = 171 nm and a subwavelength grating pitch Λ SW G = 450 nm. In this grating structure, only 39% of injected power is diffracted to the air, while 51% of power is diffracted to silicon substrate. This results in an overall coupling efficiency of only −5.3 dB (29.5%). Here, the coupling efficiency is substantially reduced by the out-of-phase interference of the beam reflected at the BOX-substrate interface with the upward radiated beam. The interference effect is governed by the BOX thickness. While the latter can in principle be adjusted to enhance grating directionality (see Fig. 2(a)) [7][8][9], in practice, BOX thickness is not a free parameter and varying it is not an option for SOI substrates frequently used in silicon photonic foundries [6].
To circumvent this limitation, in the second step of our design we optimize the diffraction efficiency of a uniform grating coupler by controlling the interference effect through the coupling angle adjustment [19]. As it is observed in Fig. 2(a), improved radiation performance of the grating coupler is achieved periodically for several possible BOX thicknesses. Our grating coupler implemented in a SOI wafer with a 3-μm-thick BOX provides an optimal coupling performance (power diffracted up 69%). Specifically, the coupler is redesigned to fulfill the constructive interference condition between the beam reflected at the BOX-substrate interface and the upward diffracted beam. The redesigned grating parameters are: Λ z = 810 nm, DC z = 55%, and n SW G = 2.40. The power radiated upwards is substantially increased to 69% for a coupling angle of 27 • , while the substrate radiated power is reduced to 27%. The calculated diffraction efficiencies in up/down directions are shown in Fig. 2(b). The coupling efficiency is more than doubled compared to the reference grating coupler. This yields a substantially improved fiber-chip coupling efficiency of −2.6 dB (55%), as shown in Fig. 3(b), with no need for a SOI wafer with customized BOX thickness. In the third step of our design, the fiber-chip grating coupler is apodized by using SWG refractive index engineering [8,19,24,25]. This is achieved by varying the effective medium index in the grating trenches along the mode propagation direction to obtain a near-field profile matching to the mode of a standard single-mode optical fiber, i.e. a near-Gaussian profile with a mode field diameter of 10.4 μm at the wavelength of 1550 nm. By controlling the SWG duty cycle G i /Λ SW G (where G i is the hole size and Λ SW G is the grating pitch), a wide range of effective medium indexes can be obtained while still keeping a minimum feature size of > 100 nm, for compatibility with DUV lithography [7,8,19]. In order to determine the optimal apodization geometry, we studied the coupling efficiency for different numbers of apodized periods and metamaterial index ranges, as shown in Fig. 3(a). In our optimized design, the apodized grating coupler comprises 10 apodized periods, followed by 15 periods with a uniform coupling strength. The effective medium index in the grating trenches is varied from 2.80 to 2.20 along the first 10 grating diffraction periods, effectively apodizing the grating without compromising its directionality. This range of effective medium refractive indexes is synthesized for an SWG pitch of 450 nm with a linear increase in hole sizes from 104 nm to 194 nm. The diffraction period (Λ z,i ) is chirped from 751 nm to 847 nm, to maintain the linear phase of the diffracted field and therefore a constant radiation angle (27 • ) along the grating. According to our F-EEM and FDTD calculations, this apodization procedure increases the mode field overlap to 93%, yielding a fiber-chip coupling efficiency of −1.92 dB (64.3%), as shown in Fig. 3(b).
Finally, a thin metal (aluminum) mirror is added underneath the BOX below the apodized coupling structure to mitigate the substrate radiation losses and further increase the coupling efficiency. With the bottom mirror, the power fraction radiated upwards is increased to 94%. As shown in Fig. 3(b), an overall fiber-chip coupling efficiency of −0.67 dB (85.7%) is predicted by FDTD calculations at a central wavelength of 1550 nm, with back-reflections of ∼6%.

Fabrication and characterization of grating couplers
Surface grating couplers and interconnecting waveguides were fabricated on a SOI substrate with silicon slab thickness of 220 nm on top of 3-μm-thick BOX layer. A single etch step process was used. The resist was patterned by electron beam lithography, followed by transferring the grating coupler layouts onto the silicon layer by inductively coupled plasma reactive ion etching (ICP-RIE), with the BOX acting as an etch-stop layer.
The metal mirror deposition was performed as follows: First, the SOI wafer was cleaved into smaller dies, approximately 1×2 cm 2 in size. The individual pieces were glued on glass carriers using wax. The pieces were thinned down to the thickness of 80 μm with an optical surface finish using a lapping tool with aluminum oxide slurry. The SOI samples and their carriers were spin coated with photoresist. A photomask was designed for backside patterning to make membrane cavities at the location of the grating couplers. Contact lithography was utilized via IR backside alignment (Suss MJB3) to align the photomask to the grating couplers. Dry etching was employed to make deep holes in the SOI substrate backside using ICP etching with sulfur hexafluoride (SF6) gas. With this process an etch rate over 10 μm/min and very high selectivity relative to the BOX layer was achieved. Finally, the samples were coated with a single 10nm-thin Al layer by electron beam evaporation, followed by releasing the samples from glass carriers to allow optical testing. The scanning electron and optical microscopy (SEM) images of fabricated surface grating coupler with a bottom mirror are shown in Fig. 4.
Grating couplers were characterized in a back-to-back configuration. The light from the input optical fiber is coupled to the chip by the input grating coupler, injecting the light into a silicon wire interconnecting waveguide, after which it is coupled out of the chip to the output optical fibre using an identical grating coupler structure. Polarization-maintaining angle polished optical fibers were positioned above the silicon chip surface to couple light at the radiation angle of 27 • . In this arrangement, the fiber facets are oriented parallel to the chip surface, refracting light at the fiber-air interface at the required coupling angle [33,34]. The fibre-chip coupling loss was determined from the measured insertion loss of two back-to-back connected couplers, subtracting the loss of the silicon wire interconnecting waveguide. The measured coupling efficiency for the subwavelength-engineered surface grating coupler with a metal mirror is shown in Fig. 4(a). The peak fiber-chip coupling efficiency of −0.69 dB (85.3%) is determined at a wavelength of 1535 nm, with a 3-dB bandwidth of ∼60 nm. The peak value is used here for consistency with the previously reported sub-decibel couplers in thicker (250 nm) SOI substrates [17,23]. To the best of our knowledge, this is the highest coupling efficiency experimentally achieved for a surface grating coupler implemented in a 220 nm SOI platform, which is typically utilized in publicly accessible silicon photonic foundries [6,9]. Our experimental results demonstrate excellent agreement with the nominal FDTD calculations. In the measured coupling spectrum, there is a minor blue shift (∼15 nm) in the central wavelength, which can be explained by a small fabrication bias of ∼7 nm, resulting in slightly increased hole sizes. The measured spectral response of the grating coupler shows a small (0.3 dB) ripple (see inset of Fig. 4(a)). The ripple can be attributed to two main sources. The first is Fresnel reflection loss at the (cylindrical) surface of the fiber (∼0.15 dB). This is due to the fact that the grating coupler has been characterized with the air as the superstrate medium. In order to prevent Fresnel reflection loss, index matching medium can be used, as in Refs. [11,17].
The second source of the ripple is the back-reflection from the grating couplers due to the residual index mismatch at the transitions between the silicon slab access waveguide and the grating region. The influence of the back-reflections can be effectively mitigated by established techniques such as curving and offsetting the grating lines [35]. The overall magnitude of the ripple is ∼0.3 dB, which yields an average coupling efficiency of −0.85 dB (82.2%) near the peak wavelength of 1535 nm.

Conclusion
We have reported on the design and experimental demonstration of the first surface grating coupler with sub-decibel efficiency in the 220-nm SOI platform. By exploiting the principle of SWG refractive index engineering in planar waveguides, the coupler was fabricated using a single-etch step process and backside metal deposition. The experimental peak fiber-chip coupling efficiency is −0.69 dB (85.3%), with a 3 dB bandwidth of 60 nm. To the best of our knowledge, this is the highest efficiency yet reported for surface grating couplers in 220nm SOI waveguides and single-etch fabrication process. This demonstration opens promising prospects for deployment of highly efficient optical coupling interfaces for a standard 220-nm SOI platform.