Junction-less phototransistor with nanowire channels , a modeling study

We propose a new nanowire based, junction-less phototransistor, that consists of a channel with both wide and narrow regions to ensure efficient light absorption and low dark current, respectively. While the light is absorbed in the wide region, the narrow region allows for ease of band engineering. We also find that a nanowire in the source can further boost the optical gain. The proposed device, which can potentially detect very low light intensities, does not rely on complicated doping profiles, but instead uses suitably designed gates. Our calculations show the detection of a photon flux as low as 35 per second. © 2014 Optical Society of America OCIS codes: (040.5160) Photodetectors; (040.3780) Low light level; (040.6070) Solid state detectors; (040.6040) Silicon; (230.5160) Photodetectors; (250.0040) Detectors. References and links 1. D. Shiri, Y. Kong, A. Buin, and M. P. Anantram, “Strain Induced Change of Bandgap and Effective Mass in Silicon Nanowires,” Appl. Phys. Lett. 93(7), 073114 (2008). 2. A. Zhang, S. You, C. Soci, Y. Liu, D. Wang, and Y. H. Lo, “Silicon Nanowire Detectors Showing Phototransistive Gain,” Appl. Phys. Lett. 93(12), 121110 (2008). 3. R. Agarwal and C. M. Lieber, “Semiconductor Nanowires: Optics and Optoelectronics,” Appl. Phys., A Mater. Sci. Process. 85(3), 209–215 (2006). 4. J. H. Park, S. H. Seo, I. S. Wang, H. J. Yoon, J. K. Shin, P. Choi, Y. C. Jo, and H. Kim, “Active Pixel Sensor Using a 1x16 Nano-Wire Photodetector Array for Complementary Metal Oxide Semiconductor Imagers,” Jpn. J. Appl. Phys. 43(4B), 2050–2053 (2004). 5. H. G. Choi, Y. S. Choi, Y. C. Jo, and H. Kim, “A Low-Power Silicon-on-Insulator Photodetector with a Nanometer-Scale Wire for Highly Integrated Circuit,” Jpn. J. Appl. Phys. 43(6B), 3916–3918 (2004). 6. A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, and J.-P. Colinge, “Junctionless nanowire transistor (JNT): Properties and design guidelines,” in Proceedings of the European Solid-State Device Research Conference (Sevilla, 2010), 357 −360. 7. S. Han, W. Jin, D. Zhang, T. Tang, C. Li, X. Liu, Z. Liu, B. Lei, and C. Zhou, “Photoconduction Studies on GaN Nanowire Transistors under UV and Polarized UV Illumination,” Chem. Phys. Lett. 389(1-3), 176–180 (2004). 8. K. H. Kim, K. Keem, D. Y. Jeong, B. Min, K. Cho, H. Kim, B. M. Moon, T. Noh, J. Park, M. Suh, and S. Kim, “Photocurrent of Undoped, nand p-Type Si Nanowires Synthesized by Thermal Chemical Vapor Deposition,” Jpn. J. Appl. Phys. 45(5A 5R), 4265–4269 (2006). 9. W. Kim and K. S. Chu, “ZnO nanowire field-effect transistor as a UV photodetector; optimization for maximum sensitivity,” Phys. Status Solidi., A Appl. Mater. Sci. 206(1), 179–182 (2009). 10. E. Lee, D. I. Moon, J. H. Yang, K. S. Lim, and Y. K. Choi, “Transparent Zinc Oxide Gate Metal Oxide Semiconductor Field-Effect Transistor for High-Responsivity Photodetector,” IEEE Electron Device Lett. 30(5), 493–495 (2009). 11. A. Zhang, C. Soci, B. Xiang, J. Park, D. Wang, and Y. H. Lo, “High Gain ZnO Nanowire Phototransistor,” in Conference on Lasers and Electro-Optics (Baltimore 2007), 1–2. 12. G. Cheng, X. Wu, B. Liu, B. Li, X. Zhang, and Z. Du, “ZnO nanowire Schottky barrier ultraviolet photodetector with high sensitivity and fast recovery speed,” Appl. Phys. Lett. 99(20), 203105 (2011). 13. Y. H. Ahn and J. Park, “Efficient visible light detection using individual germanium nanowire field effect transistors,” Appl. Phys. Lett. 91(16), 162102 (2007). 14. K.-S. Shin, A. Pan, and C. O. Chui, “Channel length dependent sensitivity of Schottky contacted silicon nanowire field-effect transistor sensors,” Appl. Phys. Lett. 100(12), 123504 (2012). #207210 $15.00 USD Received 25 Feb 2014; revised 4 May 2014; accepted 5 May 2014; published 16 May 2014 (C) 2014 OSA 19 May 2014 | Vol. 22, No. 10 | DOI:10.1364/OE.22.012573 | OPTICS EXPRESS 12573 15. H. Yamamoto, K. Taniguchi, and C. Hamaguchi, “High-Sensitivity SOI MOS Photodetector with SelfAmplification,” Jpn. J. Appl. Phys. 35(Part 1, No. 2B), 1382–1386 (1996). 16. Y. Nakamura, H. Ohzu, M. Miyawaki, N. Tanaka, and T. Ohmi, “Design of Bipolar Imaging Device (BASIS),” IEEE Trans. Electron. Dev. 38(5), 1028–1036 (1991). 17. Atlas, Silvaco., www.silvaco.com 18. R. F. Pierret, Semiconductor Device Fundamentals, (Pearson Education, 1996), Chap. 10, 11. 19. A. Fadavi-Roudsari, S. S. Saini, N. O, and M. P. Anantram, “High-Gain, Multiple-Gate Photodetector with Nanowires in the Channel,” IEEE Electron Device Lett. 32(3), 357–359 (2011). 20. The results are obtained by solving the classic Poisson’s and carrier continuity equations using Atlas simulator [17]. Room temperature dark currents are obtained by running simulations at higher temperatures, and then estimating the current at room temperature. Electron and hole lifetimes are assumed to be 10s 21. M. Otto, M. Kroll, T. Käsebier, R. Salzer, A. Tünnermann, and R. B. Wehrspohn, “Extremely low surface recombination velocities in black silicon passivated by atomic layer deposition,” Appl. Phys. Lett. 100(19), 191603 (2012). 22. O. Demichel, V. Calvo, A. Besson, P. Noé, B. Salem, N. Pauc, F. Oehler, P. Gentile, and N. Magnea, “Surface recombination velocity measurements of efficiently passivated gold-catalyzed silicon nanowires by a new optical method,” Nano Lett. 10(7), 2323–2329 (2010). 23. R. Coustel, Q. Benoît à la Guillaume, V. Calvo, O. Renault, L. Dubois, F. Duclairoir, and N. Pauc, “Measurement of the Surface Recombination Velocity in Organically Functionalized Silicon Nanostructures: The Case of Silicon on Insulator,” J. Phys. Chem. C 115(45), 22265–22270 (2011).


Introduction
Nanowires, with their miniaturized one dimensional size offer a variety of properties that are of interest in different applications, including photodetectors.Quantum mechanical effects, such as indirect to direct bandgap transition, prove useful in increasing the absorption coefficient in nanowires [1].The large surface to volume ratio of nanowires leads to a strong capacitive coupling in metal-oxide-semiconductor geometries; and offers a better control over the charge flow within the nano-scale channel of such structures.One can also take advantage of the surface states in increasing the minority carrier recombination time [2].
The small size of nanowires limits their ability to absorb light efficiently [3].Therefore, individual nanowires are preferred to be incorporated in photodetector geometries with optical gain, such as phototransistors.The transistor can be a conventional junction bipolar or a Metal Oxide Semiconductor (MOS) type [4,5], or even a junction-less geometry [6].
A Junction-less transistor is formed by adding a gate to control a nanowire channel that connects the source to the drain.The gate is able to create a potential barrier within the nanowire channel, by depleting the nanowire out of the majority carriers.The height of the potential barrier controls the amount of charge flow and the device ON-OFF state [6].Such structure offers the advantage of simpler fabrication, as: (i) all the extra steps required for doping the source and the drain regions in a top-down approach are eliminated.(ii) Using Silicon on Insulator (SOI) substrate and electron beam lithography/ etching steps allows easy fabrication and localization of the nanowires as opposed to bottom-up approaches; and (iii) SOI substrates facilitate the creation of the gate terminal by providing the buried oxide as the gate dielectric and the bottom silicon substrate as the gate [7][8][9], although it is possible to pattern and create a third terminal on top of the channel [10].
Junction-less transistor geometries are used for photo-detection applications, as well.Examples are n-and p-type Si nanowire based photodetectors [8], Si, and ZnO nanowire detectors with surface defects that separate the carriers and increase the recombination lifetime [2,11,12], and Ge, ZnO, Si, and GaN nanowire based photodetectors with back gates [7,9,13,14].As a photodetector, the junction-less transistor can be biased in either ON or OFF state.However, the focus of this manuscript is the OFF state, as the dark current and its associated shot noise are both low.This gives the opportunity of detecting low level intensities.The operating principle of such a phototransistor is similar to the lateral bipolar action [15].When the channel is illuminated, most of the photo-generated minority carriers easily travel towards the contacts in response to the high electric field.However, the majority carriers are trapped inside the potential barrier created by the gate (OFF state).To satisfy the charge neutrality the barrier height is reduced.A lower potential barrier creates a pathway for the trapped carriers to diffuse; but more importantly it eases the overall carrier flow and pushes the transistor towards ON state.The overall photocurrent is therefore increased.
A low level of dark current is a great advantage of junction-less phototransistors over photoconductors.However, lack of junctions can generally lead to a low optical gain.Due to the small cross sectional area of nanowires, the absorption in nanowires and therefore the quantum efficiency of the device would also be low [3].Both of these issues could lead to a poor noise equivalent power (NEP) for the phototransistor.In this study, we propose ways to improve the performance of the junction-less, silicon based phototransistor in terms of optical gain and sensitivity, by modifying the channel geometry and band-structure engineering by using multiple gates.Such a structure is able to potentially detect very low light intensities.

Phototransistor design: role of nanowires
Figure 1(a) illustrates the proposed structure.The channel in this structure (top view) is partly wide for light absorption and partly narrow to lower the dark current (NW 1 that is covered by the 'primary' gate).We also modify the source region by adding a second nanowire, NW 2 , and a 'secondary' gate that allows for controlling the carrier concentration in the source, without the need for changing the doping concentration in the source region, as will be discussed shortly.
For discussion and demonstration purposes, we use the wavelength of 630nm in this work.The semiconductor in this study is p-type, and therefore the primary gate has to be biased positively to keep the phototransistor in OFF state.The total channel length is 5µm.The channel is 2µm wide everywhere except at the nanowire regions.The gate oxide thickness is 20nm.Such photodetector can be integrated into a pixel by being connected to a high impedance integration node.A capacitor at this node converts the photocurrent into a voltage value that is read out later [4,16].
The first key element in our design is the channel.In junction-less transistors, the channel is normally very thin to ensure the gate is able to fully deplete it.Considering the relatively small absorption coefficient of silicon at the wavelength of interest (≈3.9x10 3 cm −1 [17]), the drawback of the thin absorption region is low external quantum efficiency.Therefore, we try to increase the thickness of the semiconductor layer, while making sure the gate is still strong enough to fully deplete the channel.This is achieved by replacing the channel underneath the primary gate with a narrow layer, as marked with NW 1 in Fig. 1(a).Use of NW 1 allows for introducing the gate in three dimensions, which helps to complete the depletion of the channel.Furthermore, since the gate control over NW 1 is strong, the channel and the gate can be short, while still avoiding short channel effects.Narrow, short regions can also lead to a smaller capacitance imposed by the gate, and speed up the device operation compared to long gates.
The rest of the channel on the drain side is kept wide, to provide a surface for absorption of light.Furthermore, the position of the primary gate is towards areas closer to the source, to increase the surface for photon absorption between gate and drain, similar to the base and collector junction in a bipolar phototransistor [18].We chose a silicon thickness of 0.85µm for this work that would result in a quantum efficiency of about 20%, assuming the light that is illuminated on the top of the device, is mainly absorbed over the wide areas.The surface reflection is also assumed to be about 0.3.A thicker semiconductor layer would of course lead to higher quantum efficiency.However, considering the nanowire widths of a few hundred nanometers and narrower, fabricating the gate contact over such high aspect ratio channel can be challenging.
The next key modification comes from the concept of bipolar transistors.In a welldesigned bipolar transistor, to push the emitter efficiency towards unity, the doping level of the emitter (source) has to be much larger than the base (channel) [18].To satisfy this condition, instead of actually doping the source region with acceptors, we use a 'secondary' gate to control the carrier concentration of the source, the same way we use the 'primary' gate to control the carrier concentration over the channel.The secondary gate is located in an area between the primary gate and the source contact.For a p-type semiconductor the secondary gate is biased negatively in order to increase the concentration level of holes over the source region.Since the impact of the gate in carrier accumulation is local, in order to make the gate effect more tangible, the area underneath the secondary gate is narrowed down, as shown by NW 2 in Fig. 1(a).We note that the narrow regions of NW 1 and NW 2 are more like narrow slabs and not nanowires in thick devices.However, the ultimate goal is to replace them with nanowires that bridge the thick, wide areas of channel and source.The conduction and valance bands of the device, together with the Fermi level are plotted in Fig. 1(b).The data is obtained along the channel, shown by cutline AA' in the top view of Fig. 1(a).To obtain this data, the primary gate is biased at +1V, while the secondary gate is biased at −1V.The source and drain contacts are both connected to the ground.The energy band diagram clearly shows the resemblance of the device to a pnp bipolar transistor.The electron and hole concentration of the structure in Fig. 1(c) also confirm that electrons are the majority carriers in the channel area under the primary gate; while holes are the majority carriers in the source and drain regions.The secondary gate increases the concentration of the majority carriers in the source region, similar to the high doping level at the emitter of a junction bipolar transistor.If the secondary gate is removed, the barrier height on the sourcechannel region will decrease, as marked with dashed lines in Fig. 1(b).Similarly the concentration of holes on the source side declines, as plotted in Fig. 1(c).
Figures 1(b) and 1(c) clearly demonstrate the importance of both gate/nanowire geometries in our design.The primary gate/ NW 1 combination is responsible for converting a simple photoconductor into a phototransistor; while the role of the secondary gate/NW 2 is to control the optical gain.Since other works, such as [9] have illustrated the role of gate/ nanowire geometry (primary gate/ NW 1 in our design) on the output parameters, the focus of this work is investigating the impact of NW 2 on the performance parameters of the phototransistor.
We note that there are significant differences between the device proposed here and the one in reference [19].The lateral bipolar action in each device is maintained differently, due to the fact that the operating principles of the junction and junction-less transistors are different.In [19], the OFF state was obtained via the reverse biased drain-channel p-n junction and the primary gate that accumulated the carriers within the channel.Whereas here, the potential barrier during the OFF state is created only by the primary gate that pushes the channel towards depletion and inversion.In both structures, the nanowire/secondary gate combination is used to increase the optical gain; but the implementation is different.The secondary gate in [19] was added over the channel for the purpose of lowering the barrier by depleting the carriers.Here the role of the secondary gate is to artificially create a junction.This eliminates the need for having a doped p-n junction, and simplifies the design of the junction-less phototransistor.

Results and discussion
Figure 2(a) shows how the source current is influenced by the voltage of the secondary gate [20].Figure 2(b) shows the conduction band energy of the structure, along the channel, for different voltages of the secondary gate.The primary gate is biased at +1V to create the OFF state potential barrier.To emphasize the importance of the secondary gate, we have plotted the current at both positive and negative values of secondary gate.When the secondary gate is biased positively, it acts like an extension of the primary gate.The device exhibits a low level of dark current, as it is biased in the OFF state.The current is increased when the device is illuminated.However, in comparison with the case of dark, the barrier height of the illuminated structure shows a very slight change (Fig. 2(b)), suggesting that the optical gain is small, and in fact calculations show an optical gain of less than 1.
As the secondary gate bias is shifted towards more negative values, the drain current starts to increase.The conduction band energy in Fig. 2(b) shows an increase in the carrier concentration at the source region, as if it is doped with a higher concentration of acceptors.This directly impacts the emitter efficiency of the structure, that is rephrased below, based on the definition of the emitter efficiency in a one dimensional, pnp junction transistor [18]: Reinterpreting the definition of the emitter efficiency to suit the junction-less transistor case, I p denotes the current of the holes, diffusing from source into the channel; and I n is the current of the electrons that are injected into the source from the channel.When the concentration of holes in the source is increased, the holes that diffuse into the channel outnumber the channel electrons that diffuse into the source.The ratio of I p /I n would therefore increase, and the emitter efficiency approaches the limit of 1.As a result, one expects a larger current.Although the secondary gate bias affects both dark, and photo-currents, the change in the current is less pronounced at dark.As illustrated in Fig. 2(a), at dark the current changes by about 40 times when the secondary gate is changed from +1V to −2V.For the same conditions, the photocurrent changes more than 700 times.This is due to the fact that at dark the device is in its OFF state, even when the secondary gate is negatively biased.Under such condition, the potential barrier is slightly higher than the case when the secondary gate is positive (Fig. 2(b)).This change in the potential barrier is responsible for the larger dark current at negative bias of the secondary gate.However, the source-channel junction is still reverse biased and the current change is low as a result.Whereas under illumination and when the secondary gate is negative, the source-channel junction is forward biased, allowing for a larger current to pass.The potential barrier of the structure shows a more dramatic change under illumination, confirming that the detector has a larger emitter efficiency.As a result, the dark current increase is smaller than the increase in photo current, in agreement with the numerical results in Fig. 2(a).
Narrowing the size of NW 2 can similarly lead to an increase in the current.This is verified in Fig. 3(a), where the source current versus the width of NW 2 is plotted.The current change is attributed to fact that accumulation of holes under the secondary gate is a local effect.We have plotted the conduction band energy for two source widths of 100nm, and 20nm in Fig. 3(b).The energy band is obtained along a cutline across the source.When the source is wide, only the areas that are very close to the interface are in accumulation.As the source width is narrowed down, a larger percentage of the channel is influenced by the secondary gate, and the net concentration of holes is increased.The emitter efficiency, and therefore the source current will both increase.
Similar to the case of the secondary gate bias, the influence of the width of NW 2 on the source current is less at dark condition.For example, in Fig. 3(a) the source current changes by more than two orders of magnitude when the device is illuminated; while the dark current varies by about 25 times.This behavior is also due to the smaller emitter efficiency of the device at dark, as discussed previously.
Investigation of the role of the length of NW 2 is plotted in Fig. 4(a).We note that the total length of the detector is kept fixed.Elongating NW 2 causes the source current to increase; however, it does not change the barrier height under the secondary gate (Fig. 4(b)).The change in the current is attributed to the funneling effect [19].The long, narrow diffusion pathway creates a physical barrier for electrons and slows down the diffusion process.This By combining the three parameters discussed in this section, the secondary gate bias, the width, and the length of NW 2 , it is possible to improve the performance of the junction-less phototransistor in terms of illumination current and noise equivalent power.We have tabulated a few cases in Table 1.The data ranges from different biases of the secondary gate, to different widths and lengths of NW 2 .The most dramatic increase in the optical gain takes place where the width of the nanowire is reduced from 400nm (first row) to 20nm (second row).This verifies the importance of having a narrow region under the secondary gate.Decreasing the voltage and increasing the length of the secondary in rows 3 and 4 are both effective, but the improvement is not as much as the change in the width of NW 2 .We note that for the data presented in the table the secondary gate is biased in accumulation, which is the best possible bias as verified in Fig. 2(a).We have also included a case in which the thickness of NW 2 is reduced (fifth row), as if a nanowire bridges the channel and the source regions.The effect of decreasing the thickness of NW 2 is very similar to the effect of decreasing its width.It strengthens the control of the secondary gate over NW 2 and increases the concentration of majority carriers.As a result, one expects a better emitter efficiency and photocurrent.Although the case of the narrow, thin NW 2 seems to be challenging in terms of fabrication, it exhibits the best photocurrent and NEP among the other devices in the table.
-2 1 Width of NW 1 =200nm, Length of primary gate=200nm, Semiconductor thickness=0.85µm,VG primary =1.0V 2 A surface reflection of 30% is considered.The photocurrent presented here is multiplied to transmission. 3The noise sources considered in calculating the NEP are input and source shot noise, and also the thermal noise of the channel.We did not calculate the Flicker noise, as it strongly depends on how the device is fabricated.The load is considered to be infinitely large; otherwise the thermal noise of the load at room temperature dominates.
We remark that for the results presented in Table 1 the effect of the surface states is not included, while the large surface to volume ratio in nanowires can lead to carrier recombination, and therefore degradation of the photodetector response.To study this, we chose the devices on rows 2 and 5 of Table 1, and investigated their response while the effect of surface states included.The surface recombination velocity of passivated silicon nanowires ranges from less than 13cm/s to about 61cm/s in the state of the art structures reported in literature [21][22][23].In our simulations, the surface recombination velocity is assumed to be 13cm/s.As a result of surface recombination, the photocurrent of the device on the second row of Table1 has dropped to 3.6 × 10 −11 A. The device in the fifth row of the table has a thinner NW 2 , which translates into a higher surface to volume ratio.The photocurrent of this device is decreased to 1.45 × 10 −10 A. The decrease in the photocurrent is due to the recombination of carriers within both NW 1 and NW 2 regions.In NW 1 , carrier recombination leads to losing some of the photo-generated carriers.As a result, the barrier would not decrease as much as in the ideal case, leading to degradation in the overall current flow.Recombination of carriers as they pass through NW 2 is also responsible for further decrease in the current.Work to decrease the surface recombination velocity and bulk recombination times will be helpful in increasing the optical gain but as expected they will lead to an increase in the time scales associated with the transient response.
The speed of the photodetector depends on a different set of physical processes during the rise and fall of photocurrent.When the light source is turned ON, the rise time (speed) is limited by the RC time constant.The capacitance (C) is determined by the two gates, and the resistance (R) is determined by the narrow NW regions.Since in the devices presented, NW 2 is longer and narrower than NW 1 , we expect the time constant of this region to dominate.Once the light source is switched OFF, the extra carriers in the NW 1 region recombine and increase the potential barrier (under the primary gate) to its original value.In this case the size of NW 2 does not cause much variation in the fall time, as the dominant process is the carrier recombination in NW 1 .
The transient response of a structure with NW 1 = 200nm, and NW 2 = 20nm is plotted in Fig. 5.The logarithmic scale in the inset shows that when the light is switched OFF, the current drops by about 3 orders of magnitude in the first few milliseconds.Normally external circuits in a pixel apply a reset signal to the photodetector to decrease the fall time.We have also summarized the rise time and fall time of two more structures in Table 2.The data shows a small difference in values as the size of NW 2 is changed.   1 Rise time: the time the current chnages from 10% to 90% of the peak value. 2 Fall time: the time the current drops from 90% to 10% of the peak value. 3Width of NW 1 = 200nm, Length of primary gate = 200nm. 4VG primary = 1.0V,VS = 0.5V, VD = 0V, Intensity = 10 −4 W/cm 2 . 5First two rows: VG secondary = −1.0V;third row VG secondary = −2.0V.

Conclusion
In summary, we proposed a new geometry for junction-less phototransistors.In this design, instead of having an entirely narrow channel, we keep the channel partly narrow and partly wide for electrostatic and optical reasons, respectively.The narrow region is covered by a primary gate that creates the potential barrier required for phototransistor operation.The wide area of the channel provides a surface for better light absorption.Further boost of the optical

Fig. 1 .
Fig.1.(a) Junction-less phototransistor with multiple gates.The semiconductor is entirely ptype (doping: 10 15 cm −3 ), with the thickness of 0.85µm.The total channel length is 5µm.The channel is 2µm wide everywhere except the narrow regions.The gate oxide is 20nm (not shown in figure).The secondary gate is lifted up to show the narrow region NW 2 .A similar geometry is present underneath the primary gate that is shown in the top view, where the gates' top layer is removed.Light is shined through a window with the area of 5.6µm 2 .(b), (c) Energy band diagram and carrier concentration (logarithmic scale) of the structure, along cutline AA', located about 100nm below the top silicon and oxide interface.Dashed lines represent the energy band and carrier concentration when the secondary gate is removed.VG primary = 1V, VG secondary = −1V, VS = 0V, VD = 0V.

#Fig. 2 .
Fig. 2. (a) Source current versus the secondary gate bias in the junction-less phototransistor.The primary gate is 200nm long and covers a 200nm wide channel.The secondary gate is 1.2um long, and covers a 20nm wide region (NW 2 ).(b) Impact of the secondary gate bias over conduction band energy of the structure along the channel (cutline AA').VG primary = 1.0V,VS = 0.5V, VD = 0V.

Fig. 4 .
Fig. 4. (a) Source current versus nanowire length underneath the secondary gate.(b) Conduction band energy, along the channel for different lengths of the secondary gate and NW 2 .For both cases the primary gate is 200nm long and covers a 200nm wide nanowire, and the secondary gate covers a 20nm wide channel.VG primary = 1.0V,VG secondary = −1.0V,VS = 0.5V, VD = 0V.