Germanium photodetector with 60 GHz bandwidth using inductive gain peaking

: Germanium-on-silicon photodetectors have been heavily investigated in recent years as a key component of CMOS-compatible integrated photonics platforms. It has previously been shown that detector bandwidths could theoretically be greatly increased with the incorporation of a carefully chosen inductor and capacitor in the photodetector circuit. Here, we show the experimental results of such a circuit that doubles the detector 3dB bandwidth to 60 GHz. These results suggest that gain peaking is a generally applicable tool for increasing detector bandwidth in practical photonics systems without requiring the difficult process of lowering detector capacitance.


Introduction
Silicon has in the past decade become the subject of intense interest for use in photonics. There are a number of advantages to using silicon as a platform for photonics including the high degree of confinement that silicon offers, the ability to leverage the fabrication knowledge and investments developed by the CMOS electronics industry and the possibility of integrating many components into complex photonic integrated circuits (PICs) [1]. Recently, the silicon photonics community has begun to move from working on individual devices to creating more complex systems [2]. However, continued effort into improving the performance of individual devices is required to ensure stability and raise the performance of such systems.
A critical component of the silicon photonics infrastructure is the germanium photodiode. Germanium is widely used as the detector absorption element due to its ability to absorb light at communications wavelengths and its CMOS compatibility. Techniques have been developed to grow germanium epitaxially on a silicon substrate with few defects [3][4]. However the relatively low absorption coefficient of germanium necessitates larger detectors to obtain reasonable responsivity. The increased area increases the capacitance of the detector junction, which correspondingly reduces the detector bandwidth. Significant work has been done to minimize this capacitance and develop high-speed waveguide-coupled germanium photodetectors [5][6][7][8]. By optimizing both the detector fabrication and geometry, detector bandwidth above 100 GHz has been reported [9]. However, for integrated photonics in silicon it is often not practical to optimize the process solely to lower detector capacitance.
Gain peaking is a technique that has been used in the design of electronics systems such as CMOS amplifiers [10][11] and photoreceiver amplification [12][13][14]. However, the authors are unaware of any previous demonstration of detector peaking that has been integrated directly on a silicon photonics chip. We have demonstrated that it is possible to significantly increase detector bandwidth using metal layers that are commonly available in CMOS-compatible silicon photonics processes [15].

Baseline Detector Modeling
Modeling of detectors can involve complex models and simulations [16][17]. Due to the small width of the intrinsic region of the germanium on silicon, waveguide-coupled detectors, the RC constant is the limiting factor in the bandwidth and transit time effects can be largely ignored [18][19]. The RC circuit often gives a reasonably accurate model for the response of a photodetector. We denote R load as the load resistance, C pd as the detector capacitance and R pd as the detector resistance. The cutoff frequency for this simple model is given by Eq. 1.
We take the bandwidth denoted by f c to be the 3dB point at which the photocurrent has been reduced by a factor of sqrt (2). The load resistance can be considered either the input to a transimpedance amplifier (TIA) or another type of 50-Ω load.
It is possible to increase the bandwidth by reducing either the detector capacitance or resistance. The detector capacitance scales with the area of the detector and is dependent on a number of variables such as the detector's intrinsic width and the doping concentrations. While the capacitance can be estimated analytically, it is more accurate to measure the capacitance for a given process. Using a number of test structures of different areas, the capacitance per unit area was measured as a function of voltage as seen in Fig. 1. Junction capacitance per unit area as a function of reverse bias voltage (positive voltage on graph is reverse bias). The curve was measured by determining the capacitance from the detector S11 parameter (as seen in inset) using a number of test structures of different areas. The junction capacitance In this work, the detectors were 8 um wide and 10 um long at the base with a 4x7.6 um junction for a junction capacitance of about 15 fF. As the detector area is minimized and the bias voltage increased, the capacitance of the photodetector is decreased and other parasitics in the circuit play a larger role. The largest of these parasitics is the capacitance due to the contact pads. The pads used in this study are 60 um x 60 um with a 100 um pitch and have a total capacitance of about 13 fF calculated by both simulation (Ansoft HFSS) and direct measurement. With smaller detectors, the parasitic pad capacitance is on the order of the detector capacitance and must be accounted for in the detector circuit model as a load parallel to the load resistance (C load ).

Gain Peaked Detector Modeling
It has previously been shown that adding an inductor to a photodetector circuit will act to increase the 3-dB bandwidth by peaking the EO response [20]. In order to evaluate how the detector circuit will respond to the addition of an inductor, we introduce another circuit model shown in Fig. 2. In this model, a non-ideal inductor element [12][13] has been added that contains an inductance L ind and a series resistance R ind in parallel with a capacitance C ind . The transfer function of this circuit is given by, where the impedances Z ind and Z load are given by Z ind =1/(C pk ⋅ s + 1/(L pk ⋅ s + R pk )) (4) Two different inductors were designed for use in gain peaking. Both inductors utilize twoloop square spiral geometries built using 1.5-um thick aluminum traces with 10-um width. The majority of the loop uses the thick top metal layer while only the metal crossing occurs in the thinner lower metal to minimize resistance. The small inductor (see Fig. 3) used an inner loop width of 20 um and an outer loop width of 50 um while the large inductor used a 50 um inner loop and an 80 um outer loop. Three-dimensional electromagnetic simulation was done on these inductor geometries using a commercial software package (Ansoft HFSS). The simulations showed that the small inductor had about 360 pH of inductance and 9.7 fF self-capacitance, while the large inductor had 580 pH of inductance and 19.8 fF self-capacitance. Both inductor elements had a relatively low series resistance of about 1Ω/GHz 1/2 .

Fabrication
The detectors were fabricated at the Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR) as part of the OpSIS-IME MPW service [21]. The platform uses a 220 nm thick SOI wafer with 2-um buried oxide (BOX) as seen in Fig. 4. A 60 nm silicon etch is used to define the grating coupler layer while a 220 nm silicon etch is used to build the 500 nm waveguides. The detector was built using selectively grown epitaxial germanium on top of the silicon. The germanium layer was 500 nm thick and had an angled sidewall. A 90 nm slab layer was also used to maximize the evanescent coupling between the silicon and the germanium. The silicon beneath the germanium was doped with boron to form the p-type side of the junction. The top of the germanium was implanted with phosphorous to form the n-type side of the p-in junction as seen in Fig. 5. A lower level of via was fabricated to contact both the n-type germanium as well as the p-type silicon. The first metal layer was then added, followed by an additional layer of vias and the second metal layer. An oxide cladding was deposited and opened above the metal pads that were used for probing the detector.

Testing Configuration
The photodetectors were tested using a fiber array with polarization maintaining (PM) fiber to couple light on and off chip using a pair of grating couplers. A well-calibrated y-junction split the light path to go both to the detector and to an output grating coupler. This configuration allowed for accurate alignment to the grating couplers and precise calculation of the power incident on the detector.
For the detector S-parameter measurement, a vector network analyzer was used to drive a high-speed lithium niobate modulator and measure the detectors electrical response. The frequency response of the modulator was calibrated using an ultra-high-speed (70 GHz), commercial photodetector and normalized out of the response of the detector under test. A GSG microprobe was used to contact the metal pads of the detector.

Device Performance
Three detectors were tested to determine the efficacy of the gain peaking technique using the small inductor and the large inductor as well as a detector with no inductor to provide a baseline. Using a 2V reverse bias, DC responsivity and dark current were measured to be .75 A/W and 3 uA respectively with small variations between detectors due to fabrication-coupler alignment and fabrication variation. The approximate photodetector resistance (R pd ) was measured by fitting the IV curve of the detector at a forward bias of around 1V.
An EDFA was used to increase the signal to noise ratio and allow measurement of the detector response up to a frequency of 67 GHz as seen in Fig. 6. From the frequency response of these detectors, it is evident that gain peaking does have a significant effect at frequencies beginning around 10 GHz. The detector with no added inductance exhibits the lowest 3 dB bandwidth of around 30 GHz. The detector with the large, 580 pH inductor shows a large response peak near 35 GHz followed by a steep drop in response and a 3 dB bandwidth near 50 GHz. The detector with the small, 360 pH inductance on the other hand has less of an extreme peak, but has a higher 3 dB bandwidth near 60 GHz. A least-squares circuit model fit was obtained by using the simulated and measured detector parameters with the EO S21 response of Eq. 2. The fit parameters are shown in Table 1. A few of the fit values such as C pd vary between detectors. This may be due to either fabrication variation of the p-i-n junction or an inexact fit of the detector response. The above fits of EO S21 are fairly accurate in both the frequency of the peaking and magnitude of the peaking. However, there is a small discrepancy in the EO S21 fit at lower frequencies that is likely due to measurement error. The phase delay is calculated from the model and closely fits the measured phase as seen in Fig. 7a. The addition of an inductor increases the group delay variation as seen in Fig. 7b from -1.5 ps at 40 GHz for the unpeaked detector to 2.1 ps and 12.3 ps at 40 GHz for the small inductor and large inductor respectively. The group delay of the large inductor detector is approaching the 25 ps period at 40 GHz, which may negatively impact digital signal quality. We do not expect a significant increase in detector noise from the inductor as shown in [20].

Conclusion
We have shown experimental evidence that the bandwidth of germanium on silicon can be significantly enhanced with the addition of a peaking inductor. The inductor can be fabricated with metal processes that currently exist on CMOS-compatible integrated photonics platforms. Using a spiral inductor of 360 pH, the bandwidth of a non-peaked detector was enhanced from 30 GHz to 60 GHz.