The influence of substrate on SOI photonic crystal thermo-optic devices

We investigate the influence of the substrate on a photonic crystal thermo-optic device on a silicon-on-insulator (SOI) platform. The substrate-induced thermo-optic tuning is obtained as a function of key physical parameters, based on a semi-analytic theory that agrees well with numeric simulations. It is shown that for some devices, the substrate's contribution to the thermo-optic tuning can exceed 10% for a heater located in the waveguide core and much higher for some other configurations. The slow response of the substrate may also significantly slow down the overall response time of the device. Strategies of minimizing the substrate's influence are discussed.


Introduction
Silicon is an attractive material for making photonic integrated circuits due to its excellent compatibility with the well-developed CMOS technology [1,2]. The SOI platform provides additional benefits for the integration of photonic devices, such as low optical loss, low power consumption, high stability, and high speed [3]. Key components of silicon photonic circuits include optical switches, delay lines, and modulators. The thermo-optic (TO) effect is an attractive option to implement optical switches and tunable delay lines if high speed is not a requirement, because it avoids free carrier absorption of light that is present in the electrooptic devices. Furthermore, understanding of the TO effect also helps in the design of silicon electro-optic modulators because the current flow associated with carrier movement is usually accompanied by heat generation [4]. The incorporation of photonic crystal (PC) structures in these devices results in significant reduction of the interaction length due to the slow light effect [4][5][6][7][8][9][10][11][12]. Ultra-compact optical switches and modulators utilizing different PC structures have been widely studied recently.
A thermo-optic PC device is based on the principle that the temperature variation in the structure induces a change of its refractive index, which in turn leads to a phase shift and a time delay for an optical signal. In an SOI PC structure, the total temperature rise (and thus the total phase shift or time delay) comprises contributions from the temperature rise across the oxide layer as well as that in the substrate. In prior simulations and theoretical studies, the substrate effect is usually assumed to be small and only a relatively thin substrate layer (e.g. <20μm) is included in simulations [8]. The effect of a full substrate (e.g. ~500μm in actual SOI wafers) has not been studied. In this work, we investigate the influence of the substrate as a function of a number of key physical parameters such as the heater length, the substrate thickness (t sub ) and the thickness of the buried oxide layer (t ox ). Our results reveal some important aspects/scenarios in which the influence of the substrate can be surprisingly high and cannot be neglected in device design. As numerical simulation of a full substrate can be extremely time-consuming, we have developed a semi-analytic theory that can be used for quick assessment of the substrate effect in thermo-optic device design. Guided by this theory, strategies of minimizing the influence of the substrate will be discussed.  Figure 1 shows the schematic of an active PC structure on an SOI wafer with a heat source of width W and length L embedded in the core of the photonic crystal waveguide (PCW). The heat source can be constructed from a lightly doped (e.g. ~10 14 cm −3 ) Si strip surrounded by relatively highly doped (e.g. ~10 17 cm −3 ) silicon on both sides [5,12]. Concentrated ohmic heating can be produced in the center strip by passing current laterally through this structure. The top PCW layer can be modeled by an equivalent hole-free homogeneous slab with an effective thermal conductivity κ eff , which is determined by the PCW structure [12]. This method helps to significantly mitigate the simulation difficulties for such a multi-scale structure and makes it possible (albeit still very time-consuming) to simulate a structure with a full substrate thickness of 500μm. A typical 3-D steady state FEM simulation result is shown in the inset of Fig. 2(a). The bottom surface of the chip is kept at T 0 = 300 K to emulate a heat sink under the substrate. Because the heat dissipation from the top and side surfaces is negligible due to the small thermal conductivity and a small heat transfer coefficient in natural convection of air, adiabatic boundary conditions are used for these surfaces [6,[12][13][14]. The values of the thermal conductivities of silicon (κ Si ), silicon oxide (κ ox ) and photonic crystal κ eff are from Ref. [12]. y x z (a) 1 10 100

Substrate temperature profile
10 100 To gain insight into heat conduction in the substrate and develop a semi-analytic model, we first consider the effective cross-sectional area (in the x-y plane) of the vertical heat flux, and then utilize an electric field analogy to obtain the vertical temperature profile in the substrate. Our previous work showed that the heat flux at the top surface of the buried oxide layer has an effective width of W + 2X spr due to lateral thermal spreading in the silicon PCW cladding, where X spr is given by / spr Si ox eff ox X t t κ κ = and t Si is the thickness of the top Si layer. As the heat flows down through the oxide layer, it also spreads laterally. With a fixedangle heat spreading model, we can readily show that the effective width and length of the heat flux cross-section are increased by ΔW = ΔL = 2t ox tan45° after passing through the oxide layer and reaching the top surface of the substrate [15,16]. A schematic diagram of the crosssection of this model is shown as the inset of Fig. 2(b). On the top surface of the substrate, the effective heat flux cross-section has the dimensions of ' ( 2 2 )and ' ( 2 ).
Using the above effective width and length of the heat flux at the top surface of the substrate, the temperature distribution in the substrate can be modeled separately using an electric field analogy. In electrostatics, the potential drop along the z-axis due to a finite sheet of charge uniformly distributed on the x-y plane and centered at the origin is given by [17] where ρ s is the charge density, ε is the permittivity, and W and L are the width and length of the sheet. It is well known that the steady state heat conduction equation resembles the static electric field equation as both are Poisson's equations [18]. By the thermal-electrical analogy,it can readily be shown that for a similar heat source of width W' and length L', the temperature profile along the z-axis in a semi-infinite (z>0) homogeneous medium is given by where Q is the power of the source, and κ is the thermal conductivity of the medium. Note the z axis points downward and z = 0 is assumed to be on the top surface of the substrate. The factor 2 is due to the semi-infinite medium (the mirror image of the half space of z>0 in the other half space of z<0 that will add a source at z = 0 − so that this half space problem corresponds to a full space problem with a source of 2Q). The integration in Eq.
(3) has a fairly lengthy result, The FEM simulation and semi-analytic results for the temperature profile in the substrate along the z-axis are plotted in Fig. 2(a) for three different values of heat source length. Note that the temperature of the substrate bottom surface, T(t sub ) = T 0 , is used as the reference. In addition, simulations are performed for different values of t ox , as plotted in Fig. 2(b) along with the analytic results. Evidently, the vertical temperature profiles given by semi-analytic theory agree fairly well with the FEM simulations. As could be expected, the (total) temperature rise in the substrate, ΔT sub ≡T(0)−T(t sub ), increases as L or t ox decreases.

Fractional thermo-optic tuning due to the substrate
Estimation of the temperature rise in the substrate is important because the temperature change in the top silicon device layer is affected by the temperature rise across the buried oxide layer as well as that of the substrate (ΔT tot = ΔT ox + ΔT sub ). For example, in thermooptic tunable delay lines, the total change of the delay time in the PCW (Δτ tot ), which is proportional to the total temperature rise in the waveguide (for small change of refractive index Δn<<1), is also affected by the temperature rise in the substrate. Assume Δτ tot = μΔT tot , where μ is a constant depending on the thermo-optic coefficient of silicon. Because Δτ tot = μΔT ox + μΔT sub , we can define the substrate-induced delay tuning as Δτ sub = μΔT sub (note that Δτ sub does not mean the time delay of light in the substrate, but the delay in the waveguide due to the substrate temperature). Note that ΔT ox can also be analytically expressed as [12] / ( [ 2 ]). Simulations are performed to estimate the fractional thermo-optic tuning due to the substrate. First, the influence of the substrate thickness is investigated. Simulations and semianalytic calculations are carried out for three different substrate thicknesses and varying heat source lengths. As shown in Fig. 3(a), analytic results agree well with the FEM simulation.
Their difference in f sub is less than 5%. From the plot, it is evident that as the substrate thickness increases, f sub increases as expected. In Fig. 3(b), simulation and analytic results are plotted for different buried oxide layer thicknesses. As t ox increases, ΔT sub decreases (and ΔT ox increases); consequently f sub decreases.
For some slow-light delay line applications in the nanosecond range or beyond, the PCW length may reach the millimeter scale or beyond, assuming group indices n g in the range of 30~100 [12,19]. For thermo-optic delay tuning, similar heater lengths are required. It can be observed in Fig. 3(b) that the value of f sub increases as the heater becomes longer. To explore its upper limit for very long heaters, f sub is calculated semi-analytically for L up to 10mm and the trend is shown in a semi-log plot in Fig. 4. Interestingly, as L continues increasing, f sub increases asymptotically towards a finite upper limit whose value depends on t ox . This upper limit occurs because for L→∞, the structure can be treated as a two-dimensional problem in the x-z plane. For L→∞, it is necessary to define the linear power density as Horizontal dashed lines in Fig. 4 show the upper limit of f sub calculated with Eq. (5). Evidently, they agree very well with the results from Eq. (3) at long L. In typical SOI devices, t sub is on the order of hundreds of microns and W′ is on the order of tens of microns, thus t sub >>W'. This can be used to further simplify Eq. (5) Calculations show that the Eq. (6) is a good approximation for Eq. (5). The difference between them is typically very small (e.g. <1%) for t sub >3W'. Thus, Eq. (6) is useful in estimation.

Minimizing the substrate-induced thermo-optic effect
Although 10% contribution from the substrate might be inconsequential in some digital applications, it can be a significant issue for many analog applications. For example, for tunable optical delay lines used in phased array antennas, the beam angle is proportional to the delay difference between adjacent elements [20]. A 10% variation of the delay difference (which is tuned thermo-optically) will cause a 10% deviation of the beam angle, which represents a significant issue for high-resolution radars (requiring accuracy of ~0.25° for up to 60° scanning angles [21]). Furthermore, in transient from one delay state to another state, the substrate temperature profile generally takes a very long time to reach its steady state whereas the oxide temperature profile stabilizes very fast. For precision analog applications, the slow response of the substrate may play a dominant role in determining the overall response time of the device. Consider the example shown in Fig. 5, where the time-dependent ΔT ox , ΔT sub , and ΔT tot data are extracted from a FEM simulation of the transient response of a structure. Note that ΔT ox and ΔT sub defined in this work do not refer to a uniform temperature increase in the oxide and the substrate, but the temperature difference between the upper and lower surfaces of these two regions. The rise time (10% to 90%) for ΔT sub is on the order of 100μs whereas the rise time (10% to 90%) for ΔT ox is on the order of 1μs. Note that the 10% point of these traces are all very close to t = 0 and their difference in time is very small. On the other hand, the time difference of the 90% points of the ΔT sub and ΔT ox traces is very large; thus only the 90% points are marked. The fall time of each curve is on the same order as its respective rise time. The rise/fall time can be estimated from 2 / Z c τ ρ κ where ρ is the density and c the specific heat capacity of the material and Z is the heat conduction length in this material [12]. For ΔT ox , the pertinent material is the oxide, Z is the thickness of the buried oxide layer. For ΔT sub , the pertinent material is silicon, Z is on the order of the substrate thickness. Silicon and SiO 2 have comparable ρc; and κ Si is about two orders of magnitude higher than κ ox . The substrate thickness is usually two orders larger than the buried oxide thickness. Based on these values, the transient response of the substrate is expected to be roughly two orders of magnitude slower than the buried oxide layer. Assume an analog application requires 1% delay tuning accuracy. Then the device analyzed in Fig. 5 is considered stable only after ΔT sub reach ~90% of its steady-state value (so that ΔT tot reaches 99% of its steady-state value because this device has ΔT sub~0 .09ΔT tot in the steady-state). Therefore, for this analog application, the device response time is practically ~100 μs. This is much longer than the intrinsic response time of the oxide layer.  According to the above discussions, it would be desirable to minimize the influence of the substrate in order to speed up the device response and improve the device stability/precision for many analog applications. To this end, it would be useful to analyze how the upper limit of f sub (L→∞) varies with key physical parameters. Results are plotted in Fig. 6 for different substrate thicknesses and oxide thicknesses. It can be seen that the influence of the substrate can be reduced by increasing the thickness of the buried oxide layer. This reduction can be attributed to two trends: ΔT ox increases as t ox 1/2 and ΔT sub decreases with t ox due to the term ln[2t sub /(W + 2X spr + 2t ox )] in Eq. (6) [12]. When the oxide layer is thicker than 5μm, f sub is less than 5% for all cases shown in Fig. 6. Furthermore, reducing the substrate thickness can also reduce ΔT sub according to Eq. (5). It can be readily shown that f sub varies faster than t ox -1/2 with respect to the oxide thickness and varies logarithmically with t sub . Thus, mathematically, f sub can be more effectively reduced by increasing t ox .
However, in practice, thicker oxide layers are less preferable for a number of reasons. First, it would be challenging and costly to achieve t ox >5μm in making high-quality SOI wafers. Second, by increasing t ox , the heat conductance between source and sink becomes smaller, which hampers device heat dissipation. Third, thicker oxide will lead to an increase of response time [12], which is not desirable for many active devices. On the other hand, a thinner substrate will provide better heat conductance and thus reduce the response time. Moreover, with the recent advance of membrane technology [22,23], the substrate can be easily reduced to less than 10μm . Thus membrane based devices could help to reduce the substrate-induced thermo-optic tuning.
It should be noted that the structure shown in Fig. 1 is optimal. If the heater is located on a lateral edge of the PCW (e.g. heater located at x heater = 7μm, and the PCW core located at x core = 0), then the temperature rise in the PCW core ΔT core could be 2~3 times smaller than the ΔT tot at the heater due to the exponential temperature drop along x [12]. This can affect f sub in the PCW core. To analyze such a case, we need to consider the total temperature rise in the top Si layer ΔT tot , the vertical temperature difference between top and bottom surfaces of the substrate ΔT sub , and the vertical temperature difference in oxide ΔT ox in two different vertical planes at x = x heater and x = x core , respectively. Obviously, the temperature rise in the core is just ΔT tot in the plane at x = x core , ΔT core ≡ΔT tot (x core ). The actual delay tuning is determined by ΔT core . Because ΔT core is much lower than ΔT tot (x heater ), the fractional thermal tuning in the PCW core due to the substrate in this case f sub (x core ) = ΔT sub (x core )/ΔT core could be much larger than ΔT sub (x heater )/ΔT tot (x heater ) given in preceding sections. In the worst case, f sub (x core ) may exceed 20% in a non-optimal structure. ΔT sub (x core ) ΔT ox (x core ) ΔT core Fig. 7. Simulation result for a non-optimal case where the heater is located at the PCW lateral edge, 7μm from the PCW core (other parameters of this structure are same as in Fig. 5). All temperatures are evaluated in the vertical plane at x = x core . Note ΔT core ≡ΔT tot (x core ) = ΔT ox (x core ) For example, for the structure simulated in Fig. 5, if the heater is moved to a lateral edge about 7μm from the PCW core, f sub (x core ) will reach ~25%, as shown in Fig. 7. Because f sub (x core ) is far above 10%, the 10%-90% rise/fall time of ΔT tot (x core ) also elongates to ~12μs (compared to ~1μs rise/fall time from 10% to 90% for ΔT tot in Fig. 5). This can explain the long rise time observed in prior experiments where the heater is located at the PCW edge (for example Ref. [8]). Note that 20% contribution is not negligible in many digital applications, as well as analog applications. This illustrates the importance of design optimization in a wide range of thermo-optic tuning/switching applications. In some cases, configurations with a heater at the PCW edge may be desirable for ease of fabrication, but the performance tradeoff needs to be considered for a specific application. The formulas given in this work are useful to guide the design optimization and evaluate the substrate-induced thermal tuning. Note that this theory also indicates that many factors have relatively weak influence on the device performance. For example, the hole radius of the photonic crystal structure, in its typical range (r/a = 025~0.35), has a relatively weak influence on f sub , as shown in the inset of Fig. 6. The heater width W is usually recommended to be relatively small to improve the heating efficiency [12]. As such, typically W<<2X spr , and the influence of W on the ΔT sub is fairly small according to our calculation. Also note that due to the complex anisotropic structure of a narrow heater embedded in a photonic crystal waveguide, the traditional fixedangle spreading model is not applicable to this entire structure. The fixed-angle model can, however, be useful for a single thin layer such as the buried oxide layer. Within the top silicon layer the temperature variation is very small along y and z axes [12].
Note that there exist small discrepancies between the analytic results and FEM simulation results. The maximum discrepancy of ΔT sub between two approaches is less than 5% in all cases we have simulated. The discrepancy can be attributed to several models used in this semi-analytic theory, including the quasi-1D model for heat transfer in a SOI PCW [12] and the fixed angle spreading model in buried oxide layer [15,16]. Each of these models has been validated in proper conditions with reasonable accuracy (e.g. <6% in Ref. [12]). Also note that in most cases, ΔT sub contributes less than ~12% of ΔT tot . Therefore, 5% discrepancies of ΔT sub contribute less than 0.6% of the discrepancies of the overall temperature ΔT tot . Such discrepancies of ΔT tot are considered very small and very difficult to further improve upon. Furthermore, it should be noted that our motivation for developing a (semi-)analytic theory to describe a phenomenon is not to achieve best accuracy, but to gain physical insight that cannot be obtained through numerical simulations, such as how ΔT sub scales with many key physical parameters given in an analytic expression. It would be highly challenging to obtain such scalings or trends through FEM simulations when multiple parameters are involved and some parameters are varying over a large range. For example, to obtain the asymptotic trend shown in Fig. 4 through FEM simulations, it would require a prohibitive amount of computational resources because it would be necessary to simulate many instances of extremely long/large devices with both L and t ox varying.
It would be interesting to extend this theory to study the substrate-induced effect in other device geometries including air-bridge PCWs or non-photonic crystal structures. For some photonic structures, the ratio of the device dimension along y-axis over that along x-axis is not as large as in PCWs. It can be expected that the substrate-induced effect in such structures will resemble short PCWs, which suggests f sub is typically a smaller value according to Fig. 4. It may also be interesting to extend this work to integrated circuits on a SOI wafer. Because the transistors generally have smaller dimensions along x and y axis, it is expected that the substrate temperature rise due to a single transistor is fairly small. For a complicated circuit including many transistors and metal interconnects in multilayer 3D configurations, it remains a challenging problem to investigate the substrate-induced thermal issues. Detailed discussion of these further research topics is beyond the scope of this work.

Conclusion
In conclusion, the influence of the substrate on SOI thermo-optic photonic crystal devices is studied in terms of key physical parameters. The temperature rise in the substrate is calculated semi-analytically. The accuracy of the semi-analytic results is verified by the FEM simulations. The upper limit of the fractional delay tuning due to the substrate is obtained as a function of key physical parameters. For long delay lines, the substrate-induced fractional delay tuning could exceed 10% for heaters in the PCW core and exceed 20% for heaters at the PCW lateral edge. The slow response of the substrate may cause the device to take a long time to stabilize, which may significantly elongate the de facto response time of the device (by 10~100 fold). This could explain slow response observed in some non-optimal device structures and help guide further device optimization. Scaling of the substrate's influence with key structure parameters is analyzed. Strategies of minimizing the influence of the substrate are discussed.