Forward error correction supported 150 Gbit/s error-free wavelength conversion based on cross phase modulation in silicon

: We build a forward error correction (FEC) module and implement it in an optical signal processing experiment. The experiment consists of two cascaded nonlinear optical signal processes, 160 Gbit/s all optical wavelength conversion based on the cross phase modulation (XPM) in a silicon nanowire and subsequent 160 Gbit/s-to-10 Gbit/s demultiplexing in a highly nonlinear fiber (HNLF). The XPM based all optical wavelength conversion in silicon is achieved by off-center filtering the red shifted sideband on the CW probe. We thoroughly demonstrate and verify that the FEC code operates correctly after the optical signal processing, yielding truly error-free 150 Gbit/s (excl. overhead) optically signal processed data after the two cascaded nonlinear processes.


Introduction
In recent years many experimental demonstrations have adopted the trend of assuming the use of FEC codes to render measured BER values of ~10 −3 error-free. However, only very few experiments actually implement a real FEC code [1,2]. As most FEC codes have limitations, such as difficulties in correcting certain types of systematic errors, e.g. bursty errors, it is important to experimentally verify the implemented FEC for any given system. Experiments relying on nonlinear optical signal processing have only very rarely actually employed a FEC module. Wavelength conversion is interesting to test with FEC, since it processes all the bits in the data stream in one go, and to the best of our knowledge this has only been done at 10 Gbit/s [2] and not for ultra-high bit rates yet.
In this paper, we build a FEC module and implement it in an optical signal processing experiment. The experiment consists of two cascaded nonlinear optical signal processes, i.e. 160 Gbit/s all optical wavelength conversion based on XPM in a silicon nanowire and subsequent 160 Gbit/s-to-10 Gbit/s demultiplexing using a highly nonlinear fiber (HNLF). We show that the FEC module enables truly error-free (no errors) performance (post-FEC) for the nonlinear optically processed data with an overhead of 6.6%. We thoroughly demonstrate and verify that the FEC code indeed operates correctly, yielding truly error-free 150 Gbit/s (excl. overhead) optically signal processed data even after the two cascaded nonlinear processing steps.

Forward Error Correction (FEC)
We have designed a product code (1020 × 1020) with Bose-Chaudhauri-Hocquenghem (BCH) component codes (1020, 988) inspired by I.9 in [15]. This component code corrects 3 errors and detects 4 by adding two extra parity bits. The frame size is 1020x1020 using a simple block interleaver as illustrated in Fig. 1(a). The "overhead" for the parity symbols is 6.6%. Computer simulations of the performance are shown in Fig. 1(b). The figure also includes an estimate of the lower bound (error floor), calculated along the lines of [16]. When the error floor is reached most frames are decoded without errors, but a few frames are left with around 16 bit errors. The simulations show that with 3 iterations (3 times row and column decoding) the output Bit-Error-Rate is below 1E-10 at input BER 3.4E-3, and indicate that the output BER will be below 1E-15 for input BER < 3.0E-3.  Figure 1(b) also includes experimentally measured points, which agree well with the simulations for a 3 iteration case, as implemented. The experimental setup is very similar with the one in section 4, but just back-to-back measurement without all-optical wavelength conversion. The experimental result verifies the code very well. The input BER value (pre-FEC BER) is set to a certain target value by adjusting the received power, but during the measurement, this value drifts to a worse BER due to a clock drift in the flip-flop, and the plot in Fig. 1(b) shows the maximum and minimum pre-FEC BER and the corresponding post-FEC BER measured over 10 s. The minimum (optimized case) pre-FEC BER points agree well with the simulations. In a simple 10 Gbit/s back-to-back case the setup was left running for one hour at a target pre-FEC BER of about 3E-3, and the FEC corrected all errors yielding an error-free post-FEC data signal. Thus 3.6E13 bits where transmitted truly error-free. Since the errors after decoding are expected to occur as 16 bits in error in some frames, it is important to calculate the expected number of these frames based on the results of the experiment. The decoding of the frames is independent so the number of erroneous frames is a Poisson distributed variable with parameter λ. Erroneous frames are rare events so it is difficult to estimate λ and its variance, which results in that the usual method of calculation of confidence intervals does not work. Instead we use the approach by [17] where bounds for λ are calculated such that with a certain probability the observed results were possible. With zero errors observed, the calculation gives that the actual number of erroneous frames with probability 95% is between 0 and 3.00. Thus the actual BER may be upper bounded by 3.00 For the BCH decoders the syndromes are calculated only once and updated during the iterations. The final decoding (calculation of error locations) are based on a number of table look-ups using the method of [18]. Multiplications in the finite field, GF(2 10 ), are also done with table look-up.
The decoder is built around a pipeline structure with RAM blocks for storage of 6 frames and corresponding syndromes. The structure is shown in Fig. 2. When the frame is received, the row syndromes are immediately calculated and while the next frame is received the column syndromes are calculated. Now follows the three iterations where the final decodings are performed by two parallel row decoders and two parallel column decoders. Each of these updates both the data and the syndromes; therefore, these are ready for the succeeding decoding. The final pipeline stage is just output. As a total we have implemented 12 parallel BCH decoders and perform 3 iterations with a latency of 5 frames. The decoder is implemented in an Altera Stratix IV FPGA (EP4S40G2F40I2) using 15% of the logic cells and most of the RAM blocks. The Decoder is running on a 250 MHz clock with 40 bit input each clock cycle, i.e. 10 Gbit/s.   The pulse pump can modulate the refractive index of the silicon waveguide, which results in phase modulation on the co-propagating continuous wave (CW) probe, as shown in Fig. 3(b). The phase modulation will then result in transient chirp on the CW probe. The rising edges of the pump pulse will generate red-shift chirp, whereas the falling edges of the pump pulse will generate blue-shift chirp. The blue shifted and red shifted sidebands are generated as a result of the chirp. If an off-center filter is used to extract either blue shifted sideband or red shifted sideband, the XPM-induced phase modulation can be converted into amplitude modulation. When an RZ-OOK data signal is used as the pump, the generated sideband can pass through the off-center filter in the presence of '1' bit of the pump, whereas no generated sideband results in no transmission through the off-center filter in the presence of '0' bit of the pump. Roughly speaking, the sideband generated on the CW probe is a combined result of the Kerr effect and an index change due to generated carriers. The Kerr effect, such as self phase modulation (SPM) and XPM, is an ultra-fast process with a response time of ~fs. On the other hand, carrier based effects in silicon, such as free carrier absorption (FCA) and free carrier dispersion (FCD), has slow dynamics with the order of several hundred picoseconds to several hundred nanoseconds [10]. The rising edge of the pump pulse excites free carriers through two photon absorption (TPA), which will slowly recover and thereby affect the falling edge of the pump pulse by the FCA. However, the slow dynamics of the carrier recovery only contribute by a small amount to the total blue-shift chirp as it results from the time derivative of the phase modulation. Therefore, this will only affect the blue shifted sideband close to the CW probe and can be avoided by further off-center filtering. In a previous investigation, both blue shifted and red shifted sidebands were filtered out for the wavelength converted signals [14]. In the present experiment, only the red shifted sideband with the absence of the free carrier effect is filtered and used as the wavelength converted signal.

Cross phase modulation (XPM) in a silicon nanowire waveguide
The device used in the experiment is a dispersion engineered straight 3.6 mm long silicon nanowire with a cross-sectional dimension of 240 nm × 450 nm (height × width), which includes tapering sections for low-loss interfacing with optical fiber [3]. The device has a silicon-on-insulator (SOI) structure, with the silicon waveguide placed on a SiO 2 /Si substrate. The measured propagation loss is 4.3 dB/cm and the fiber-to-fiber loss of the device is 5.5 dB. The experimental setup for the FEC supported 10 Gbit/s AOWC in a silicon nanowire is shown in Fig. 4. The erbium glass oscillating pulse-generating laser (ERGO-PGL) produces 10 GHz pulses at 1542 nm with a 1.5-ps full-width at half-maximum (FWHM) pulse width. The spectrum of the pulses is broadened in a 400-m dispersion-flattened highly nonlinear fiber DF-HNLF (dispersion coefficient D = −0.45 ps/nm/km, dispersion slope S = 0.006 ps/nm 2 /km at 1550 nm, and nonlinear coefficient γ = 10.5 W −1 km −1 ) due to self-phase modulation (SPM) [19]. The broadened spectrum is filtered at 1562 nm with a 5-nm optical bandpass filter (OBF). The generated 10 GHz pulses at 1562 nm with the full width at half maximum (FWHM) of 1 ps are then on-off keying modulated either by a 10 Gbit/s PRBS (2 31 -1) signal or by the FEC module coded data pattern (see section 2) in a Mach-Zehnder modulator. The PRBS signal is used to measure pre-FEC bit error ratio (BER) and the FEC coded signal is used to measure post-FEC BER.

FEC supported 10 Gbit/s all optical wavelength conversion (AOWC) in silicon
In the AOWC, the 10 Gbit/s data signal at 1562 nm is combined with a CW beam at 1546 nm using a 3-dB coupler, and then launched into the silicon nanowire. The data pump average power is 18 dBm and the CW power is 16 dBm. At the output of the silicon nanowire, the CW light is off-center filtered at 1549 nm with a detuning of 3 nm and only the red-shift sideband is selected for the wavelength converted signal.
In the 10 Gbit/s receiver with the FEC module, the wavelength converted 10 Gbit/s signal is pre-amplified and then detected by a photo-detector. The flip-flop is used to convert an RZ signal to an NRZ signal. The FPGA with the FEC decoder (described in section 2) is used to decode the data pattern and correct the errors. Finally, the BER after the FEC decoding can be calculated.    Figure 5 shows optical spectra at the input and output of the silicon nanowire for the 10 Gbit/s case. At the output, the spectrum of the pump (10 Gbit/s RZ signal) is asymmetrically broadened due to both the Kerr effect (such as SPM) and carrier effects (such as FCA and FCD). The SPM can symmetrically broaden the spectrum, but the FCA and the FCD effects can shift the output spectrum towards shorter wavelengths (so called free-carrier induced blue shift) [3,20]. The combined Kerr effect and carrier effects (as described in section 3) result in the asymmetric sidebands (Fig. 5). Finally, the red shifted sideband is filtered and amplified as the wavelength converted signal.
To test if the FEC coding would still properly correct errors for the optically processed (i.e. wavelength converted) signals, we measured pre-FEC BER and resultant post-FEC BER for the converted signal, as shown in Fig. 6. The converted signal has slightly better pre-FEC BER performance compared to the back-to-back (B2B) case since the '0' level noise is suppressed after the wavelength conversion ( Fig. 6(b) and 6(c)), which indicates potential regeneration using XPM based AOWC in silicon. The post-FEC BER for the converted signal behaves as expected and drops very rapidly to BER < 1E-11 at a received power of −44.4 dBm, which confirms that the optical signal processing does not generated unexpected errors and can be well supported by the FEC. The setup was left running for 1000 s, and no post-FEC errors occurred, corresponding to an expected BER < 1E-13 (this confirms with 95% confidence a BER upper bound < 4.8E-12). The experimental setup for the FEC supported 160 Gbit/s AOWC in a silicon nanowire is shown in Fig. 7. The 10 Gbit/s data signal is generated as described in section 4, and subsequently multiplexed up to 160 Gbit/s using a fiber based multiplexer. The 160 Gbit/s OTDM signal at 1562 nm is merged with a CW beam at 1546 nm into the silicon nanowire, and then off-center filtered at 1549 nm. The data pump average power is kept at 18 dBm, same as the 10 Gbit/s AOWC case. This corresponds to the energy consumption of ~390 fs/bit, which is at the same order of magnitude with the FWM based wavelength conversion at the same bit rate [3].

FEC supported 160 Gbit/s AOWC in silicon and subsequent 160 Gbit/s-to-10 Gbit/s demultiplexing in a HNLF
The wavelength converted 160 Gbit/s signal is then demultiplexed down to 10 Gbit/s using a nonlinear optical loop mirror (NOLM). The NOLM operation is based on cross-phase modulation (XPM) in a 50-m highly nonlinear fiber (HNLF). Finally, after the cascaded nonlinear optical signal processing the 10 Gbit/s data signal is detected in the 10 Gbit/s receiver with the FEC module (described in section 4).   Figure 8(a) shows optical spectra at the input and output of the silicon nanowire for the 160 Gbit/s AOWC. Compared to the 10 Gbit/s AOWC in silicon, the asymmetrical pump (160 Gbit/s RZ signal) spectral broadening and asymmetrical sideband generation on the CW probe are not obvious since the peak power of the pump is much lower (only 1/16) and the TPA induced carrier effect is almost negligible. The red shifted sideband of the CW probe is filtered and amplified as the 160 Gbit/s wavelength converted signal. Figures 8(b) and 8(c) show the optical sampling eyediagrams for the 160 Gbit/s B2B signal and wavelength converted signal. The eyediagram of the converted signal looks clear and open, though slightly broader than the B2B due to narrow optical filtering. Figure 9(a) shows measured pre-FEC BER curves directly using an error analyzer and with a PRBS 2 31 -1 data signal. The pre-FEC BER performance of the converted signal is almost identical with the B2B case, indicating a good wavelength conversion. All the 16 converted channels are below the FEC limit (3E-3), as shown at the bottom of Fig. 9(b). We then measured the absolute pre-FEC and post-FEC errors using the FEC module ( Fig. 9(b) upper and middle). The FEC module properly corrects the errors to yield zero errors for all 16 demultiplexed wavelength converted channels, even though the input errors vary from 185 to 1780 per frame. All 16 channels have no error for 10 seconds measurement, corresponding to an expected BER < 1E-11, i.e. a 150 Gbit/s (exclude overhead) truly error-free signal. Channel no.1 is even tested for longer time and it has no error for > 100 seconds, corresponding to an expected BER < 1E-12. This measurement confirms again optical signal processing is well supported by the FEC even after two cascaded nonlinear optical processing operations.

Conclusion
We have shown that our developed FEC module enables truly error-free (no errors) performance (post-FEC) with an overhead of 6.6%. By off-center filtering the red shifted sideband on the CW probe, 160 Gbit/s all optical wavelength conversion is achieved based on XPM in silicon. In the 160 Gbit/s wavelength conversion using a nonlinear silicon waveguide and subsequent 160 Gbit/s-to-10 Gbit/s demultiplexing using a HNLF, we thoroughly demonstrated and verified that the FEC code indeed operates correctly, yielding truly error- free 150 Gbit/s (excl. overhead) optically signal processed data after the two cascaded nonlinear processes.