Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb / s

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PICoff-chip for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 Vpp, the integrated 1 mm-phase-shifter modulator in the PICoff-chip demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of VπLπ ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at −1V. The fabricated silicon PICintra-chip for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. 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Advancement of silicon photonics technology can offer a new dimension in chip-level data communications by providing high-performance optical interconnects with un-precedent bandwidth based on the cost-effective silicon photonic/CMOS platform [1][2][3][4][5].In recent years, silicon photonics has shown remarkable progress , and is starting to find its position in practical applications in telecommunications and data communications.
Increasing the integration level in silicon photonics is required to develop compact highperformance optical interconnects for future systems.There have been reports on silicon photonic integration at various levels [31][32][33][34][35]. Monolithic integration of multiple optical components on the same wafer to realize silicon photonic integrated circuits (PICs) can costeffectively increase both functionality and performance.Continued performance improvement of silicon photonic devices and their integration levels based on CMOS fabrication technology is necessary for full utilization of silicon photonics in chip-level data communications and telecommunications.
Silicon optical modulators and Ge-on-Si photodetectors, which are the main active components in silicon optical transceiver circuits, have made remarkable progress .The silicon optical modulator, a key device for transmitting optical data, is based on the freecarrier plasma dispersion effect, where the refractive index of a silicon waveguide can be modulated by either carrier injection in a PIN diode or carrier-depletion effect in a PN diode [6][7][8][9][10][11][12][13][14][15][16][17][18].In the modulator for chip-level optical interconnects, it is important to achieve high modulation efficiency up to high data rates with low optical loss while minimizing size for high energy efficiency.Intensive work has been done in this area in recent years.Silicon Mach-Zehnder (MZ) modulators and resonator-type modulators based on a PN junction in reverse bias modes have shown potential for wideband high-speed performance due to their faster modulations utilizing fast carrier depletion effects.Using vertical and lateral PN junctions, depletion-mode modulators with various efficiencies in high speed operation from 10 Gb/s up to 40 Gb/s have been reported [7][8][9][10][11][14][15][16][17][18].Most of the reported silicon MZ modulators require relatively high driving voltages greater than 6 to 7 V pp to achieve efficient modulation depths.Low driving voltages below 1.2 V pp potentially allow a modulator to be driven by monolithically integrated high-speed CMOS driving circuits, and also indicate low energy consumption.The Ge-on-Si photodetector, the key device for receiving optical data in a silicon chip, has also shown impressive progress in performance.Several Ge photodetectors have been reported for their large bandwidths and high responsivities.The reported waveguide-type Ge photodetectors [19][20][21][22][23][24] and vertical-illumination type Ge photodetectors [25][26][27][28][29][30] have achieved high performance comparable to conventional semiconductor photodetectors.
Simultaneous increases in the photonic integration level and the performance levels of the constituent devices are important.We previously reported a high-efficiency carrier-depletion PN-diode-based 12.5 Gb/s silicon MZ modulator [11] and a 12.5 Gb/s racetrack resonatortype silicon optical modulator [12].We also presented high-performance verticalillumination-type Ge-on-Si photodetectors grown by reduced pressure chemical vapor deposition (RPCVD), and a 10 Gb/s Ge photoreceiver with −19.5 dBm sensitivity for a BER of 1 × 10 −12 at λ~1550nm [28][29][30], which can readily replace conventional III-V compound semiconductor photodetectors.In this paper, we have investigated simultaneous increases in the silicon photonic integration level and the performance levels of constituent silicon photonic devices.
Silicon PICs for chip-level optical data I/Os (inputs/outputs), that is, off-chip (inter-chip) and on-chip (intra-chip) optical interconnections have been fabricated, into which both silicon MZ modulators (MZM) and Ge waveguide photodetectors (PDs) were monolithically integrated on a Si-on-insulator (SOI) wafer, using a fabrication process compatible with CMOS integration.The integrated modulators of the PICs were optimized in terms of speed, efficiency, driving voltage, and optical loss simultaneously.For the monolithic integration of the Ge PDs, a simplified fabrication process was performed based on selective expitaxy growth (SEG) using RPCVD with omitting chemical mechanical polishing (CMP) and doping for Ge.Also to further increase of the integration level to electronic-photonic IC (EPIC), we hybrid-integrated a silicon PIC chip with 0.13µm CMOS interface circuit chips, which include modulator-drivers, trans-impedance amplifiers (TIAs) and limiting amplifiers (LAs).In the followings, the design, fabrication, performance characterizations up to 30 Gb/s operation are described.The silicon photonic devices and CMOS circuits were designed and fabricated in array form in this work.The two types of silicon PICs for the off-chip optical interconnect (PIC off-chip ) and the onchip optical interconnect (PIC intra-chip ) consist of carrier-depletion-type asymmetric MZ modulators for 8-channel photonic transmitter parts, evanescent-coupled waveguide-type Ge PD for 8-channel photonic receiver parts, and grating couplers (GCs) for optical I/O coupling of fiber with silicon waveguides, which were monolithically integrated on a 6-inch SOI wafer with a top Si thickness of 220nm and a buried oxide thickness of 1µm as shown in Fig. 1. integrated Ge PDs are shown in the bottom region of each chip.The modulator is defined on an asymmetric Mach-Zehnder interferometer (MZI) with 2x1 multi mode interferometers (MMIs) and lateral PN junction phase shifters embedded in both arms.The Ge PD is integrated onto an 8 µm-wide silicon waveguide.The PIC off-chip chip shown in Fig. 1(a) has three kinds of GCs for surface normal coupling to fibers.GC1 is for input coupling of the external CW laser light into the chip to feed the MZMs, and GC2 is for the modulated optical outputs transmitted off the chip.GC3 couples the externally modulated input signals into the chip to be delivered to the integrated Ge PDs.The performance of the integrated active components in the PIC off-chip , therefore, can be characterized individually.On the other hand, in the PIC intra-chip for intra-chip optical interconnection, the integrated modulator and the Ge PD are directly connected by the waveguide on the same chip, and GC1 for input coupling of the external CW laser light into the chip is integrated in Fig. 1(b).The optical signal modulated across a MZ modulator is transmitted through the connecting waveguide, the width of which is tapered from 0.5µm to 8µm, to be directly detected by the monolithically integrated Ge PD in the PIC intra-chip .High-resolution focused ion beam (FIB) transmission electron microscope (TEM) and scanning electron microscope (SEM) cross-sectional images and schematic views of the modulator phase shifter and the integrated Ge PD are shown in Fig. 1(c) and Fig. 1(d), respectively.
For the fabrication of silicon PICs, ridge waveguides which configure or connect photonic devices were defined by I-line lithography and high dense plasma (HDP) dry etching process on a 6-inch SOI wafer.The silicon grating couplers with the pitch of 0.315µm were defined on the waveguides.The target etch depth was 70 nm.The ridge waveguide with 100 nm slab height is 0.5µm wide for the modulator, and 8µm wide for the Ge PD.In designing the PN depletion diode for a modulator, the electrical speed of a junction, carrier-dependent loss, and index change efficiency were considered simultaneously.These factors are related to each other based on the device configuration.The free carrier absorption loss is relatively large for the modulation efficient PN diode waveguide.Hole depletion can cause larger refractive index change, whereas electron depletion can give faster electrical response.Lower P-type doping than N-type doping reduces the total capacitance and enhances the operating speed.High N-type doping does not increase the total capacitance, and it enhances phase shift efficiency.The configuration of doping concentrations was designed to achieve a larger bandwidth by reducing junction capacitance with effective refractive-index change for modulation efficiency and relatively reasonable optical loss of the phase shifter.The target doping levels of the lateral PN junctions formed on the phase shifters on both arms of a modulator were 1×10 18 cm −3 for the P-region and 3×10 18 cm −3 for the N-region.The P ++ , N ++ implants for a Si modulator and the N ++ implant for a photodetector were performed to the doping concentration levels of ~1×10 20 cm− −3 , followed by an activation process at 900°C for 30 seconds.After a 1-µm-thick SiO 2 layer was deposited, 6×13 µm 2 windows in SiO 2 above the predefined 8 µm-wide waveguides were etched by reactive ion etching (RIE) for the selective expitaxy of Ge.The growth of a 900 nm-thick Ge layer, which comprised a 0.11 µm-thick Ge single-crystal seed layer grown at 400°C and a Ge layer grown at 650°C without further thermal annealing was performed on a predefined window area, followed by the deposition of a 100 nm-thick P + polysilicon layer over Ge using RPCVD.This epitaxial growth of the Ge photodetector structure greatly simplifies the monolithic integration process by omitting chemical mechanical polishing and additional doping processes for Ge [28][29][30].Metallization with 950nm-thick Ti/TiN/Al_1%Si/TiN and an alloying process were performed.The fabricated devices for channels showed reasonable uniformity in characteristics.
For the device characterization, continuous wave (CW) light from a tunable laser source was coupled to the GC on a chip through a polarization controller to feed a modulator, and the electrical signal from an external driver was connected to drive the modulator in a PIC.In the PIC off-chip chip, the optical signal modulated across an integrated MZM was transmitted off the chip through the output GC to fiber, and boosted using an erbium doped fiber amplifier (EDFA).This optical signal was measured by an Agilent 86100A Digital Communication Analyzer (DCA).Also the external optical input data signal was fed to the GC to be detected by the integrated Ge PD, and this detected electrical signal was measured by the Agilent DCA.  Figure 2(a) shows typical optical transmission spectra of the 1mm-phase-shifter MZM measured at various DC biases.Here, only one phase shifter arm is biased.An avalanche breakdown of the device occurs around −10 V.The black solid curve in Fig. 2(a) represents the transmission spectrum of the unbiased modulator.As is shown in the figure, total optical loss at the maximum of the transmission for a 1mm-phase-shifter MZM is measured to be ~22 dB at λ~1538.1 nm, which includes 1.7 dB/MMI loss, phase-shifter loss of 3.2 dB/mm, passive waveguide propagation loss of ~0.2 dB/mm, and ~7.5 dB loss for each grating coupler.Large coupling loss through grating couplers, which requires resolution of 315 nm, resulted from the I-line lithography limit greater than 350 nm.The free spectral range (FSR) of the integrated modulator is ~5.4 nm.The yellow solid curve represents transmission spectrum of the modulator biased at −6 V, which shows the wavelength shift, ∆λ of ~1.0 nm.The voltage-induced wavelength shift, ∆λ/∆V, is measured to be ~0.17nm/V.The voltageinduced phase shifts, ∆φ=2π∆λ/FSR for a 1 mm-phase-shifter MZM are shown in Fig. 2(b).The modulation efficiency, V π L π , the applied voltage and length required to obtain ∆φ = π, was ~1.59 V•cm.
The high-speed performance of the integrated modulator was characterized by measuring the 3dB bandwidth and eye-diagrams at high transmission rates.The electrical speed of the modulator using a reverse biased PN junction is limited by capacitance.The measured capacitance of the modulator is < 840 fF near −3 V DC .The predicted RC-limit −3dB bandwidth, f -3dB = 1/(2πRC), of the modulator was ~22 GHz.The frequency response measurement of the integrated modulator of a PIC off-chip was carried out using a 20GHz HP 8730A lightwave component analyzer (LCA).The high-speed electrical signal and DC bias voltage were applied to the modulator through a bias-tee and a 40 GHz RF probe.The modulated output signal was amplified using an EDFA, before it was fed into the LCA.The measured frequency responses of the 1mm-phase-shifter MZM with varying reverse bias on one phase-shifter arm are shown in Fig. 3(a).As shown in the graph, the measured bandwidth of a modulator is ~14.3GHz at −2 V DC bias, and 15.0 GHz at −5 V DC bias.Here, a travelling-wave electrode was not adopted for the device.The discrepancy between the measured bandwidth and the RC-limit bandwidth of the device resulted from the un-optimized metal electrode.On-wafer measurements of eye diagrams were performed at various bit rates from 12.5 Gb/s to 30 Gb/s for the integrated modulator in PIC off-chip .The non-return-to-zero (NRZ) pseudo-random bit sequence (PRBS) 2 31 -1 signal of the Anritsu MP1758A pulse pattern generator (PPG) was combined with a DC bias using a bias-tee, and applied to the modulator.The modulator was driven differentially with RF signals from 1.2 V pp to 2.5 V pp .The input CW beam from a tunable laser was passed through a polarization controller and coupled to GC1 of Fig. 1(a) to feed the modulator.Due to the large GC coupling loss, relatively high optical input power was required in the measurement.The modulated output signal from the PIC off-chip chip was coupled to fiber probe aligned with GC3.EDFA was used to boost the modulated output signal, and a tunable wavelength filter was used before light signal was The low driving voltage of 1.2 V can allow a MZ modulator to be driven by monolithically integrated high-speed 0.13µm CMOS driving circuits.Figure 4 shows lowvoltage operation characteristics of the 1 mm-phase-shifter MZM of the PIC off-chip driven differentially with 1.2V pp using a 12.5 Gb/s PRBS signal source.The measured optical eye exhibits an ER of 10.5 dB at −3V DC bias for λ~1542.1 nm.The additional optical loss of ~4dB is measured at the '1' level of the signal compared with the maximum transmission case.This represents a large improvement compared to our previous result using a similar modulator [11].The higher driving voltage of 2.5 V pp resulted in larger extinction ratios.Figure 6 exhibits the performance of the integrated 1 mm-phase-shifter MZM of the PIC off-chip for 2.5V pp drive with −5 V DC bias.The measured ERs are 12.68 dB and 9.41 dB for 20 Gb/s and 30 Gb/s operation, respectively.Here, the measured additional optical losses at the '1' level of the signal compared to the maximum optical transmission are 1.4dB and 1.9dB for 20 Gb/s and 30 Gb/s operation, respectively.Also, the same modulator at 12.5 Gb/s operation exhibits a high ER of 13.45 dB for 2.5V pp drive.For characterization of the 6×23µm 2 Ge PIN waveguide photodetector integrated on the silicon waveguide in a PIC off-chip , the external light data signal was delivered to the PD through GC3 of Fig. 1(a) coupled to an optical fiber probe.The device exhibited low dark current under 700 nA at 1 V reverse bias.The frequency response was measured by impulse response measurement with a Pritel femtosecond pulse laser and the Agilent DCA with an 8611A 70 GHz remote sampling module.Figure 7 In the measurements of the PIC intra-chip , where intra-chip photonic interconnect could be investigated, higher optical input power was required than in PIC off-chip case.The CW light from a tunable laser was amplified by an EDFA and was coupled into the grating coupler through an optical filter and a polarization controller to feed the integrated MZM.Also, the PRBS electrical input signal was applied to drive the modulator.The optical signal modulated by the MZM transmits through the connecting silicon waveguide to be detected and converted into the electrical output signal by the monolithically integrated Ge PD in the same chip.The electrical output signal reflecting on-chip optical data interconnection was measured by the DCA with an 86105C 20 GHz electrical module.Figure 9 shows on-wafer measurements of optical eye diagrams in the PIC intra-chip , where on-chip data transmissions of 12.5 Gb/s up to 20 Gb/s occur from the integrated 1 mm-phaseshifter MZM to the monolithically integrated Ge PD at λ~1542.7 nm.The NRZ PRBS signal from the Anritsu PPG was applied to the MZM.Here, the modulator was driven with a 2.5 V pp signal at −5V DC bias and the PD was biased at −3V.This measured eye patterns were raw signals detected by the integrated Ge PD without any preamplifier ICs involved.Although the same devices were integrated, the performance showed degradation compared with that of the 30 Gb/s PIC off-chip case, resulting from the high input optical power.The background heat in the chip and the ASE noise of EDFA limit the performance of both integrated devices.Further improvement in the coupling efficiency of the grating coupler and To further increase the integration level to the electronic-photonic IC, we hybridintegrated a silicon PIC intra-chip chip with 0.13µm CMOS interface circuit chips.Figure 10(a) shows photographic images of the hybrid silicon EPIC.The test setup for EPIC characterization is shown in the inset.The EPIC assembly is die-attached and wire-bonded on a test PCB, and a fiber is aligned with the grating coupler for optical input.In the figure, the top chip is a CMOS modulator-driver IC, the middle chip is a silicon PIC intra-chip chip and the bottom chip is a CMOS TIA-LA IC chip.The CMOS modulator-driver IC is the cascode voltage-mode driver designed for high voltage swings up to 3V pp with a measured bandwidth of 5 GHz.The TIA is designed based on an RGC feedback loop with two coupled shunt series peaking inductors [36].The measured bandwidth of the TIA in the chip is 7.9 GHz.The limiting amplifier is designed to have 6 gain stages with an offset compensator.The buffer and output driver IC are also included in the TIA-LA IC chip.Figure 10(b) shows the electrical performance of the modulator-driver IC and the TIA-LA IC measured at 7 Gb/s and 10 Gb/s operation.The size of the 8-channel CMOS modulator-driver chip is 4.3mm × 1.5mm, and the chip size of 8-channel CMOS TIA and LA is 4.2mm × 1.8mm.Figure 10(c) shows the measured "eye" diagram of the hybrid silicon EPIC for on-chip optical interconnection for 5, 8, 10 Gbps operation with V RF = 1.3 V pp .As seen in the figure, the performance of the EPIC is limited by the performance of the 0.13µm CMOS interface circuits.Upgrading in CMOS interface ICs with a lower driving voltage design can improve the performance of silicon EPICs.With continued improvements in CMOS interface ICs and silicon photonic devices, we expect to develop even more efficient silicon PICs and EPICs leading to high performance interconnections for future inter/intra-chip applications.
In conclusion, we presented the performance of silicon photonic integrated circuits for offchip optical interconnects (PIC off-chip ), where monolithically integrated PN depletion-mode MZ modulators and evanescent-coupled Ge waveguide PD on a SOI wafer demonstrated data transmissions up to 30 Gb/s.For the low-voltage drive of 1.2 V pp , the integrated 1mm-phaseshifter modulator of the PIC off-chip demonstrated a phase shift efficiency of V π L π ~1.59 V/cm with 10.5dB ER for 12.5 Gb/s modulation, 9.1dB ER for 20 Gb/s modulation and 7.2dB ER for 30 Gb/s modulation.The integrated Ge waveguide PD grown by RPCVD showed good eye diagram for 30 Gb/s operations with low dark current levels.Also, the silicon PIC for intra-chip optical interconnect (PIC intra-chip ), where the light signal modulated by the integrated modulator is detected by the monolithically integrated Ge PD in the same chip, exhibited on-chip optical interconnection up to 20 Gb/s.We also presented the silicon EPIC, where a silicon PIC intra-chip chip and 0.13µm CMOS interface circuit chips for modulatordriver and preamplifier IC were hybrid-integrated.Based on our results, further optimizations in the smaller MZ modulator with high efficiency and the integrated PD, and improvement in CMOS interface ICs can lead to more efficient silicon PICs and EPICs for future inter/intrachip interconnect applications.

Fig. 1 .
Fig. 1.Top views of microscopy images of the fabricated monolithically-integrated silicon photonic IC (PIC) chips for (a) off-chip optical interconnect (PICoff-chip) and (b) on-chip optical interconnect (PICintra-chip).The TEM, SEM cross sectional images and schematic diagrams of (c) monolithically integrated silicon MZ modulator phase shifter, and (d) integrated Ge photodetector.

Figure 1 (
a) shows top-view microphotographs of a fabricated 8.7mm×3.5mmPIC off-chip chip, and Fig. 1(b) shows a fabricated 6.3mm×3.5mmPIC intra-chip chip.The integrated MZ modulators are shown in the top regions of the PIC off-chip and the PIC intra-chip chip, and the #156656 -$15.00USD Received 19 Oct 2011; revised 30 Nov 2011; accepted 8 Dec 2011; published 16 Dec 2011 (C) 2011 OSA

Fig. 2 .
Fig. 2. Optical transmission spectra of the integrated asymmetric MZ modulator (MZM) with 1-mm-long phase shifter at biases from 0V to −9V, and (b) the voltage-induced phase shifts.

Figure 2
Figure 2 plots the measured transmission spectrum of the integrated modulator of the PIC off-chip as a function of the wavelength, which demonstrates high modulation efficiency.Figure2(a) shows typical optical transmission spectra of the 1mm-phase-shifter MZM measured at various DC biases.Here, only one phase shifter arm is biased.An avalanche breakdown of the device occurs around −10 V.The black solid curve in Fig.2(a) represents the transmission spectrum of the unbiased modulator.As is shown in the figure, total optical loss at the maximum of the transmission for a 1mm-phase-shifter MZM is measured to be ~22 dB at λ~1538.1 nm, which includes 1.7 dB/MMI loss, phase-shifter loss of 3.2 dB/mm, passive waveguide propagation loss of ~0.2 dB/mm, and ~7.5 dB loss for each grating coupler.Large coupling loss through grating couplers, which requires resolution of 315 nm, resulted from the I-line lithography limit greater than 350 nm.The free spectral range (FSR) of the integrated modulator is ~5.4 nm.The yellow solid curve represents transmission spectrum of the modulator biased at −6 V, which shows the wavelength shift, ∆λ of ~1.0 nm.The voltage-induced wavelength shift, ∆λ/∆V, is measured to be ~0.17nm/V.The voltageinduced phase shifts, ∆φ=2π∆λ/FSR for a 1 mm-phase-shifter MZM are shown in Fig.2(b).The modulation efficiency, V π L π , the applied voltage and length required to obtain ∆φ = π, was ~1.59 V•cm.The high-speed performance of the integrated modulator was characterized by measuring the 3dB bandwidth and eye-diagrams at high transmission rates.The electrical speed of the modulator using a reverse biased PN junction is limited by capacitance.The measured capacitance of the modulator is < 840 fF near −3 V DC .The predicted RC-limit −3dB bandwidth, f -3dB = 1/(2πRC), of the modulator was ~22 GHz.

Fig. 3 .
Fig. 3. Frequency response of the MZ modulator shows the −3 dB bandwidth (f-3dB) of 15.0 GHz at −5 VDC bias and 14.3 GHz at −2 VDC bias for the wavelength of 1539.5nm.

Fig. 5 .
Fig. 5. High-speed operations of an integrated 1 mm-phase-shifter MZM driven in differential mode of 1.2 Vpp for 20Gb/s and 30Gb/s modulations for λ~1541.2nm in the PICoff-chip.Measured ERs are 9.1 dB at −3VDC for 20Gb/s modulation, and 7.2 dB at −4 VDC for 30Gb/s modulation.

Figure 5
Figure 5 shows measured eye-diagrams of the integrated 1 mm-phase-shifter MZM of the PIC off-chip driven differentially with 1.2 V pp swing using 20 Gb/s and 30 Gb/s PRBS signal for λ~1541.2nm.As seen in the figure, the measured eye diagrams exhibit good eye openings up to 30 Gb/s operations.The measured ER is 9.1 dB at 20 Gb/s data transmission with −3 VDC bias, and 7.2 dB at 30 Gb/s data transmission with −4 VDC bias.
(a) shows the normalized frequency response of a Ge PD.As shown in the figure, the measured −3dB bandwidths are 23.5 GHz at −1V bias and 27 GHz at −3 V bias.Figures 7(b) and 7(c) exhibit good eye-diagrams of the Ge PD at 20 Gb/s and 30 Gb/s operation at −3V bias for λ~1550 nm.The measured responsivity was ~0.3 A/W.This value is lower than expected.The Ge PD on 220nm SOI showed lower responsivity than the measured ~1 A/W responsivity of the same PD integrated on 450nm SOI.This reflects that Ge SEG process on the over-etched thin top silicon in SOI can affect the quality of the Ge epilayer in the bottom region, and this is under investigation.This suggests room for further optimization of the SEG process on the thin top Si layer of a SOI in RPCVD.As are shown in the above, both integrated modulators and Ge photodetectors of the PIC off-chip have demonstrates 30 Gb/s operations in data transmitting and receiving separately.The modulators showed improved characteristics of high modulation depth at high-speed #156656 -$15.00USD Received 19 Oct 2011; revised 30 Nov 2011; accepted 8 Dec 2011; published 16 Dec 2011 (C) 2011 OSA operations with low-voltage driving voltages, and the integrated photodetectors exhibited high-speed performance with low dark current.

Fig. 8 .
Fig. 8.The detected photocurrent curves for the optical transmission spectra of a integrated modulator by the monolithically integrated PD in the PICintra-chip.The modulator is biased from 0V to −9V, and the PD is biased −3V.

Figure 8 (
Figure8(a) shows the measured photocurrent curves corresponding to the typical optical transmission spectra through an integrated 1 mm-phase-shifter MZM, detected by the monolithically integrated Ge PD in a PIC intra-chip chip.Here, the modulator was biased from 0V to −10V, and the detecting PD was biased at −1V.The measured FSR of the integrated modulator is ~5.6 nm in the figure.The black solid curve is the transmission spectrum through the unbiased modulator, and the violet solid curve is the measured photocurrent curve for the transmission spectrum through the modulator biased at −9 V, which shows the wavelength shift, ∆λ ~1.4 nm.The voltage-induced wavelength shift, ∆λ/∆V was measured to be ~0.157nm/V.Figure8(b) shows the voltage-induced phase shifts as a function of the modulator bias voltage.Although the same modulators as those used in the PIC off-chip were integrated, the modulation efficiency in the PIC intra-chip were measured to the larger value of V π L π ~1.78 V•cm.Figure9shows on-wafer measurements of optical eye diagrams in the PIC intra-chip , where on-chip data transmissions of 12.5 Gb/s up to 20 Gb/s occur from the integrated 1 mm-phaseshifter MZM to the monolithically integrated Ge PD at λ~1542.7 nm.The NRZ PRBS signal from the Anritsu PPG was applied to the MZM.Here, the modulator was driven with a 2.5 V pp signal at −5V DC bias and the PD was biased at −3V.This measured eye patterns were raw signals detected by the integrated Ge PD without any preamplifier ICs involved.

Fig. 10 .
Fig. 10.(a) Silicon EPIC on a test PCB, where a silicon PICintra-chip chip is hybrid-integrated with 0.13µm CMOS VLSI chips.Top chip is a CMOS modulator-driver IC, the middle chip is a silicon PICintra-chip chip, and the bottom chip is a TIA-LA CMOS IC chip.Test setup for hybrid silicon EPIC characterization is shown in the inset.(b) The measured electrical eye of CMOS ICs at 7 Gb/s and 10 Gb/s operations.(c) Eye diagrams of the hybrid silicon EPIC at 5 Gbps, 8 Gbps, and 10 Gbps measured with 1.3 Vpp PRBS signal.Here, on-chip EPIC characteristics are limited by the 0.13µm CMOS interface circuits.theresponsivity of the integrated PD with the use of a smaller MZ modulator with high modulation efficiency can reduce the burden of high input power and result in improved onchip transmission characteristics in the PIC intra-chip chip.