SPICE Modeling of Memcomputing Logic Gates

Memcomputing logic gates generalize the traditional Boolean logic gates for operation in the reverse direction. According to the literature, this functionality enables the efficient solution of computationally-intensive problems including factorization and NP-complete problems. To approach the deployment of memcomputing gates in hardware, this paper introduces SPICE models of memcomputing logic gates following their original definition. Using these models, we demonstrate the behavior of single gates as well as small self-organizing circuits. We also correct some inconsistencies in the prior literature. Importantly, the correct schematics of dynamic correction module is reported here for the first time. Our work makes memcomputing more accessible to those who are interested in this emerging computing technology.


Introduction
Digital memcomputers are an emerging class of unconventional computing systems developed to efficiently solve factorization and combinatorial optimization problems [1], [2].Fundamentally, these are complex dynamical systems with deterministic continuous dynamics whose phase space contains a fixed point attractor corresponding to the problem solution (or multiple attractors if several solutions are possible).According to Traversa and Di Ventra, when implemented in hardware, digital memcomputing machines offer a polynomial-time solution to factorization and NP-complete problems [1].Moreover, it has been argued that the dynamics of digital memcomputing machines (with solutions) is deterministic, non-chaotic, without periodic orbits [3], [4], and topologically robust against perturbations and noise [5], [6].If a solution exists, it is certain that it will be discovered.Otherwise, there is no equilibrium.In such cases, some or all of the gates will continually change in an effort to self-organize into the logically consistent state of the circuit.However, such a state does not exist in problems without a solution.
So far, the research on digital memcomputing has been substantially focused on software simulations of ordinary differential equations representing the circuit dynamics.A recent benchmark [7] indicates that the memcomputing solution for a specific class of difficult problems is characterized by an exponent similar to that found for other solvers (such as Toshiba simulated bifurcation machines [8] and Fujitsu digital annealers [9]).Further progress could be made if computing was implemented on the hardware.For more information on competitive computing approaches, we refer the interested reader to [7] and the references therein.
Three designs of memcomputing logic gates are available in the literature.The most complex is the original design [1] (Design I) that is presented in Fig. 1.According to Fig. 1, self-organizing AND, OR or XOR can be built using 12 memristive elements, 15 voltage-controlled voltage generators, and several resistors.Moreover, some auxiliary circuitry is required to ensure that the final states of these gates (operating in the continuous or analog domain) are binary.Bearden et al. [10] introduced a simplified design of selforganizing AND and OR (Design II) [10] in which each gate requires 5 memristive elements, 6 voltage generators and few resistors.In principle, the simplified gates can perform the same tasks as the original ones.A study shows that Design II gates can be built using physical memristive devices [14].In the third design (Design III), the gates are defined by a set of differential equations [15].In fact, Design III is a variation of analogSAT [16], [17].Recently, Design III calculations were implemented on an FPGA board [18].
The purpose of this work is to develop SPICE models of Design I self-organizing logic gates [1].During the last decade or so, the SPICE modeling of adaptive circuit elements (known as memrisitive, memcapacitive, and meminductive systems [11,12,19]) has become increasingly important and resulted in various SPICE models of deterministic memelements (see, for instance, [20][21][22][23][24][25][26][27][28]).A notable recent development is the simulation of probabilistic memristive devices in SPICE [29].SPICE is a general-purpose circuit simulation program [30], [31].In SPICE, the circuit can be built graphically and then numerically simulated using predefined or user-defined models of individual circuit components.Such user-defined models of Design I self-organizing logic gates [1] are formulated in this paper.In this work, we used LTSpice XVII (Analog Devices) as a simulation tool.Our SPICE models may need minor adjustments to be used on other SPICE simulators (e.g., PSPICE, Ngspice).

SO UNIVERSAL GATE
The paper is organized as follows.We start with the introduction of Design I self-organizing logic gates (Sec.2) that is followed by a presentation of their SPICE models (Sec.3).In Sec. 4, we give examples of SPICE simulations of individual gates and circuits thereof.Section 5 concludes the paper.Complete listings of LTspice codes are given in Appendix C.

Self-Organizing Gates and Circuits
Self-organizing logic gates generalize traditional logic gates for operation in the reverse direction [1], [2].In these gates, each terminal serves the double function of input and output.Although self-organizing gates operate in analog mode, the auxiliary circuitry (voltage-controlled differential current generators presented below) and the gate design ensure that the final states are binary.In what follows, Boolean 1 and 0 are represented by  c = 1 V and − c = −1 V voltage levels, respectively.
The logic behind the construction of self-organizing gates can be partially captured from the following excerpt from [1]: "if the gate is connected to a network and the gate configuration is correct, no current flows from any terminal (the gate is in stable equilibrium).Otherwise, a current of the order of  c / on flows with the sign opposite to the sign of the voltage at the terminal."Below, this property of selforganizing gates is used to demonstrate that the polarity of the memristive elements in Fig. 1 circuit must be reversed for the correct gate operation.
Transformation of traditional Boolean logic circuits into Design I self-organizing logic circuits [1] involves the following steps: • Replacing the traditional logic gates with selforganizing gates of the same type.
• Representing the external input signals by constantvalue voltage sources.
• Adding auxiliary circuitry: A voltage-controlled differential current generator (VCDCG) is added to each node, but not to the nodes that are used for input signals.
By node, we mean either the point of connection of two or more gate terminals or an unconnected gate terminal.
• External input signals are applied at the initial moment of time and stay constant over time.The end of dynamics indicates that a solution is found and can be read.The infinite dynamics implies the absence of a solution.
For the sake of completeness, we next provide the minimal description of the circuit components in the Design I self-organizing logic circuits that is required for their implementation in SPICE.These definitions were extracted from [1,2,32].

Voltage-Controlled Voltage Generators
Consider the structure of the universal self-organizing gate shown in Fig. 1.Its ultimate functionality (e.g., selforganizing AND, OR, or XOR) is defined by the equations that govern voltage-controlled voltage generators (VCVGs)   1 −   4 and   .According to [1], the voltage across VCVG is a linear function of the gate voltages where  1 ,  2 , and  0 are the gate voltages, and  1 ,  2 ,  0 , and  are the constants.For convenience, these constants are specified in Tab.A1 (Appendix A).

Memristive Elements
Having defined the voltage-controlled voltage generators, next we consider the memristive elements  in Fig. 1.The response of the memristive system  is described by Ohm's law where    is the voltage (defined with respect to the thick-bar terminal of the circuit symbol of ),    is the current, is the state-dependent resistance (memristance),   ∈ [0, 1] is the internal state variable [11],  on and  off are the on-and off-state resistances.
The dynamics of   follows the ordinary differential equation: where  is the constant and the function ℎ(,   ) influences the dynamics of the internal state.While many choices for ℎ(,   ) are available, following [1], we use where  (. . . ) is the unit step function.According to (4) and (5),   decreases down to   = 0 at positive voltages.At negative voltages,   increases to   = 1.It is not difficult to recognize that (2), (4), and (5) correspond to the ideal memristor model [33].The limitations of this model are well known [19].Note that Table A2 (Appendix A) lists the values of parameters used in the prior simulations [1].Equation ( 5) corresponds to   = 0 and  = ∞.For definition of   and , see [1].
Moreover, a parasitic device capacitance is taken into account using a constant-value capacitor of capacitance  connected in parallel to every memristive element.These capacitors are not shown in Fig. 1 explicitly but taken into account in the model.

Voltage-Controlled Differential Current Generators
Finally, we introduce equations describing voltagecontrolled differential current generators.These generators are second-order dynamical systems whose evolution follows [1], [32]: Here,  is the constant,  DCG,  is the voltage at the node that VCDCG is connected to,  DCG,  is the current, i DCG is the vector of the currents of all VCDCGs, and   is the second state variable.Note that the above equation corresponds to  = 0 in Tab.A2 (Appendix A).For the definition of , see [1].Our specific realization of  DCG () in ( 6) is based on arc tangent functions (one of the suggested realizations of  DCG () [1]).Specifically, we use where ,  0 ,  1 , and  c are the constants.Equation ( 8) is illustrated in Fig. 2(a).
Importantly, unlike [1], [32] we use the minus sign in front of the   term in (9).The minus sign is required to implement the following anticipated purpose of   -s: the reset of all | DCG,  | to below  min as soon as at least one of | DCG,  | exceeds  max .Equation ( 9) is illustrated in Fig. 2(b).Figure 2(b) (left panel) shows that when the absolute value of all currents is less than  min , the function   i DCG ,   has a single zero at  > 1, which is a stable fixed point of (7).When the absolute value of at least one  DCG,  is larger than  max , the stable fixed point is located at  < 0, see Fig. 2(c) (right panel).In the intermediate case, there are two stable fixed points and one unstable fixed point (Fig. 2(b) (middle panel)).Therefore, when the absolute value of one of the currents exceeds  max , all variables   -which are described by identical equations -start drifting toward the negative stable fixed point, causing the relaxation of VCDCG currents (through the last term in ( 6)).The normal response of VCDCGs (due to the first term ino.( 6)) is restored later, after the condition | DCG,  | <  min for all  is satisfied.

Basic Details
Our SPICE models are based on the parameters' values from [1] (Tab.A2, Appendix A) with the assumption that these values are given in the SI units.An issue is that the small resistances lead to large currents (of the order of amperes) and some other parameters lead to slow dynamics (on the scale of seconds).In particular, the on-and off-state resistances,  on = 0.01 Ω and  off = 1 Ω, are much smaller than the on-and off-state resistances in experimental devices that typically range from kiloohms to megaohms.In our LTspice models, we have introduced two scaling factors,   and   .These factors are used to rescale the currents and time in typical ranges for electronics.For consistency, the same values of   and   must be utilized in all LTspice models (Appendix C).The results reported here were obtained using   = 10 5 and   = 10 3 .
Appendix C contains LTspice models of self-organizing AND, OR, and XOR, memristive elements, and voltagecontrolled differential current generators (Listings C1-C5).These models were formulated following the common practices in SPICE modeling [22].For example, to integrate the differential equations ( 4), (6), and ( 7), we use capacitors that are charged or discharged with voltagecontrolled current sources representing the right-hand sides of these equations, etc.
Figure 3 shows the current-voltage curves for the memristive element.To obtain these curves, we used the SPICE model from Listing C4.According to Fig. 3, the memristance decreases at   > 0 and increases at   < 0. The frequency dependence of the current-voltage curves in Fig. 3 is typical for memristive systems [11], [12].V o l t a g e ( V ) We have found that the polarity of the memristive elements in Fig. 1 is incorrect.To understand this, one can evaluate the total terminal current in a gate terminal assuming a logically consistent state.As we have mentioned above, in this case, the total terminal current must be zero (see the second paragraph in Sec.2.1).For example, a simple calculation shows that the current at terminal 1 of AND at and the voltage across  1 in Fig. 1 circuit is +2 V.As positive voltages drive  1 into  on ,  1 = 2/ on −2/ off > 0. Thus, to satisfy  1 = 0, the polarity of  1 must be reversed.
As all variables   are described by the same Equation (7), we represent these variables by a single variable  ≡   for all .In SPICE, we have defined an s-block as the component that integrates (7) (see the second model in Listing C5 and Fig. B1 in Appendix B).The s-block has 8 voltage inputs for the voltage signals encoding  DCD,  -s and a single output, which is .The output of s-block must be connected to all VCDCGs (to terminals 4).The inputs of the s-block are taken from terminals 3 of the VCDCGs.The SPICE model of the s-block in Listing C5 can be directly used with up to 8 VCDCGs in the circuit and can be easily expanded to a larger number of VCDCGs.

Important Implementation Notes
1.The correct version of Design I self-organizing gates involves two resistors (Fig. 1, left).In [2], it is shown without resistors.In [32], it is presented with memristors instead of resistors.
5. Memristive elements subjected to zero voltage and associated voltage sources have not been included in the models of AND and OR (e.g.,   2 and   4 and associated memristive elements in the DCM of terminal 1 of AND).
6.All   -s are implemented using a single variable .

7.
To suppress high voltage spikes1 and improve the convergence, we have increased  on to 0.05, decreased  max to 10, and added a capacitor in each VCDCG (C1 in Listing C5).
8. To enable the random initial states of memristive elements, the option "Use the clock to reseed the MC generator" must be checked in LTSpice XVII.The transient analysis was performed using the option uic.
9. For reproducibility of our results, the initial states of the memristive elements are chosen from a flat random distribution between 0.18 and 0.22.All other initial values are selected deterministically.

Single Gates
This subsection exemplifies the behavior of selforganizing gates using the OR gate as an example.First, we consider the traditional (direct) operation, wherein the voltage signals are applied to the traditional inputs of the gate.Second, we explore the reverse operation (not available with the usual OR).1In the circuit based on original parameters, spikes can be of quite extreme magnitude (e.g., several hundred thousand volts).These spikes have been associated with instantons, see [2].

LR
Figure 5(a) shows the simulated circuit for the direct operation of the self-organizing OR.In this circuit, the input signals are applied using pulsed voltage sources connected to terminals 1 and 2 of U1.The output terminal of U1 (not connected to any voltage source) is driven by a VCDCG (see the circuit transformation rules in Sec. 2). Figure 5(b) shows the gate response.Clearly, except for short transients, the gate reproduces the truth table of OR.In Fig. 5(b), the curve  VCDCG represents the current in VCDCG U2 (without accounting for the current of C1).We note that this current fluctuates at about zero.
Next, consider the reverse operation of the selforganizing OR. Figure 6(a) and (b) show two slightly different circuits used in our simulations.The difference is that in Fig. 6(a) we use two terminals (terminals 2 and ) as input and one terminal (1) as output, while in Fig. 6(b) there is a single input terminal () and two output terminals (1 and 2).As before, we use VCDCGs to ensure binary states at the output terminals.
Figure 6(c) shows the gate voltages for the circuit in Fig. 6(a).In this presented realization of circuit dynamics, after a transient, the voltage at the first terminal,  1 (), becomes equal to −1 V.When   = 1 V, the truth table of OR is satisfied.In the opposite case, the gate shows a reasonable behavior as it chooses  1 = −1 V over  1 = 1 V deterministically.In some other runs, instead of  1 () = −1 V, the voltage at terminal 1, after a short transient, repeated the applied voltage   ().In this case, again, the truth table of OR is satisfied whenever   () = 1 V.
Finally, consider the response of the self-organizing OR in Fig. 6(b).Using a flat random distribution of initial states of memristive elements from 0 to 1, in each run we observed one of the following general responses: (i)  1 () =  2 () =   () (as in Fig. 6 Clearly, all of these cases are consistent with the truth table of the OR. Overall, we conclude that the self-organizing OR correctly reproduces the truth table of OR (whenever possible) regardless of the role of each terminal as input or output.The response may be different in different runs (but always correct).We have verified that the same is true for selforganizing AND and XOR.

Circuits of Self-Organizing Gates
As an example of a circuit of self-organizing gates, consider a self-organizing 2-bit by 2-bit multiplier.Its schematics is presented in Fig. 7(a).The self-organizing multiplier involves eight self-organizing gates and eight voltage-controlled differential current generators.This circuit was designed based on the conventional 2-bit by 2bit binary multiplier using the circuit transformation rules outlined in Sec. 2.
The circuit in Fig. 7(a) uses four constant voltage sources V3-V6 to encode the number to factorize (it is 6 in Fig. 7(a)).We emphasize that the signals P0-P3 serve as the input.The output signals are A0, A1, B0, and B1, which are the bits of two factors (A0 and B0 are the least significant bits).These factors are found through the deterministic dynamics of the self-organizing multiplier.
Examples of circuit dynamics are demonstrated in Figs.7(b)-(f).In particular, Figs.7(b) and (c) show that the result may be different in different runs.Specifically, these graphs indicate that number 2 can be presented as 2 • 1 or 1 • 2. This ability to identify different solutions is related to the random choice of initial states of memristive elements.Two distinct solutions are observed when two sets of initial states belong to different basins of attraction.
Figures 7(e) and (f) indicate that the factorization of some numbers can be more difficult than others (using some close initial conditions).In our simulations of the selforganizing multiplier, the most difficult was the factorization of 1.In this case, most frequently, we have observed the transition to a limit cycle behavior as the one in Fig. 7(f) and quite occasionally the correct solution to the problem (1 = 1 • 1).
We have verified that the existence of the limit cycle (Fig. 7(f)) is not related to certain modifications to the parameters that we made.In particular, the limit cycle was observed in the circuit without C1 (in the VCDCG model) and with prior values of  on , , and  max (from Tab.A2).In a longer simulation, it was observed that the limit cycle continues up to 100 s.To ensure that the limit cycle is not a numerical artifact, we performed some additional simulations.The use of other numerical integration methods in LTspice (trapezoid and modified trap in addition to Gear)2, variation of tolerances, noise addition, and the use of PSPICE result in the same limit cycle behavior.
The existence of the limit cycle in the numerical dynamics seems to contradict the statement "if the Boolean problem the DMMs are designed to solve has a solution, the system will always find it, irrespective of the initial conditions" in [4] (see also [1]) for the continuous dynamics.Currently, the exact reason for this is not known, and its determination is beyond the scope of this work.

Conclusion
Having identified and corrected some inconsistencies in the prior literature [1,2,32] (see Items 1-4 in Sec.3.2), we have formulated SPICE models of the Design I self-organizing logic gates.The operation of individual self-organizing gates and small circuits thereof has been demonstrated.
T i m e ( m s )    We emphasize that in future studies of these gates, special attention should be paid among others to: • Polarity of memristive devices in DCMs.
• Use of resistors in the schematics of the universal gate.
• Sign of the   term in the function   i DCG ,   .
• Values for parameters   and   .
In summary, self-organizing logic gates are an interesting generalization of the traditional Boolean logic gates.The SPICE models reported in this paper offer an easy and pretty reliable way to explore self-organization in memcomputing circuits.Experimental demonstration of self-organizing gates is an interesting project for the future.

Fig. 1 .
Fig. 1.Left panel: the universal self-organizing logic gate is composed of three dynamic correction modules (DCMs) and two resistors.Right panel: internal structure of the dynamic correction module (incorrect).Here, the resistive memories  [11-13] have minimum and maximum resistances  on and  off , respectively, and the resistance of the resistors is  =  off .   -s and   are voltage-controlled voltage generators.As we explain in the text, in the right panel, the polarity of all memristive elements must be reversed.Reprinted from [1], with the permission of AIP Publishing.
r e n t ( m A )

Fig. 3 .
Fig. 3. Current-voltage curves of the memristive element subjected to a sinusoidal voltage.These curves were obtained using the SPICE model in Lst.C4 (Appendix C).

Fig. 5 .
Fig. 5. Direct operation of self-organizing OR.(a) Circuit used in the simulations.Here, V1 and V2 are the pulsed voltage sources, U1 is the self-organizing OR (for the LTspice code, see Listing C3), U2 is the VCDCG (for the LTspice code, see Listing C5), and U18 is the s-block (see Listing C5 and Fig. B1 in Appendix B).The s-block implements (7) and (9).(b) Transient voltage signals at the terminals of the self-organizing OR and VCDCG voltage output (terminal 3 of U2).The curves were displaced for the sake of clarity.

Fig. 6 .
Fig. 6.Reverse operation of self-organizing OR. (a), (b) Circuits used in simulations.Here, V4 and V14 are pulsed voltage sources and V1 is the 1 V constant voltage source.(c) Example of voltage transient signals at the terminals of the self-organizing OR in (a).(d) Example of transient voltage signals at the terminals of the self-organizing OR in (b).

FFFF a c t o r i z a t i o n o f 1 sFig. 7 .
Fig. 7. Solving integer factorization problem with a self-organizing 2-bit by 2-bit multiplier.(a) Circuit used in the simulations.Here, the number to factorize is represented by (P3,P2,P1,P0), and the factors -by (A1,A0) and (B1,B0).(b)-(f) Examples of the transient dynamics of the self-organizing 2-bit by 2-bit multiplier.Curve  in (f) was shifted down by 2 V for clarity.

0
Tab. A1.Parameters of voltage-controlled voltage generators for AND, OR, and XOR gates.