Low Voltage High Performance CMOS Current Mode Four-Quadrant Analog Multiplier Circuit

. This paper describes a new CMOS current-mode four-quadrant analog multiplier circuit. The proposed design is based on a high performance squarer cell, whose main core is realized by the up–down topology trans-linear loop using flipped voltage followers (FVF). The simulation results are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 µm CMOS process available from level 49 MOSIS at 25°C with ±0.75 V supply voltage. The proposed multiplier offers improved characteristics compared to the multipliers previously exposed in the literature. It has a wide dynamic range. The total harmonic distortion is about 0.42% at 100 kHz with peak-to-peak input current of 40 µA. The − 3 dB bandwidth is more than 850 MHz and maximum power consumption is of approximately 105 µW.


Introduction
Signal processing circuits are present in all the equipment used in our life, such as telecommunications, television, transport or medical equipment [1][2][3][4]. The analog approach of these circuits is highly recommended in the manufacturing sector due to their low power and highspeed operation, allowing real-time signal processing.
Analog multiplier circuit is a block widely used in analog signal processing systems, for example in adaptive filters, modulators, automatic gain control, image processing, artificial neural networks, fuzzy integrated systems , squaring and square rooting of signals [5][6][7][8]. It usually has two input ports and one output port. Under ideal conditions, the output of this circuit Z is defined as the linear product of two input signals X and Y, which translates to Z = K X Y, where K is a constant with an appropriate dimension [9]. Current mode multipliers have received considerable attention due to their good characteristics of dynamic range, accuracy, bandwidth, power consumption [10][11][12]. For this reason, many researches have been carried out with the aim of improving their performance using different techniques. The first group of circuits was made based on the trans-linear principle (TL) using loop transistors operating either in weak inversion [13], [14] or in strong inversion [15], [16]. The second group deals with the structure based on active circuits such as Current Conveyor (CC) [17][18][19], Operational Amplifier (OA) [20], Operational Trans-conductance Amplifier (OTA) [5], [21] and voltage differencing gain amplifier (VDGA) [22]. This paper presents a new CMOS current-mode fourquadrant multiplier circuit. It is implemented by using two squarer circuits. The circuit is simulated using TSPICE simulator by level 49 parameters (BSIM3v3) in 0.18 μm standard CMOS technology with ± 0.75 V supply voltage. The simulation results present ± 20 µA dynamic range with THD less than 0.8% at 1 MHz, 850 MHz bandwidth and a maximum power consumption about 0.105 mW.

Proposed Current Mode Squarer Circuit
The proposed CMOS current-mode squarer circuit is shown in Fig. 1 where V GS is the gate-source voltage, V DD is the positive voltage supply, V SS is the negative voltage supply and V TH is the threshold voltage of transistor. Since all transistors operate in the saturation region V DS ≥ V GS -V TH , the drain-source current equation can be expressed as: where k n = μ n0 C ox W/L is the trans-conductance parameter, C ox is the oxide gate capacitance in unit area, μ n0 is the low field mobility, W/L is the ratio of width to length and θ is the mobility attenuation factor.
If the mobility attenuation factor is not taken into account, the drain-source current expression of transistor becomes: From (3), the gate-source voltage V GS expression can be written as: Applying Kirchhoff's voltage law (KVL), the relationship between the gate-source voltages of translinear loop is given by: Assuming that all transistors have the same transconductance value, the following expression is given using (4) and ( By taking the square from both sides of (9), we get: By squaring (10), the output current of the squarer circuit is given by: On the other hand, if the mobility attenuation factor is taken into account, the gate-source voltage expression of transistor is given by: Knowing that the mobility attenuation factor is low, such θ 2 /k n 2 I 2 DS << 2/k n I DS , the gate-source voltage expression has become: Assuming that all transistors have the same transconductance value and the same mobility attenuation factor θ, equation (14) is given using (13) and (5). .
Knowing that the drain-source currents of transistors M1 and M2 are equal to the bias current I B and by using (7) and (8) By taking the square twice on both sides of (15), we get: By comparing (11) and (16)

Proposed Multiplier Circuit
The working principle of a current mode fourquadrant multiplier circuit based on the squared difference identity is given by: Based on (17), the block diagram of the multiplier circuit can be realized by two squarer circuits, a current subtractor and a current adder, as presented in Fig. 2.
The summation and subtraction of input current signals I X + I Y and I X -I Y respectively are made using an additional input stage composed of simple current mirrors as shown in Fig. 3.
The proposed current mode multiplier circuit is shown in Fig. 4. It consists of two squarer circuits composed by two up-down topology trans-linear loops formed by M1-M4 and M18-M21. Assuming that the input currents are respectively (I X + I Y ) and (I X -I Y ), the output current of two squarer circuits are given by: The output current of the second squarer circuit is reversed by the current inverter circuit consisting of transistors M26, M33, M34, M35, M36 and M37.
The output current of multiplier circuit can be written as:

Mismatch Analysis
In this section, the mismatch analyzes for the proposed multiplier circuit are performed. It includes the input current mismatch, the mobility parameter mismatch and the trans-conductance parameter mismatch of transistors.

Input Current Mismatch
The proposed multiplier circuit requires two wellmatched input signals I X and I Y . It is reported that the mismatch in the input signals leads to a second harmonic distortion condition at the output of the multiplier circuit.
All input currents can be defined as follows in terms of possible mismatches (i = 1, 2): The mean values of input currents are Î X and Î Y . The mismatch percentages of Î Xi and Î Yi are Δ Xi and Δ Yi , respectively.
By considering Δ 2 Xi , Δ 2 Yi and Δ Xi Δ Yi less than 1, the output currents of squarer circuits are given by: The output current of multiplier circuit can be written as: In (25), if one of the inputs Î X is assumed constant and the other is sinusoidal in the form of Î Y = î m sin(ωt), the second harmonic distortion from the input signal offsets can be calculated as follows: According to (26), it should be noted that the mismatch ratio increases and the second harmonic distortion also increases.
However, it remains roughly stable and does not significantly change the distortion of the third harmonic, as it does not show up in manual calculations.

Mobility Parameter Mismatch
If we assumed that the mobility parameter of the proposed multiplier circuit is not perfectly adapted, the output currents of the squarer circuits can be written as: The output current of the proposed multiplier circuit can be written as: Using (27), (28) and (29), the output current is given by: The absolute error is given by: We can see from (31) that the proposed multiplier is insensitive to mismatch in carrier mobility parameter.

Transconductance Parameter Mismatch
If we assume that the transconductance parameter of the transistor does not fully match, the output currents of the squarer circuits can be written: n n 2 4 n n 2 4 Combining (29), (32), and (33), we get: The absolute error is given by This means that the proposed circuit is insensitive to mismatch in trans-conductance parameter.

Simulation Results
The simulation results of the proposed circuits are verified using Tanner TSPICE simulator with 0.18 μm CMOS parameter technology under a supply voltage of ±0.75 V and a bias current I B of 10 µA. The aspect ratios of the transistors are shown in Tab. 1.  The DC transfer characteristic of the proposed fourquadrant analog multiplier is shown in Fig. 7. The input current I X varied between -20 μA to 20 μA, when the current I Y has the same disparity from -20 μA to 20 μA with step size 4 μA. The application of multiplier used as a modulator is shown in Fig. 8. The input current signals I X and I Y are set to 1 MHz and 100 kHz with peak-to-peak amplitude of 10 μA and 5 µA, respectively. The variations of total harmonic distortion (THD) with respect to the peak-to-peak amplitude of the input signal I X when I Y amplitude equal to 10 μA at 100 kHz and 1 MHz are shown in Fig. 9. In the worst case, when Ix is equal to 40 μA peak-to-peak amplitude at 1 MHz, the total harmonic distortion is obtained 0.8%.
The variation of temperature as a function of relative error is shown in Fig. 10. The simulation results are obtained using a transient signal input current I X , with an amplitude of 10 µA and a frequency of 1 MHz, and a constant current I Y equal to 10 µA. The maximum error is reported at 75°C as 1.18 %. The output at 25°C is considered as the ideal value with zero relative error, so that the outputs obtained at other temperatures are calculated based on the reference value.
The frequency response of the multiplier is checked using an AC input current I X with an amplitude equal to 10 µA and a constant current I Y equal to 10 µA. The simulation result obtained is shown in Fig. 11, where the low frequency gain is -120 and the bandwidth obtained is 850 MHz. The power consumption of the circuit is 105 µW.
Monte Carlo analysis is performed for 100 samples by applying a ±5% Gaussian distribution for temperature effect to analyze bandwidth and gain variations, as shown in Fig. 12. These simulations are performed using an AC Total harmonic distortion THD (%) Input current IX P-P (µA) IY @ 1MHz IY @ 100 kHz The proposed multiplier is compared to recently published work as presented in Tab. 2. Simulation results from the proposed multiplier indicate better performance in terms of supply voltage, bandwidth, high accuracy and power consumption.

Conclusion
This work presents a new CMOS current mode analog four-quadrant multiplier. The proposed circuit is designed by using two low voltage squarer circuits based on the up-down topology trans-linear loop and the flipped voltage followers (FVF).
The simulation results have verified by TSPICE using TSMC 0.18 µm CMOS process available from MOSIS at 25°C with 0.75 V supply voltage. The circuit is characterized by a low power consumption 105 µW, a wide bandwidth about 850 MHz and a low nonlinearity error of 0.85%.