A Self-Start-Up Sub-Threshold DC/DC Boost Converter Using Bootstrap Driver for Self-Powered Sensor Nodes

In this paper, a fully autonomous and integrated sub-threshold DC-DC converter is presented for energy harvesting from ambient sources to self-powered IoT nodes. The proposed converter and its clock generator are designed by exploiting body biasing technique for low power operation and operate in sub-threshold regime. This bulk driven technique can dynamically enhance the on-current during conducting state and decrease reverse current during the non-conducting state. A bootstrap driver with dynamic body bias is employed to drive the phase generator at the output of the ring oscillator to decrease the settling time of the charge pump. This further improves the driving capacity of the clock along with extended rail to rail output voltage swing. Also, a novel cross clock scheme is proposed to improve the output voltage’s transient response and conversion efficiency of a converter by reducing reverse current loss. The proposed circuit is implemented in CMOS 0.18 μm process. The proposed design requires very low start-up voltage of 400 mV and exhibits output voltage of 1.98 V, settling time of 33 μs, and pumping efficiency of 99% with a total power dissipation limited to just 1.5 μW.


Introduction
Nowadays, a large number of wireless sensor nodes (WSNs) are connected in a network to realize smart systems such as the Internet of things (IoT), smart homes, and intelligent grid. However, due to their widespread and existence in large number, these systems require low maintenance, low area, and seamless operation without replacement of the battery. Micro energy harvesting has been recently emerging as a promising solution to power up such systems [1]. However, the harvester's output voltage is a few hundred mill volts (e.g., the output voltage of an amorphous single photovoltaic cell is between 0.3 V and 0.6 V) [2]. Usually, such low voltage is not sufficient enough to power these circuits. Consequently, a power management unit (PMU) with the DC-DC boost converter is strongly required to raise the voltage level proportionate to the desired voltage level. The DC-DC converter in self-powered devices needs operating voltage higher than the MOS device's threshold voltage to achieve high conversion efficiency. Several start-up mechanisms have been implemented in the literature to trigger the converter in such a low voltage range. The boost converter in [3] recharges the auxiliary battery for one time. The converter in [4] employs a mechanical vibrator that is triggered by kinetic energy (KE) in motion to power up the portable IoT node. The work in [5] uses a transformer-based start-up circuit, which requires a very large turning ratio. Post-fabrication threshold voltage tuning is developed in [6] to enable the low voltage operation. However, all these start-up mechanisms utilize external excitation.
Self-start-up on-chip DC-DC converters realized with inductors have also been investigated [7]. A combination of low threshold voltage MOSFETs and switched inductor used in [8] was designed to operate in the low input voltage range. However, it suffers from low-quality factor integration, high cost, and inefficient chip usage. On the other side, integrated inductor less dc/dc converters also referred to as a charge pump (CP), can provide the best integration solution to make compact self-powered IoT devices. The first fully integrated inductor less DC-DC converter was developed by Dickson in 1976 [9]. It was simply implemented with chain of NMOS diode-connected MOSFETs that operate in cut-off or saturation region. The steady-state output voltage of the NMOS diode-connected MOSFET CP can be defined as: where V IN is the supply voltage, V th is the threshold voltage, is the number of stages, p is the ratio of pumping capacitance ( k ) to top parasitic capacitance, and ϕ is the clock amplitude. From the above equation, it can be seen that k , ϕ , and th limit the voltage gain and efficiency. Thereafter, to improve the efficiency and voltage gain in [9], many control techniques have been investigated [10]. Although charge transfer switches (CTSs) are turned off, non-negligible reverse saturation current flows through the CTSs, which degrades conversion efficiency. A linear charge pump (LCP) with improved conversion efficiency using a gate-controlled switch technique was presented in [11]. However, CTSs in LCP cannot be completely turned on/off when the supply voltage is lower than the MOSFET's threshold voltage. A latched CP (also referred to as cross-coupled charge pump) using a simple two-phase complementary scheme was presented in [12] and same was introduced in [13]. This two branch structure using latch configuration generates the differential doubled output voltage with the near-zero voltage drop across each CTS. Also, this structure reduces the ripple voltage and improves efficiency. Successively, the works in [14] improve the conversion efficiency using hybrid structure. The stage, which is connected to supply, employs three latched cells connected in parallel so that the power extraction can be done optimally from power sources. The next stage, which is connected to load, works typically as a conventional charge pump to boost the pumping efficiency at the target level. Incompetent with prior works, latched CPs have several advantages. However, they do not work well for low voltage applications. To make IoT devices operate at low voltages, some interesting solutions have been provided in the literature. The converter presented in [3] can operate with low supply voltage using Carbon Nano-tube FETs (i.e., CNFETs) that offer devices with a low threshold voltage. Another high efficiency switched converter in [15], which offers low threshold voltage, was implemented in 65nm node. On the other side, to make them less dependent on the threshold voltage of the MOS device in various charge pump topologies, bulk biasing techniques [15] using proper bias of the MOSFETs' well (i.e., p-well for NMOS and n-well for PMOS in the triple-well process) are used. One of the high-performance latch based CPs was proposed in [16] where gates and bulks dynamically adjust the bulk voltage to enable the circuit operates at minimum operating voltages. However, the requirement of an extra complex circuit at the last stage of CP is a major drawback of it. The forward body biasing for latch based CP was proposed in [17]. In this method, all MOSFETs are forward biased, thus resulting in higher on-current. In this biasing scheme, the enhanced on-current is higher than bulk leakage current that allows the low voltage operation of the CP. Nevertheless, the high inverse saturation current through NMOS transistor during the non-conducting phase of switches decreases the end-to-end conversion efficiency of the CP.
This work aims to implement a simple self start-up low voltage DC-DC boost converter with compact size, high conversion efficiency, and low settling time.The proposed converter and its clock generator, which operate in sub-threshold, are designed by expoliting body biasing technique using auxiliary transistor for low power operation with no external start-up circuit. This bulk driven technique can dynamically enhance the on-current in conducting state and decrease reverse current in the non-conducting state.Working in low supply voltage has a benefit of low power dissipation, but CPs suffer from poor conversion efficiency due to reverse current loss.To address this issue, a novel cross clock scheme is proposed to improve the output voltage's transient response and conversion efficiency of a converter by reducing reverse current loss. Also, a bootstrap driver with dynamic body bias is employed to drive the phase generator at the output of the ring oscillator in order to decrease the settling time of the charge pump. This further improves the driving capacity of the clock along with extended rail to rail output voltage swing. The remainder of this paper's workflow is as follows: Section 2 presents the implementation of the proposed DC-DC booster converter. Section 3 discusses the functionality of the implemented prototype, which is validated using postlayout simulations. Finally, the conclusion is given in Sec. 4.

Four Stage Latched Charge Pump
The basic block diagram of the DC-DC boost converter and the proposed DC-DC boost converter using bootstrap driver are depicted in Fig. 1. A latch based charge pump is exploited in the proposed boost converter to achieve low ripple voltage and better charge transferability than preceded charge pump topologies [9][10][11]. Nevertheless, to improve the performance metrics of the latched CP in the low voltage range, a few modifications are essential; one of the possible solutions to allow the CP for low voltage operation is bulk biasing technique. So, a latched CP using body biasing with auxiliary transistor technique is designed to implement the proposed self-start-up DC-DC boost converter, as depicted in Fig. 2. As shown in Fig. 2, body biasing, which effectively turns on/off CTSs in the sub-threshold regime, is applied to both PMOS CTS and NMOS CTS in CP. As a result, the sub leakage current decreases and transient characteristics of CTS are improved. And also, to achieve high conversion efficiency with a low input voltage, a dc/dc boost converter with high conversion ratio is needed; however, a large pumping capacitance in circuit is also required. Thus, the proposed converter can provide high conversion ratio with small pumping capacitance.
On the other side, the undesired charge flows between the input node and output of CP due to improper timing clock transitions by switching clocks, so the end to end efficiency deteriorates significantly. To address this problem up to some extent, non-overlapping clocks can be used in dual-phase clock scheme circuit, but the undesired charge still exists in this case as well, and also generating perfect non-overlapping clocks is not possible in reality. Successively, several control schemes using an auxiliary circuit for CTSs were developed in [18]. In this paper, without using any auxiliary circuit and non-overlapping clocks, a novel cross clock scheme is proposed to improve the output voltage's transient response and conversion efficiency. CLK and CLKB, which are two cross clocks generated from the clock generator, have amplitudes that are same as the amplitude of the supply voltage.  The operation of the first stage is as follows. When the clock signal CLK is low, and CLKB is high, voltages at nodes and are IN and 2 IN , respectively, so 2−CP , 2 , 1−CP , 1 are turned ON and charge transfers consequently from the input node to node . Also, applied body biasing technique improves the conductance of N 2−CP and P 1−CP while ensuring proper forward biasing of substrate junction diodes even for low input voltages, thus resulting in high oncurrent. On the other hand, charge transfer switches (i.e., 1−CP and 2−CP ) and their respective auxiliary transistors are turned off so that reverse current is prevented at the later stages. Hence, the output of the first stage, when the clock signal CLK is low and CLKB is high, is 2 IN in the first half cycle. During the other half cycle, voltages at nodes and are 2 IN and IN , respectively, so 1 , 1−CP , 2−CP , 2 are turned ON, and charge transfer switches 2−CP , 1−CP are turned OFF. Consequently, the output voltage of the first stage is 2 IN in the second half cycle. Therefore, the output voltage always remains as 2 IN during the complete full cycle. The same operation is applicable to the next stages of the charge pump. Sizing of the charge transfer switch is discussed in the next section.

Sizing of CTS
Body of the CTSs (i.e., 2−CP and 2−CP ) in Fig. 3 are biased by single transistor at each CTS. As CLK is high, and CLKBis low, 2−CP turned on, and the node voltage of 'g' is charged to a higher level. 2 are also turn on during this time interval which shorts the , , 2 . The relation among the , , 2 is given by On the other hand, 2−CP , 2 are turned off when CLK is low, and CLKB is high. 2 is mainly determined by the capacitance model of 2−CP , 2 that can be expressed as where sb , gb , db are 2−CP 's source-body, gate-body, drain-body capacitance, respectively, while gb( 2 ) is gatebody capacitance of 2 , db( 2 ) is drain-body capacitance of 2 . Source-body capacitance of 2 is ignored because of source and body shorted and T is s + gb , s is stray capacitances inculding the 2−CP , 2 's substrate capacitance. As 2−CP is turned on then V < ≤ and consider sb( 2−CP ) + db ( 2 ) is negliable compared to C T , then (3) can be simplified as We get V 2 in (6) gb( 2−CP ) is much larger than db( 2 ) , s , sb( 2−CP ) . As a result, we can << 1 by choosing the moderate size of 2 , 10% of 2−CP is acceptable such that these capacitors have smallest values. And the relation among the , , 2 when CLK is low, and CLKB is high are expressed in (7) From (2) and (7), it can conclude that 2 follows closely to the lower one between and which makes sure that the bulk-source and bulk-drain PN junction is not turned on and suppress the junction leakage current. Moreover, when 2−CP is turn-on in CLK is high, and CLKB is low, 2−CP 's body and the source are short, which prevents 2−CP from body effect. And analysis of charge transfer switch 2−CP is analogous to NMOS-CTS. Figure 1(b) shows the block diagram of the proposed dual-phase clock generator that can generate cross couple clocks with 50% duty cycle. It consists of a five-stage stack ring oscillator, followed by the bootstrap driver, phase generator, and buffers. The clock generator circuits, which were proposed for low voltage applications in the literature [19], pose several challenges. While implementing a clock generator for low voltage (LV) applications, one of the primary challenges is to design ring oscillator that can produce out of phase-clocks with well-output current driving capability. The ring oscillator must be operated in the weak inversion region or sub-threshold region for LV applications. However, when the harvester output voltage is less than the MOS threshold voltage that has a typical threshold voltage of 0.5 V in 0.18 μm CMOS process, the device must work in the weak inversion region, thereby allowing a small amount of current. Consequently, MOS devices exhibit poor drivability and low electrical characteristics. Hence, oscillator's performance deteriorates.

Clock Generator
A bulk biasing technique is exploited to improve device drivability and electrical properties in sub-threshold circuits by adjusting the threshold voltage. The relationship between the threshold voltage and source bulk voltage [20] is given by where is the substrate bias coefficient (body effect parameter, th0 is the threshold voltage for zero substrate bias (i.e. SB = 0), F is substrate Fermi potential, SB is the substrate-body voltage. It is observed from the equation that as bulk source voltage ( SB ) increases, the threshold voltage of the transistor increases, and consequently reverse saturation current of the OFF device decreases, which usually exists in reverse body biasing (RBB). Similarly, as SB increases, the transistor's threshold voltage decreases, and consequently conductance of ON device increases, which generally occurs in forward body biasing (FBB). On the other hand, to obtain both of the benefits discussed above, dynamic body biasing (DBB), a combination of FBB and RBB, is used. Therefore, DBB based ring oscillator (RO), which is depicted in Fig. 4, is exploited in this work. To obtain target frequency, a chain of five stages stacked inverter is utilized, and the size of the inverter is kept small [14] to lower the threshold voltage ( th ). Moreover, the stacked inverters in RO reduce power consumption since the leakage current represents an essential part of the circuit's total consumption when the circuit operates at low voltages. The current leakage can be reduced by means of the stacking effect of transistors [21]. To improve the speed of the CMOS sub-threshold circuits in which drivability is challenging task, several bootstrap drivers have been investigated [22,23]. In the proposed work, a bootstrap technique is incorporated between ring oscillator and phase generator to enhance the load drivability and rail to rail clock output swing of clock generator without increasing overall circuit's power much. Figure 4 depicts the bootstrap driver using dynamic body biasing where B1 and B2 are two bootstrap capacitors, B1 , B2 , B3 are NMOS transistors, and B1 , B2 , B3 are PMOS Transistors. As shown in Fig. 4, the combination of bootstrap capacitors and DBB technique makes the input signals to overcome the shortage of gate overdrive problems for low voltage operation where input voltages are less than MOS device's threshold voltage. The bootstrap capacitors B1 / B2 with pre-charge charge transistors and the driver transistors using DBB can resolve the issue that is related to a shortage of gate overdrive voltage. Consequently, the driving speed of the clock generator becomes better. The output of the bootstrap driver is fed to Phase generator, which can produce dual-phase cross clock signal. Figure 6 shows the schematic of the phase generator [24] that is composed by transmission gate, inverter, and buffer. Usually, phase generator circuit is used to produce non-overlapping clocks. It is implemented by using a dual-branch chain of dual input inverters [17] or by using a chain of at least eight NAND and NOT gates [25]. Thus, significant power drop occurs when the dc/dc boost converter is used for low-power applications. A phase generator circuit, designed in this work with a count of 8 transistors, consumes less power, which is a tremendous advantage for self-powered IoT nodes. In the last stage, large sized progressive buffers are employed to eliminate the undesired glitches in the final clock signal.

Results and Discussions
To verify the benefits of the proposed solution, a fourstage latched charge pump with and without bootstrap driver with 400 mV supply voltage using auxiliary body biasing is implemented and simulated using UMC180 nm triple-well CMOS process.  The proposed CP with dynamic bulk biasing is investigated at the supply voltages of 320 mV and 400 mV regarding output voltage, settling time ( s ), power dissipation, voltage conversion efficiency (VCE), voltage ripple ( ), and rampup current ( r ). Table 1 describes the simulated results for 1 pF load capacitance. Figure 7 shows output voltage transient response of the converter with bootstrap driver under the different supply voltages (i.e., 0.3 V, 0.32 V, 0.36 V, 0.4 V, and 0.44 V) at no-load condition. As shown in the figure, when the supply voltage increases, the response speed increases (i.e., start-up time reduces from 395 μs at 300 mV to about 10 μs at 440 mV). Also, the steady-state output voltage magnitude increases from 1.47 V to 2.18 V. Figure 8 depicts the proposed circuit's output voltage transient response with and without bootstrap driver and its corresponding cross clocks with a 50% duty cycle. Figure 9 illustrates the output transient response using non-overlapping clocks scheme with a 49% duty cycle at a supply voltage of 0.4 V. It can be observed from Fig. 8 and Fig. 9 that cross clocks scheme achieve the output voltage of 1.98 V and 1.91 V with a settling time of 33 μs and 60 μs with bootstrap and without bootstrap driver case. Simultaneously, non-overlapping clock scheme achieves the output voltage of 1.94 V and 1.88 V with settling time of 84 μs and 128 μs with and without bootstrap driver, respectively. However, the proposed circuit with the cross-clock scheme has better steady output voltage level and settling time than the non-overlapping clock scheme. Figure 10  with and without a bootstrap driver at various supply voltages. The achieved pumping efficiencies are more than 99% and 97% of the ideal value for the supply voltages ranging from 300 mV to 470 mV in with and without bootstrap driver cases, respectively. Therefore, the proposed converter with the bootstrap driver has much higher pumping efficiency than without bootstrap driver.  Figure 11 illustrates the dependency of the proposed circuit's start-up time with and without bootstrap driver on the supply voltage. It is noticed from Fig. 11 that as the input voltage increases, the settling time require to settle the output decreases. It can be observed that less start-up time is achieved in with bootstrap driver's case than without a bootstrap driver's case. Figure 12 illustrates settling time under various load capacitances. As load capacitance increases from 1 pF to 10 pF, circuits with and without bootstrap driver require settling times range from 33 μs to 101 μs and 57 μs to 132 μs, respectively. The output versus various load currents of the designed circuiput voltage is plot with and without bootstrap driver for a supply voltage of 400 mV, as shown in Fig. 13. When the load current ranges from 10 nA to 200 nA, the output voltage varies from 1.96 V to 1.32 V and 1.89 V to 0.9 V in with and without bootstrap driver cases, respectively. It can be observed that as load current increases, the output voltage decreases due to decreased load resistance. The designed charge pump with the bootstrap technique performs better compared to without bootstrap technique at different load currents. Table 2 describes the effect of the load capacitor on the proposed CP for 0.4 V supply voltage. It can be observed that the high value of L increases start-up time ( s ) and decreases the ripple. The simulation transients under dynamic conditions are shown in Fig. 14 and Fig. 15. It can be observed that there is no significant change voltage drop till 72 nA and 51 nA in with and without bootstrap driver cases. So, the proposed converter can cope up with the load transients as well. As illustrated in Fig. 16 The incorporation of a bootstrap circuit results in achieving better efficiency than without a bootstrap circuit at both low and high loads. Therefore, the maximum efficiencies achieved are 33.6% and 29.4% with and without bootstrap circuits, respectively. Figure 17 illustrates transient output voltage response over various bulk topologies. It is concluded that the CP using dynamic body biasing with auxiliary transistor has better transient response than existing topologies.   As shown in Fig. 18, it has a mean of 78.58 and normalized standard deviation of 2.8m. Moreover, Monte Carlo simulation power consumption, shown in Fig. 19, results in the average power consumption of 1.3 μW, and standard deviation of 214.4 nW. Figure 20 illustrates total power consumption of the proposed DC-DC converter. Finally, Table 4 depicts the performance comparison of the designed charge pump with state-of-the-art designs. In order to make a fair comparison, figure of merit (FOM) is estimated using (9) This FOM includes several performance metrics such as CMOS process node ( [μm]), voltage conversion efficiency at that supply voltage ( %/ IN ), conversion ratio ( ), no of stages ( ), and minimum start-up voltage ( min ). The proposed design in [16] has better FOM than the proposed converter but uses external auxiliary capacitors and complex clocking scheme. The charge pump in [26], which is implemented in 65 nm node, offers a lower value of threshold voltage for MOSFETs than that of the proposed design. However, without going to lower technology, the proposed circuit, which is implemented in 180 nm, offers almost the same performance as achieved by charge pump in [26]. Also, in comparision with prior works, the proposed circuit has a high conversion ratio, low power consumption,and low settling time.

Conclusion
In this paper, a self-start-up sub-threshold boost converter has been designed and implemented in a CMOS 0.18 μm process. A bootstrap technique is incorporated between ring oscillator and phase generator to enhance the load drivability and rail to rail clock output swing of the clock generator. Consequently, novel cross clocks are generated from the clock generator, which reduces reverse currents in the charge pump. Body biasing has been used to reduce the switching loss and leakage current and also makes the design suitable for low voltage applications. Simulation results verify that better output voltage transient response, lower settling time and higher conversion efficiency can be achieved by the proposed circuit compared to conventional circuits.