A 0.5 V 110 nW Sensor for Temperature Monitoring of Perishable Foods

Real-time monitoring solution is essential for the perishable food to estimate the food quality and to predict its shelf life. In this paper an on-chip temperature sensor which is applicable for UHF RFID passive tag is proposed. MOSFET is used as the sensitive element to the temperature. Since the transistors are biased in sub-threshold region, the power consumption is decreased. To converting proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT) voltages to the digital code, the delay generator and 8-bit ripple counter are utilized. For designing binary counter, a low power and high speed D-flip flap (D-FF) based on gate diffusion input (GDI) technique is employed. The proposed temperature sensor dissipates 110 nW power while the supply voltage is 0.5 V. Simulated in TSMC 0.18 μm CMOS technology, the total chip area is 0.0104 mm and the error is –0.3/0.7°C in the temperature range of –20°C to 10°C.


Introduction
Nowadays using of sensor in the RFID tag is developed in order to increase the level of controlling systems. The temperature sensor is one of the RFID sensors that have a variety of various applications such as the temperature control of patients [1], [2] and the perishable foods temperature control [3][4][5]. The temperature sensors are designed for the various temperatures based on their applications. In these sensors the sensitive element to the temperature can be the resistor [2], BJT transistor [6][7][8][9], or MOSFET transistor [5,10,11]. Among such sensitive elements to the temperature, MOSFETs have the lowest power consumption and acceptable error. To design the sensor, two signals, which are proportional to absolute temperature and complementary to absolute temperature [5] or dependent and independent on the temperature [6][7][8][9], should be created in order to measure the temperature with the comparison of these two signals.
The design of sensor with CMOS technology can be categorized into three groups: the temperature sensor based on analog to digital converter [6][7][8], the temperature sensor based on delay propagation and time to digital converter [5], [12] and the temperature sensor based on ring oscillator and frequency to digital converter [2,11,13]. The temperature sensor based on the analog to digital converter (ADC) dissipates about 80% of its power in ADC block, while it has high chip area. Therefore, despite the high accuracy, it has high power consumption and chip area which makes it unsuitable for using in RFID applications. Usually, temperature sensors based on ring oscillator and delay propagation are utilized for the purpose of having low chip area and power consumption. In the temperature sensor based on the ring oscillator, the signal which is dependent on the temperature is converted into the frequency and then with the help of frequency to digital converter (FDC) the digital data dependent on the temperature is created. In the temperature sensor based on the delay propagation, the signals dependent on the temperature are converted to the delay and then it is changed into the digital data by the time to digital converter (TDC). In general, the sensors based on the delay generator and TDC have lower power consumption and higher accuracy than the sensors based on the ring oscillator and FDC.
In this paper, the RFID passive temperature sensor with very low power dissipation, chip area and error is proposed. The sensitive element to temperature is MOSFET and for converting the PTAT and CTAT voltages to the output digital data, the delay generator and 8-bit counter with 2.5 MHz clock frequency are used. The considered temperature range is -20°C to 10°C which is commonly suitable for controlling the foodstuffs and depraving foods.
In Sec. 2, the designed temperature sensor is proposed. The simulation results are presented in Sec. 3 and finally the conclusion is stated in Sec. 4. the core of sensor, PTAT and CTAT delay generators and the digital part of the sensor. The current source supplies the bias current of the sensor core. First, two signals which are V PTAT and V CTAT are produced in the sensor core by the variation of the temperature. By passing of delay generators the modulated voltage signals to the temperature are converted to the time. The output pulse widths of PTAT and CTAT delay generators are proportional to and inverse of temperature, respectively. In this process, by implementing XOR function on two output pulses the non-linear part of these signals which is dependent to the temperature is eliminated. Finally, the output pulse width is proportional to the voltage difference between V PTAT and V CTAT and also is dependent on the temperature linearly. Then the XOR output is changed into the digital code in the digital part of the sensor by the binary counter which counts the rising edge of clock along the pulse width during one period of sampling. The sampling period independent on the temperature is determined by the reader [14]. Then the digital code is saved in the memory of the tag digital core in order to provide the temperature data for the reader when it is necessary. For reducing the power dissipation, the analog part of the sensor is deactivated after each conversion and the sensor becomes ready for the next conversion. Figure 2 shows the presented nano-ampere reference current source [15] which supplies the required current for PTAT and CTAT voltage generators. This structure includes the start-up circuit, the current source, PTAT voltage generator and biasing voltage circuit. Unlike M 9 which works in deep triode region, the rest of the transistors work in sub-threshold region. M 9 and M 17 have the same size and are biased with the equal current. According to [16], the reference current is calculated as

The Reference Current Circuit
where I REF0 is independent of the temperature and m is the temperature exponent of the carrier mobility (μ = μ 0 (T 0 /T) m ), which is a process-dependent parameter.

The Design of the Sensor Core
For designing of the proposed temperature sensor, first two V PTAT and V CTAT signals are produced with sensor core that by comparing these two signals, the temperature is determined. Two different structures of the PTAT voltage (b) the differential pair PTAT voltage generator [15].
generators are shown in Fig. 3. The classic PTAT voltage generator [14], in which the transistors work in sub-threshold region by employing the low supply voltage, is shown in Fig. 3(a). The PTAT voltage is the voltage difference between V gs of M N1 and M N2 , which are biased in sub- where η is the sub-threshold slope, V T is the thermal voltage and V gs is the gate-source voltage of the transistor. Figure 3(b) shows the PTAT voltage generator presented in [15]. This circuit includes the differential pair with the current mirror circuit. When the MOSFETs work in sub-threshold region, V PTAT,b is achieved as is a process-dependent parameter and V th is the threshold voltage. Therefore V PTAT,b is gained with the condition of k´> 1. The PTAT voltage generator of Fig. 3(b) has more linear behavior than that of Fig. 3(a). In addition, it is more controllable for adjusting the PTAT voltage, since not only the size of differential pair transistors, but also the size of active load transistors effects on the PTAT voltage value. Figure 4 shows the proposed sensor core. This design consists of the reference current circuit and the PTAT and CTAT voltage generators. In the proposed sensor core the combination of the primary cores presented in Fig. 3, the classic and differential pair voltage generators, is used for generating PTAT voltage.
In order to increase the PTAT voltage level, the sizes of differential pair and active load transistors can be increased, which culminates in decreasing the chip area. Thus three stages of the differential pair are employed to this design for the purpose of ameliorating the voltage level. Knowing that all transistors operate in subthreshold region, V PTAT is achieved as CTAT voltage of the proposed sensor core is produced by two diode-connection MOSFETs, M C1 and M C2 which work in sub-threshold region. Based on I-V characteristic of MOSFET in sub-threshold region and replacing (1) in it, equation (5) is achieved in which the temperature dependence of V gs,C1,2 is stated as By the appropriate choosing of transistors W/L, V gs,C1,2 has the inverse relation to the temperature. CTAT voltage is gained as At the start of each conversion, V st is employed and activates M D4 (M D9 ), so C P (C C ) can charge to V DD at the pre-charge process. The measurement process initiates by the rising edge of V st signal which comes from the tag digital core. I PTAT and I CTAT discharge C C and C P , respectively. XOR gate is employed to the buffer outputs of these two PTAT and CTAT delay generators to produce the temperature dependent pulse. The pulse width of XOR output is dependent on pulse width of modulated temperature signals which are produced from PTAT and CTAT delay generators. The time delay of the XOR output pulse width is calculated as

The Design of the Delay Generator
where ΔV (= V DD -V th ) is the voltage difference between V DD and threshold voltage of inverter transistors at the input of buffer. The value of I CTAT (T) and I PTAT (T) are calculated as (9) and (10), respectively where T is the instantaneous temperature, T 0 is the reference temperature, k P and k C are the temperature coefficient of I PTAT and I CTAT , respectively. By using (9) and (10) in (8) and considering only the first and second term and ignoring the rest of the terms, the XOR output pulse width is calculated as (11): As it is clear from (11), if the output pulse width of each delay generator has the non-linear relation to the temperature, after implementing XOR, the non-linear parts are eliminated and the output pulse width of the XOR has the linear relationship to the temperature. Then by quantizing the pulse width with ripple counter the digital temperature data is achieved from the same conversion. At the end of each conversion, when the edge of XOR pulse signal falls the done signal is triggered and makes C P and C C completely discharged. By sending of this signal, the end of conversion is determined and the sensor becomes ready for the next conversion.

The Design of Ripple D-FF Counter with
the GDI Technique Figure 6 shows the novel structure of the 14-transistor D-Flip Flap (DFF) with Gate Diffusion Input (GDI) technique. GDI technique is recently developed and is efficiently replaced instead of CMOS and SOI technology in the design of logic circuits. Using this technique in the DFF structure decreases more delay, number of transistors and chip area in comparison with 18-transistor CMOS cell. GDI technique in the DFF design dissipates lower power, since it reduces the sub-threshold leakage current and the components of gate leakage current. Generally employing this technique in the ripple counter not only improves the power consumption and chip area, but also increases the speed of counter in the digital circuits of the sensor.

Simulation Results
The proposed temperature sensor is designed in 0.18µm CMOS technology. In this design the values of C P and C C are considered 1 pF. Table 1 presents the size of transistors used in this design. Figure 7 shows the output signals of the sensor core, V PTAT and V CTAT , in the temperature range of -20°C to 10°C. The output of V PTAT and V CTAT delay generators and also the XOR output pulse are shown in Fig. 8 at the temperature of 10°C.
Based on (11), by decreasing the temperature the pulse width is increased which is shown in Fig. 9(a). In addition, Fig. 9  generators. The process variation and mismatch of the sensor core transistors M C1,C2 and M P1-P8 , the current mirror transistors M T1-T12 and the used capacitors in the delay generators are the most important factors in the existence of the proposed temperature sensor error. Figure 10 shows the Monte Carlo simulation results of the sensor error for 100 runs that the mean and standard deviation are 0.18°C and 0.33°C, respectively. According to Monte Carlo simulation, the measured error of the samples varies in the range of -0.3°C to 0.7°C in the temperature range of -20°C to 10°C.
The comparison of the results of the proposed temperature sensor with some recently designed sensors is presented in Tab. 2. In comparison with the other sensors, the proposed sensor has the lowest chip area and power dissipation as its transistors work in sub-threshold region.
The layout of the proposed sensor, which occupies 0.0104 mm 2 area, is shown in Fig. 11.

Conclusion
A low power CMOS sensor is designed for temperature control of the perishable foods at the temperature range of -20°C to 10°C. The sensor core transistors work in sub-threshold region. D-FF based on GDI technique is employed to the counter instead of conventional D-FF to reduce the power dissipation. Considering 0.5 V supply voltage and 10°C temperature, the power dissipation of the sensor core, delay generator and digital part is only 110 nW. This sensor which has low power dissipation and low chip area is suitable for RFID tag applications. Using the Cadence software, the temperature sensor is simulated in 0.18µm CMOS technology.