Comparison of MOSFET Gate Waffle Patterns Based on Specific On-Resistance

This article describes waffle power MOSFET segmentation and defines its analytic models. Although waffle gate pattern is well-known architecture for effective channel scaling without requirements on process modification, until today no precise model considering segmentation of MOSFETs with waffle gate patterns, due to bulk connections, has been proposed. Two different MOSFET topologies with gate waffle patterns have been investigated and compared with the same on-resistance of a standard MOSFET with finger gate pattern. The first one with diagonal metal interconnections allows reaching more than 40% area reduction. The second MOSFET with the simpler orthogonal metal interconnections allows saving more than 20% area. Moreover, new models defining conditions where segmented power MOSFETs with waffle gate patterns occupy less area than the standard MOSFET with finger gate pattern, have been introduced.


Introduction
Miniaturization in the semiconductor industry is a well-known practice. It is driven not only by price per area optimization, but it also allows realizing new types of applications, which are not easily reachable by previous generations of technologies. Actual trends and intensive developments are currently focused on mobile electronics, wearable electronics, and Internets of Things (IoT) applications that are limited by miniaturization possibilities. Applications such as smart watches, electronics pills, wireless head speakers, or Augmented Reality (AR) glasses represent a small part of new types of applications that come from progress in miniaturization. To solve high requirements on system dimensions, the highest process nodes are being used as well as whole system integration by using System in Package (SIP), System on Chip (SoC) approach, Package on Package (PoP) or more advanced Through Silicon Via (TSV). The last TSV is used for 3D Integrated Circuits (IC) with more optimal interconnections and for more compact chips stacking. Additional advantage of smaller chip area is yield improvement [1].
In past and also nowadays, a big portion of IC chips are occupied by power management. In order to save area in SIP packages, we could use the more compact vertical power devices. Hence in more compact SoC, only lateral power devices can be used. For additional effective scaling of lateral low voltage power devices, the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with waffle gate patterns can be used [2]. Another publication deals with RF measurement of the waffle MOSFET without defining analytic model of channel conductance [3]. Vemuru has described models for square shape waffle MOSFET in [4]. However, these models do not allow describing non-square shapes. Madhyastha [5] has described waffle MOSFET with orthogonal source and drain interconnection but its metallization is more complex and has a weak electro-migration limit. Moreover, the waffle structure robustness against threshold degradation due to ionizing dose radiation has been described in publication [6]. Shen-Li Chen [7] has described properties of lateral HV LDMOS waffle structures used for ESD of IC.
The advantage is that waffle gate topology patterns do not require any further adjustment of the process. This paper   [2]. introduces a new model allowing description and comparison of two waffle gate patterns. The first one is a MOSFET with waffle gate topology and with orthogonal source and drain interconnection (Fig. 1). This metal interconnection is more robust in term of serial resistance and electromigration than Madhyastha used [5]. The second one is a MOSFET with waffle gate topology and diagonal source and drain interconnections (Fig. 5). Both of them are compared with a standard MOSFET with finger gate topology (Fig. 3).
The IC fabrication process follows all process design rules that are collected in a design rule manual (DRM). Related to MOSFET geometry, the process design rule is often based on the scale process factor λ [2], [4]. Then the relationship between scale factor λ and the feature sizes is as shown in Tab. 1 [2]. Dimension d 5 defines a minimum spacing between polysilicon gates with a contact to diffusion in between (Fig. 4). Dimension d d5 defines a spacing between gates with the contact to diffusion in between but contact is rotated about 45° (Fig. 7).
To support devices of higher voltage range from dual oxides processes, the gates length is also considered larger than minimum. In other words in this article, the gate length d 1 can acquire a larger dimension than the minimum value defined in Tab. 1.

Comparison Method
For a quantitative comparison of different MOSFET structures, it is necessary to define a qualitative parameter for evaluation of benefits coming from more complex layout structures.
Drain current I D in linear region of the MOSFET transistor with nonrectangular channel area is defined as where V GS is gate to source voltage, V T is threshold voltage and V DS is voltage between drain terminal to source terminal of the MOSFET,  is charge-carrier effective mobility, C OX is gate oxide capacitance per unit area and (W/L) EF is an effective width to length ratio of the channel.
For small V DS where V DS << 2 (V GS -V T ), the drain current is linear function of V DS described by From known drain current I D , it is possible to define the resistance of path from the drain to the source terminals marked as R DS-ON with neglecting contacts and diffusion resistance [1] marked as Equation (3) describes the main contributor to the total resistance. As can be seen, the other contributors such as package constraints, metal interconnection resistances, wire bonding or ball array that can play an important role in the total R DS-ON resistance are not present in (3), because it is outside of the scope of this paper.
For regular finger shape of the MOSFET channel, the on-resistance is proportional to the channel length L, inversely proportional to the channel width W, and inversely proportional to the width to length ratio of the channel For MOSFETs with non-regular channel area such as waffle gate, the resistance R waf is inversely proportional to the effective width to length ratio of the channel (W/L) waf In practice, the power MOSFET devices are described by a figure of merit parameter known as specific on-resistance and defined as resistance on device area. In our case the specific on-resistance of MOSFET with waffle gate sR waf is where R waf and A waff is resistance and area of the MOSFET with waffle gate topology, respectively. The specific onresistance can be used not only to compare power MOSFETs devices but also to calculate the area for the required resistance. The area of MOSFET devices with the same resistance for waffle gate topology and finger MOSFET (A waf ) Rfin is described by the following expression The Area Increment AI of waffle MOSFET compared to finger MOSFET is where after insertion of (7) into (8) the Area Increment AI is waf waf waf fin fin fin fin waf 1 1 .
The figure of merit parameter AI quantitatively defines how much of the waffle structure area is required to achieve the same on-resistance as the standard MOSFET with finger gate topology has.
To achieve high reliability of power MOSFETs transistors, the bulk connections should be robustly connected. From a layout point of view, the bulk connection divides the whole power MOSFET into smaller segments. These segments are repeated over all structure (Fig. 2), and then the total area of the power MOSFET A MOS is where N S is a count of power MOSFET segments separated by bulk connection, d B is a bulk dimension, d X , d Y are X dimension and Y dimension of power MOSFET segment, and A SEG is its area.
In this paper, a comparison between different power MOSFET structures has been realized at the same or very similar robustness of a bulk connection. Due to the same bulk connections and simplification of analytic models, the segment area or its subpart (core area) shown in Fig. 2 have been used for comparison of different power MOSFET structures described after.

Standard MOSFET Structure with Finger Gates
The basic MOSFET structures have finger gate topology where each finger has a rectangular shape of channel region as can be seen in Fig. 3. For correct and robust well polarization, the bulk connections are created on each side of the MOSFET.
An example of a segment of standard MOSFET topology with two finger gates without bulk connection is shown in Fig. 4. The Y dimension of this standard MOSFET and its width are in general defined as a real number. In this publication, it is considered as a discrete value due to alignment with waffle MOSFET dimensions and to simplify the analytic model. Due to this Y dimension of the standard MOSFET, it is possible to scale by an equivalent number of gate fingers N yF in Y-axis.
For full analytical description, it is important to define not only dimensions of the whole structure but also its subparts called core area. The core area A FC of the standard  MOSFET segment with finger gate and without considering peripheral area outside the core area is where N xF is a number of gate fingers in X-axis direction.
Since the core area does not always contain whole contacts inside the boundary but also their fractions (Fig. 4). It is important to define area enlargement to allow fit of whole contacts into the boundary. In this publication, we consider enlargement of the core area about d 5 /2 on each side in X and Y-axis. After that, the segment area of the standard MOSFET with finger gates A F is The width to length channel ratio in the core area for the standard MOSFET with finger gates WL FC is and the width to length channel ratio for the standard MOSFET with finger gates on segment area WL F is

Waffle MOSFET Structure with Diagonal Source and Drain
The MOSFETs with waffle gate topology have diagonal interconnections of source and drain terminals comparing to the standard MOSFET with finger gate topology (Fig. 5). The presented structure is compatible with all processes where diagonal interconnection is allowed and where the waffle shape polysilicon gates do not violate the process design rules. No additional process steps are required. The partitioning of the channel area of the waffle MOSFET segment is in Fig. 6.
Core area A WdC of the MOSFET segment with waffle gates and diagonal source and drain interconnections without considering peripheral area outside the core area is where N xWd is a number of gate fingers in X-axis direction and N yWd is a number of gate fingers in Y-axis direction. The segment area of the MOSFET with waffle gates and diagonal source and drain interconnections A Wd is The width to length channel ratio in core area WL WdC for the MOSFET with waffle gates and diagonal source and drain interconnections is where WL B is width to length channel ration in the region of element B (Fig. 6).
The width to length channel ratio WL Wd of the MOSFET with waffle gates and diagonal source and drain interconnections on segment area is

 
(18) As we can see, equation (18) describing the width to length channel ratio of the MOSFET with waffle gates and diagonal source and drain interconnections is a sum of width to length ratios of homogenous elements A, central elements B, and cross edge element E (Fig. 6).

Waffle MOSFET Structure with Orthogonal Source and Drain
Additional waffle structure is the MOSFET with waffle gates in orthogonal interconnections of the source and drain terminals (Fig. 1). Because source and drain contacts in the layout are not rotated, the layout of the structure (Fig. 7) is in general compatible with all processes where diagonal polysilicon gate does not violate the process design rules. No additional process steps are required. The bulk connection makes segmentation of the compact whole power MOSFET into segments repeated over structure. To prevent process modification or design rule violations the contacts are not rotated about 45°. Due to this reason the spacing between two polysilicon gates d d5 is larger than d 5 for waffle MOSFETs with diagonal source and drain interconnection as can be seen in Tab. 1. The core area of the MOSFET segment with waffle gates and orthogonal source and drain interconnections A WoC without considering peripheral area outside the core area is where N XWo is a number of gates in X-axis direction and N yWo is a number of gates in Y-axis direction.
The segment area of the MOSFET with waffle gates and orthogonal source and drain interconnections A Wo is The width to length channel ratio WL WoC in core area for the MOSFET with waffle gates and orthogonal source and drain interconnections is The width to length channel ratio WL Wo for the MOSFET with waffle gates and diagonal source and drain interconnections on segment area is As can be seen in (22), the width to length channel ratio for MOSFET with waffle gate and diagonal source and drain interconnections is a sum of width to length ratios of homogenous elements A, central elements B and cross edge elements E.

Width to Length Ratio Calculation for Waffle MOSFET Elements
For calculation of width to length channel ratio of the element B and element E, 2D Finite Element Method (FEM) solver from TCAD SILVACO was used [8]. Test structure of element B is shown in Fig. 8.
The effective width to length channel ratio of the cross test structure (W/L) cross is calculated based on the simulated 2D resistance R 2D and its resistivity  as follows   To consider only the width to length channel ratio of element B, it is required to subtract the width to length channel ratio of four elements A. By considering homogenous current distribution in area of elements A and its subtraction from cross element, all nonhomogeneous current distributions will be pressed only into area of element B. L'/W' [-] For homogenous current distribution in elements A, the effective width to length ratio is equal to its geometry aspect ratio The result of the calculation as a function of its dimension is in Fig. 9.
For dimensions with ratio L'/W'< 10, we can approximate data from TCAD simulation by the following fitting function Another element E (Fig. 10) describing channel on the periphery can be calculated in a similar way. From known 2D resistance R 2D (TCAD simulation) and its resistivity  it is possible to calculate effective width to length channel ratio of cross test structure (W/L) cross2 as D cros2 2D DS To consider only width to length channel ratio of element E, it is required to subtract the width to length channel ratio of two elements A. By considering homogenous current distribution in the area of elements A and its subtraction from edge cross element, all nonhomogeneous current distribution will be pressed into the area of element E only.
For homogenous current distribution in elements A the effective width to length ratio is equal to its geometry aspect ratio Calculated results of effective width to length channel ratio of element E are shown in Fig. 11.  For L'/W' value smaller than 10, we can approximate data from TCAD simulation by the following fitting function

Core Structures Comparison
For core structures comparison, the figure of merit AI is used. In this section, no edge elements C, D and E will be taken into account.
In addition, the analytic model has been verified by 3D TCAD simulation from SILVACO [8] for different dimensions. The first simulated structure is the NMOSFET with finger gates (Fig. 12) and the second is the NMOSFET with waffle gates (Fig. 13). The simulated NMOSFET transistors have been in linear region where V GATE is equal to 2.0 V, V DS is equal to 0.2 V and gate threshold voltage V TH is equal to 1.18 V.
The resistance R DS-ON has been calculated from simulated drain current I D . The Area Increment AI is calculated from R DS-ON resistance of waffle and finger structures and from their areas by applying (9) (Fig. 14). To simplify the analytic model of Area Increment, we can define aspect ratio of gate dimension d 1 and dimension of source or drain area d 5 as follows Putting expression (11), (13), (15), (17) and (25) into (9) and by applying (29) As can be seen from (32), the Area Increment AI WOC is also independent on area dimensions of core elements N xF , N yF , N xWo , N yWo .
Since equation (32) is a function of two aspect ratios AR 15 and AR 1d5 , it will be useful to simplify it. The first step is to define relation between d 5 and d d5 by using scaling parameter  from Tab. 1 As mentioned earlier, the figure of merit parameter Area Increment AI quantitatively defines the amount of needed areas to have the equal resistance of waffle structures and the standard MOSFETs with finger gates. When qualitative parameter Area Increment of waffle structure has negative value, it means that the waffle structure requires less area. Due to this, for real application it is very useful to know the dimensions of waffle structures where AI is negative.
The equations (36) and (37) can be used for analytic definition of conditions when the area of core waffle structure occupies smaller area than the core finger structure with the same resistance.

Structures Comparison Considering Edge Elements
For more precise comparison of two topologies with considering edge elements, it is useful to have the same or similar area of each test structures. The same area of segments of the MOSFETs with finger or waffle gate topology and with diagonal source and drain terminals is guaranteed when N x = N xF = N xWd and N y = N yF = N yWd . After putting expressions (12), (14), (16), (18) and (25) After putting (12) By inserting (34) into (41), the simplified Area Increment AI WO is a function of one aspect ratio AR 15 only and thus it can be defined as given in (42) below.

Definition of Waffle Use Cases Considering Edge Elements
In general, qualitative parameter Area Increment AI has negative value for all used cases, because only then the area of waffle structure occupies smaller area than finger structure with the same resistance. The Area Increment from (38)    .
Equations (43), (44), (47) and (48) can be used for analytic definition of condition when the area of waffle structure occupies smaller area than the finger structure with the same resistance.

Comparison of Models with FEM Results
To analyze proposed models, more complex test structures in certain process have to be simulated in 2D FEM solver Agros2D [10] and the results are presented in Tab. 3. For test structures, the TSMC 0.35m process design rules have been modified to be more robust (Tab. 2).
An example of potential gradient for three different gate patterns simulated in Agros2D can be seen in Fig. 15  area A F = 2144 m 2 and width to length channel ratio calculated by analytic model is WL F = 136.17. Tab. 3. Comparison of Core Area Increment AI C and Area Increment AI for different layout structures where N x is the dimension in X-axis, N y is the dimension in Y-axis, A c is the area of the core structure, A is the area of the whole structure, (W/L) c is the effective width to length channel ratio of the core element, (W/L) is the effective width to length channel ratio of the whole element, (W/L) FEM is the effective width to length channel ratio of the whole element calculated with FEM by using Agros2D tool, (W/L) ERR is the relative error between (W/L) and (W/L) FEM , (* value for dimension d d5 , # value for ratio d 1 / d d5 ). F is Standard MOSFET with finger gate, Wd is MOSFET with waffle gate having diagonal interconnections of source and drain terminals and Wo is MOSFET with waffle gate having orthogonal interconnections of source and drain terminals.
The waffle MOSFETs with diagonal source and drain terminals and dimension N x = 5, N y = 5 has identical area A Wd = 2144 m 2 as standard MOSFET with finger gates and have width to length channel ratio calculated by analytic model WL Wd = 236.35 which is about 0.66% higher value than calculated by FEM WL Wd = 234.8. From these analytic values by using (9), the Area Increment AI = -42.38% can be calculated.
Based on this figure or merit parameter, it can be concluded that the waffle MOSFET with diagonal source and drain terminals with the same resistance as the standard MOSFET with finger gates occupies about 42.38% less area than finger structure, or equivalently for the same area, it has about 42.38% less resistance. On top of that, the analytic definition of requirements for AI Wd < 0 based on (43), (44) From the results, it is also apparent that the Area Increment calculated for core area AI C presented by [2] is independent on segment dimensions and depends on aspect ratio of d 1 /d 5 or d 1 /d d5 only. Because it does not consider peripheral elements, it cannot be used for precise description of power MOSFETs with segmentation.

Discussion
In this work, the gate length d 1 is considered in wider range. Due to this, the aspect ratio AR 15 defined by (29) can be larger than minimum ratio 1/3 used in [3] and [4] defined based on the λ scale process factor. The reason for larger gate length variability is to cover dimensions of low voltage MOSFETs with higher voltage range used by processes with dual oxide. In these processes, the gate with thicker oxide also has a larger length to sustain the higher voltage, but minimum contact to polysilicon spacing d 3 is robust so that it can remain the same. Hence, also the di-mension d 5 can remain unchanged. Additional used cases for longer gate are in analog design where different W/L ratios are required.
In general, width to length channel ratios of non-homogenous elements B and E with non-homogenous current distribution are fixed values and do not have to variate with different element geometry. In opposite, width to length channel ratios of homogenous elements A, C and D with d 5 >> d 1 have mostly homogenous current distribution and have to variate with ratio of element geometry. For d 5  d 1 , the elements C and D mostly have non-homogenous current distribution. In publications [2], [3], [4], and [5], only homogenous currents are considered for these partially homogenous elements. In this work, all non-homogenous current distributions are considered to reach higher precision of width to length channel ratio calculation in range d 5  d 1 . This error correction is presented in the value of width to length channel ratio of non-homogenous elements B and E. This is the reason why width to length channel ratios of non-homogenous elements B and E are not fixed values and have to variate with different element geometry (25)

Waffle MOSFET Implementation in Power Integrated Circuits
Advantage of waffle MOS structures is that it allows improving of specific on-resistance of power MOSFET structures even without additional process steps or process modification of mature process. To reach the same R DS-ON with using waffle MOS topology, the smaller power MOS area structure is required.
In order to use the waffle MOS concept in real application, the test chip has been designed and fabricated. In power management product from STMicroelectronics, made in 160nm BCD8sp process, the main low voltage (5V) power MOSFET Fig. 3 has been replaced with the equivalent waffle power 5V MOSFET with orthogonal source and drain interconnections Fig. 1. Because the waffle MOSFET has the same orthogonal source and drain interconnection as the original finger MOSFET, the replacement was faster and easier.
The proposed new IC with smaller power part passed all standard product validation tests [11]. Measured onresistance of the original power MOSFET with finger gates was 397.53 m and measured resistance of the waffle MOSFET was 397.92 m. Even we can consider the same on-resistance for both power MOSFET structures, the area of waffle MOSFET is about 19% smaller compared to the finger MOSFET structure Fig. 16. Due to the smaller power MOS area and the same control part area, the total chip area has been reduced about 6%.

Conclusion
To achieve high reliability of power MOSFET structures, the bulk connections have to be robustly connected [12]. This segmentation of power MOSFETs influences the specific on-resistance parameter. In this article, two MOSFET topologies with waffle gate with a diagonal and orthogonal source and drain interconnections have been compared and the new analytic models have been described for the first time. The proposed models in comparison to Vemuru [4] allow evaluating non-square shapes of power MOSFETs. Moreover, proposed orthogonal source and drain interconnections of waffle structure are much simpler in comparison to orthogonal topology proposed by Madhyastha [5] where an orthogonal source and drain interconnection has more complex metallization and has a weak electro-migration limit.
In addition, the analytic models of effective width to length channel ratio have been compared by numerical 2D FEM simulation. Here, the good match has been observed between analytical and numerical models with differences less than 2% for both waffle structures. This paper confirms that models [2] considering only core area elements are not sufficiently precise for the accurate description of power MOSFETs with segmentation. Therefore, in this work, the new more precise models have been presented.
The examples of MOSFET topology with waffle gate pattern with diagonal source and drain interconnections and the standard MOSFET with finger gates have been com-pared with the condition of the same on-resistance. As a result of this comparison, the waffle gate pattern with diagonal source and drain interconnections occupies 42.38% less area than the standard one.
Similarly, the second example of MOSFET topology with waffle gate with an orthogonal source and drain interconnections occupies 22.43% less area compared to the standard MOSFET with finger gates with the condition of the same on-resistance. Moreover, in this paper, for the first time conditions have been defined where the segmented power MOSFETs structures with waffle gates occupy less area than the standard MOSFET structures with finger gates having the same channel on-resistance.
All analytical models of power structures have been realized based on FEM simulations. The silicon measurements of on-resistance for power MOSFET with finger and waffle gate have been proposed in the real application. In the power IC, it has been presented 19% area saving of power 5V MOSFET in 160nm BCD8sP process by using waffle power MOSFET with orthogonal source and drain interconnections.