An Efficient MRTD Model for the Analysis of Crosstalk in CMOS-Driven Coupled Cu Interconnects

This paper presents an efficient wavelet based numerical method for analyzing functional and dynamic crosstalk of CMOS driven coupled copper (Cu) interconnects known as Multi-Resolution Time Domain (MRTD), wherein, the CMOS drivers are modeled using nth-power law model. The performance of the proposed MRTD method is evaluated through recursive simulations in HSPICE environment and compared with the conventional Finite Difference Time Domain (FDTD) method at 32-nm technology node for global interconnects of length 1mm, where the computations of the proposed model and conventional FDTD are carried out using MATLAB. For different number of test cases, the proposed MRTD method gives an average error of 0.14% and 1.9 % for peak crosstalk noise and peak noise timing, respectively, with respect to HSPICE results. Also, the dynamic crosstalk noise on victim line of the proposed MRTD method are in close agreement with those of HSPICE. The results show the dominance of the proposedMRTDmethod over the conventional FDTD method regarding accuracy. The proposed MRTD method is also extended for three-mutuallycoupled interconnect lines for crosstalk analysis, with an average error less than 1%when compared to that of more than 3% using the conventional FDTD method. Moreover, for the transient analysis, the MRTD method is more time efficient than HSPICE.


Introduction
With the evolution of deep sub-micron CMOS technology, the circuits in chips (SOCs) allow Giga-scale integration.In such circuits, the analysis of interconnects have become extremely important to determine the performance of a circuit such as power consumption and time delay.In addition to the delay, with the high operating frequencies, crosstalk is a pitfall in the design of interconnect structures for circuitry.As on-chip circuitry is gradually miniaturized, the adjacent interconnects are brought into closer proximity.Accordingly, the undesired signal coupling between the interconnects gets elevated [1].So, the precise prediction of peak crosstalk noise and peak noise timing in a driver-interconnect-load (DIL) system has become a critical design view for a long period [1].
For the analysis of the crosstalk noise, most of the earlier models have considered non-linear CMOS driver as a simple linear resistor [2], [3], which leads to a discrepancy in the results.Because, during the transient, MOSFET operates in saturation region about 50 % of its operating time and rest of time in linear (or) cutoff regions [4].
To model a DIL system, several methods have been reported in the recent state of the art works , where different analytical solutions, the Finite Difference Time Domain (FDTD) method and SPICE solutions are explored [5], [6].The alpha-power law model used for modeling non-linear CMOS driver and an interconnect line is modeled using the Analytical approach for the analysis of functional crosstalk effects [5] and dynamic crosstalk effects [7].The models outlined in [5] and [7] is limited to only two coupled interconnect lines resulting in dependance on even-odd modes.To analyze the dynamic crosstalk of multiple mutually coupled on-chip interconnect lines, Vobulapuram et al. in [8] used FDTD method for modeling of interconnect lines where CMOS driver is represented using alphapower law model.The alpha-power law model becomes imprecise with the technology scaling, as it ignores the finite drain conductance (λ) parameter.Later, in [9], Vobulapuram et al. employed n th power law model [10], which includes the finite drain conductance (λ) parameter to represent CMOS driver with FDTD [11] for modeling mutually coupled interconnect lines.
The conventional FDTD method is a substantial numerical technique for solving partial differential equations and Electromagnetic problems.But the conventional FDTD method is numerically dispersive [12].The Multiresolution Time-Domain (MRTD) method proposed by Krumpholz et al. in [13] presents significant advantages in numerical dispersion properties [14]- [17].In Multiresolution analysis using the Haar scaling function as the basis function, the MRTD algorithm is equally accurate with the conventional FDTD [15].The Daubechies' scaling function based MRTD method with three and four vanishing moments shows higher accuracy than conventional FDTD [16].The MRTD method using the Daubechies' scaling function as the basis function for the transient analysis of transmission lines shows a better dispersion property than the FDTD method [18].However, the MRTD method has not been used to calculate the crosstalk noise and delay of CMOS driven coupled on-chip interconnects in the present state of the art works.This paper adopted the MRTD [18] method for the analysis of crosstalk noise of VLSI interconnects.To drive the interconnect lines a non-linear CMOS driver is considered, which is modeled using nth power law model [10].
The rest of the paper is organized as follows: Section 2 discusses the formulation of the MRTD method for coupled Cu interconnect lines.Section 3 describes the simulation setup and the validation of the results for two and three coupled interconnects, followed by conclusion in Sec. 4.

Formulation of the MRTD Method
The proposed MRTD method is developed using Daubechies' scaling function as the basis function having four vanishing moments for coupled VLSI interconnects.In a more practical approach, CMOS drivers are considered for analyzing the performance more precisely.Capacitive loads are considered for the termination of interconnect lines.The schematic of the CMOS-driven coupled interconnect lines are shown in Fig.

Modeling of Coupled VLSI Interconnects
The coupled on-chip interconnects considered as distributed RLC transmission lines are described by telegrapher's equation [11].
where the voltages (V) and currents (I) are expressed in 2 × 1 column vector form V 1 V 2 T , I 1 I 2 T and line parasitics are expressed in 2 × 2 matrices per unit length as shown below.
The accuracy and stability of the MRTD method for solving telegrapher's equations is achieved by considering the voltages and currents which are separated by ∆z 2 in space and ∆t 2 in time as shown in Fig. 2, where ∆z is the space discretization interval and ∆t is the time discretization interval.
A CMOS driver drives the interconnect line of length l at z = 0 and capacitive load terminates it at z = l.The line is divided uniformly into Nz segments of length ∆z = l Nz , representing the discretized voltage and current nodes which are unknown coefficients as shown in Fig. 3., where I 0 represents the source current.
To solve (1a) and (1b), the voltage and current terms can be expanded using the known functions (φ k (z) and h n (t) ) and the unknown coefficients are considered from the method outlined in [13] as: where V n k is the coefficient of the voltage expansion and I   The function h n (t) and φ k (z) is defined as: where h (t) represents a Haar scaling function and φ (z) represents a Daubechies' scaling function.
To derive the MRTD method for equation (1a) and (1b), the following integrals [19] are considered: where δ k,k and δ n,n represents the Kronecker symbol.In equation (6b) S b denotes the effective support size of the basis functions.The coefficients a(i) are called connection coefficients.By considering Daubechies' scaling function having four vanishing moments (D 4 ) as the basis functions, Tab. 1 shows a(i) for 1 ≤ i ≤ S b , whereas a(i) for i > S b are zero and for i < 1 it can be obtained by the symmetry relation Applying the Galerkin technique [13] to equations (1a) and (1b) using the test functions φ k+ 1 2 h n (t) and φ k h n+ 1 2 (t), the following iterative equations for the currents and voltages are obtained: where In the iterative equations (7a) and (7b), not only the near-end boundary voltage V n+1

and far-end boundary voltage V n+1
Nz+1 are derived but also the iterative equations of the voltages and currents near the boundaries also need to be updated.Near the boundaries the voltages are represented by For updating the iterative equations of voltages and currents, equation (7a) and (7b) need to be decomposed using the relation in [20], which satisfies the coefficients a(i) given by

and the currents by
Substituting ( 8) into (7b), we get Considering the corresponding terms with i, we can decompose (7b) as: Equation ( 10) is further modified by applying the boundary conditions as illustrated in Sec.2.2 and Sec.2.3 respectively.

Modeling of CMOS Driver
The CMOS drivers are modeled using nth power law model that considers the effect of finite drain conductance parameter (λ) along with velocity saturation.During transient simulation the operation of the pMOS and nMOS transistors are in either linear, saturation (or) cutoff regions [4].
The pMOS and nMOS current equations using n th power law model are where I DSATp (I DSATn ), λ p (λ n ), V DSATp (V DSATn ), and V Tp (V Tn ) are the drain saturation current, finite drain conductance parameter, drain saturation voltage and the threshold voltage of pMOS (nMOS) respectively.The drain saturation voltages and currents of pMOS and nMOS are obtained from The parameters K p (K n ) and m p (m n ) control the linear region, whereas B p (B n ) and n p (n n ) control the saturation region characteristics of pMOS (nMOS) transistor.The effective channel length is represented by L eff and the width of pMOS (nMOS) represented by W p (W n ).The model parameters [9]

Modeling of DIL System
Modeling of the DIL system is incorporated with the boundary conditions.The current equations incorporate near-end and far-end interconnect terminal conditions, where the nodal equation of the source current (I 0 ) at the near-end terminal (at k = 1) is given by: where By applying the Galerkin technique [13] to eq. ( 13), we obtain So, the voltage at near-end terminal of interconnect is obtained by substituting k = 1 in equation (7b) Equation ( 15) is decomposed by following the steps from the equations ( 8)- (10).From the decomposition, we know that the subscript of the term I (15) exceeds the index range, for i = 2, 3, • • •, S b .So, a forward difference scheme is used to overcome this difficulty.Therefore, the final iterative equation for near-end terminal voltage V n+1 1 is updated as In equation ( 16), by substituting I and I n+1 0 from equation ( 14) we get where, and A 2 = ∆t ∆z C −1 .Similarly, at the far-end terminal (k = N z +1), the nodal equation of the load current (I N z+1 ) is given by The final iterative equation at the far-end terminal is given by where, In continuation with the algorithm, to derive and update the iterative equations, some term indices exceed the index range for all nodes between the terminal, therefore a truncation method is employed.Taking V n+1 k as an example for k = 2, 3, . . ., S b and following the steps of equation ( 9) and (10), we can decompose (7b) as . . .
From the equations (20a)-(20e), it can be observed that for the first k terms, the indices of the equations doesn't exceed the index range, whereas, all the equations for which the index terms exceed the index range appear in the rest S b − k terms.As S b − k terms go out-of-bounds, these equations are unavailable for forming iterative equations in MRTD method.To avoid this problem, a truncation is made in the equations where the index range is exceeding.
By summing up the first k terms in equations (20a)-(20e), we can obtain the modified iterative equa- Using the same steps illustrated in equations (20a)−(20e), a modified iterative equations of voltages at interior points as shown in equation ( 22) and voltages near the load as shown in equation ( 23).
The iterative equations of current can be updated by following the same steps of voltage iterative equations with a slight difference.As shown in Fig. 3, it is observed that the current nodes appear at the half-integer points, which means that all the currents are located at the interior points of terminals.So, the currents near the terminals need to be modified.
For the iterative equations of current near the terminals, we need to decompose (7a) by using the steps from voltage iterative equations.The final modified current iterative equations are obtained as for k = 1, near the source for k = 2, 3, for equations at interior points are A bootstrapping approach is used for evaluating the updated voltage and current iterative equations.Foremost, the voltage iterative equations are solved at fixed time using equations ( 17), ( 19), ( 21)-( 23) in terms of past values of voltages and currents.Thereafter, the iterative equations of currents are solved from equations ( 24)-( 27) in terms of voltages evaluated initially and past values of currents.So, to get the stable output for the MRTD iterative equations, the courant stability condition [18], [20] is considered as which states that the propagation time must be greater than the time step, over each cell.where q is a Courant number given by q = = ϑ∆t ∆z and ϑ is the phase velocity of propagation on the line.

Simulation Setup and Validation of Results
The proposed MRTD method is validated in HSPICE using W-element method and compared with the conventional FDTD method.The coupled interconnect lines are driven using symmetric CMOS drivers.To maintain the symmetry in operation of CMOS inverter, the aspect ratio of W p to W n is chosen to be 2 : 1, with the width of pMOS (W p ) is chosen to be 3.2 µm.A ramp signal falling from 0.9 V(V DD ) to 0 V with a transition time of 10 ps, is given as an input to the CMOS driver of aggressor line.The technology used is 32-nm with thickness and width of the interconnect line as 0.66 µm and 0.22 µm respectively, with an aspect ratio of 3:1 [9].The height from the ground plane is considered to be equal to the thickness of the interconnect line and the spacing between the two interconnect lines is assumed to be equal to its width.The global level interconnect length, load capacitance and inter-layer metal-insulator dielectric constant of the line are 1 mm, 2 fF and 2.2 respectively.The line parasitics extracted using the setup mentioned above are shown in Tab. 3.
The corresponding mode velocities, for given line parasitics, are calculated as odd mode velocity ϑ o = 1.71 × 10 8 m/s and even mode velocity ϑ e = 1.45 × 10 8 m/s.To obtain high accuracy, the value of space discretization (∆z) is computed to be less than 0.46 mm, by considering break frequency of 32 GHz and even mode velocity.The time discretization (∆t) value is calculated to be 1.869 ps by using the value of (∆z) and odd mode velocity for the Courant number q = 0.7.

Transient Analysis of Coupled Two Interconnect Lines
The analysis of inclusive crosstalk noise at far-end terminal of the victim line is performed using, HSPICE, conventional FDTD method and the proposed MRTD method.The transient response of switching of functional crosstalk and dynamic in-phase as well as out-phase crosstalk, are illustrated in Figs.4a-4c.For functional crosstalk, the victim line remains at ground level, whereas, the aggressor line makes a transition from the ground to V DD .For dynamic in-phase crosstalk, the switching from ground to V DD takes place in both aggressor and victim lines.Finally, the transition takes place from V DD to ground and ground to V DD in aggressor and victim lines, respectively for dynamic out-phase crosstalk.It is observed from Fig. 4 that the proposed MRTD method dominates the existing conventional FDTD method and is in good agreement with HSPICE.Table 4 presents the computational error in predicting the crosstalk induced peak voltage and timing, on quiescent victim line, using the proposed MRTD model and the conventional FDTD, with respect to HSPICE simulations.The percentage error can be calculated for the methods (M) with respect to HSPICE (H) by using the equation (29).

% age error
The model is tested for the robustness at different input transition times.It is observed from Tab. 4 that, for the proposed model, the average error in prediction of crosstalk peak voltage is 0.14 % when compared to that of 2.7 % for conventional FDTD method.It can also be inferred from the Tab. 4 that the peak noise timing is well predicted using proposed model with average error of 1.9 % when compared to that of 2.8 % using the conventional FDTD method.

Transient Analysis of Three Mutually Coupled Interconnect Lines
Further, the proposed MRTD method is extended to three-coupled interconnect lines as illustrated in Fig. 5 and it is validated using HSPICE (W-element).The interconnect line parasitics for the analysis of the crosstalk of threecoupled lines can be extracted using the setup described in Sec. 3.  The coupling capacitance between the two aggressor lines can be neglected safely as the spacing between them is large [21].
The comparison of the transient response of crosstalk switching on victim line for three-coupled interconnect lines between the proposed MRTD method, HSPICE and the conventional FDTD method for two different test cases are illustrated in Fig. 6.It is observed that the proposed MRTD method is in good agreement with the HSPICE simulation results.From Figs. 6a and 6b it is also observed that a peak is resulted in the response using the conventional FDTD method due to its numerical dispersion properties.However, the proposed MRTD method with its great advantages in numerical dispersion properties [14]- [17] dominates over the conventional FDTD method with respect to accuracy.Table 5 presents the computational error involved in predicting the crosstalk induced 50 % delay on victim line due to aggressor lines using the proposed MRTD method and the conventional FDTD method with respect to HSPICE.Table 5 shows that the proposed model has an average error less than 1 %, whereas, the conventional FDTD method has an average error more than 3 %.
The elapsed CPU time for the proposed MRTD method, the conventional FDTD method and the HSPICE (W-Element method) is determined using the Intel Core i7 -3770 CPU (3.40 GHz).Table 6 shows the corresponding elapsed CPU times of each method.It is observed that both MRTD and conventional FDTD methods are faster than HSPICE with respect to simulation time, conventional FDTD being slightly faster than the proposed MRTD, since it requires slightly more number of iterations than conventional FDTD.Therefore, there is a trade-off between accuracy and simulation time.
1. C d and C m are the parasitic capacitance of CMOS, where C d represents drain diffusion capacitance and C m represents gate-to-drain coupling capacitance.Where R x is the line resistance per unit length (p.u.l.), L x is line inductance p.u.l.C x is line capacitance p.u.l.The subscript x represents aggressor line at x = 1 and victim line at x = 2. C L is the load capacitance.The interconnect lines are coupled inductively M C and capacitively C C .
of the current expansion in terms of scaling functions.The indices k and n are the discrete spatial and temporal indices related to space and time coordinates via z = k∆z and t = n∆t.

Fig. 4 .
Fig. 4. Transient response at the far-end terminal of the victim line during the switching of (a) functional crosstalk (b) dynamic in-phase and (c) dynamic out-phase crosstalk.
of pMOS and nMOS transistors are listed in Tab. 2 for 32-nm technology node.
Computational error involved for peak crosstalk noise and peak noise timing on victim line (conv.*-conventional).