Guidelines on the Switch Transistors Sizing Using the Symbolic Description for the Cross-Coupled Charge Pump

This paper presents a symbolic description of the design process of the switch transistors for the cross-coupled charge pump applications. Discrete-time analog circuits are usually designed by the numerical algorithms in the professional simulator software which can be an extremely timeconsuming process in contrast to described analytical procedure. The significant part of the pumping losses is caused by the reverse current through the switch transistors due to the continuous-time voltage change on the main capacitors. The design process is based on the analytical expression of the time response characteristics of the pump stage as an analog systemwith using BSIMmodel equations. Themain benefit of the article is the analytical transistors sizing formula so that the maximum voltage gain is achieved. The diode transistor is dimensioned for the pump requirements, as the maximal pump output ripple voltage, current, etc. The characteristics of the proposed circuit have been verified by simulation in ELDO Spice. Results are valid for N-stage charge pump and also applicable for other model equations as PSP, EKV.


Introduction
Charge pumps are switched-capacitor circuits that transport charge between main capacitors to create a higher output voltage.They are used to supply low-power circuits that require relatively high input voltage, for example, EEPROM memories.
The advanced architectures of the modern integrated two-phase charge pump are based on the elimination of the threshold voltage of the active components (Dickson charge pump [1]), that decreases all node voltages.The static charge pumps [2][3][4] realize the charge transport through the switch transistors, which are controlled by the output voltage from the next stage as is shown in Fig. 1.When the logic levels of the two-phase clock signal are φ = 0 (low) and φ = V DD (high) and assuming the correct function of the charge pump, then switch transistor M S1 is fully ON, node voltages V i−1 and V i+1 are pumped up to 2V DD and 3V DD respectively, and main capacitor connected to node i is charged to 2V DD .The voltage drop between two nodes is theoretically determined by the saturation voltage of the switch (MOSFET) at the end of the charge transport.Conversely, when φ = V DD and φ = 0, M S1 must be OFF [4], so that capacitor connected to node i can be pumped up to 2V DD and forward charge transport between nodes i and i + 1 can be realized.The problem of the reverse current occurs at the same time (φ = V DD and φ = 0) because the voltage difference v inv − v i−1 may be higher than threshold voltage V TH MS1 .Now, the MOSFET electrodes Drain and Source are mutually exchanged and M S1 is not OFF in spite of the expectation.
The discharge-reverse current i R , which flows through the switch is undesirable because it decreases the pump voltage gain.The reverse current of the diode transistor is practically zero.The cross-coupled charge pump contains the inverter that controls the switch at the time intervals defined by the clock signal.This topology allows achieving higher efficiency compared with the static charge pump.However, the problem of reverse current still exists [4], [5].
Simulation results show a strong dependence of the pump voltage gain on the strength of the switch transistor(s).Design of discrete-time analog circuits including charge pump circuits represent the fundamental problem, which relates to the solution of the part steps of the design algorithm.The following three key steps are necessary for a successful design: circuit model, simulation and evaluation of the simulation results.Only transient analyses are allowable.It is a fundamental difference of approach compared to analog circuits [5].The experimental part including simulation of real properties of the cross-coupled charge pump [5] and their comparison with other architectures (Dickson charge pump, a static charge pump) has been done [1][2][3][4], [6], [7].However, a design process of the circuit has not been known yet.General description methods of discrete-time analog circuits have been published in many books and research papers [5], [8], [9].Well-known description methods are insufficient because they do not consider the relevant properties (nonidealized structure), that are typical for the behavior of the charge pumps.Optimization is usually circuitous process due to many iterations to achieve of the required parameters (static, dynamic).The different access to solve this task will be offered in this article.The symbolic description of the design process of the cross-coupled charge pump stage as an analog block for high-voltage application will be discussed to find an analytical expression for width and length of the diode and switch transistors so that the voltage gain of the N-stage pump will be maximal.The pump elements (switch, diode, capacitors,..) usually have same parameters at all pump stages.Long channel MOSFET is provided due to high bias voltages (drain-source) in the circuit.Sizing of the switch transistor will be designed so that the reverse current will be suppressed.Sizing of the diode transistor is related to the optimization of pump parameters such as maximation of the load current, minimalization of the output ripple voltage.
The DC characteristics of the pump stage will be firstly found.Because the transistors are operating in strong inversion region, the simplified BSIM model [10] can be used for this purpose.The main part contains an analytical description of the time response characteristics, which are applied in the real circuit.The switch transistors ratio W s /L s is set, so that their equivalent resistance value is a compromise between the charge/forward and discharge/reverse current.The ratio is calculated for the worst case of bias voltages because this resistance is nonlinear.The equivalent diode resistance is determined by the change of the pump output voltage.The derived formulas are verified by simulation in ELDO Spice.The effort is to find mentioned solution without using the numerical optimization procedure.The created model including the dominant real properties points to an alternative way to N-stages charge pump draft (static, dynamic parameters).The strong inversion operating region of the MOSFET is expected, in which the behavior of the MOSFET models is correct [11] compared with the real measured curves (BSIM, EKV, PSP, etc.) in the specified technology process.

The Static Model of the Pump Stage
One stage of the cross-coupled charge pump is shown in Fig. 2. The drain current of the each MOS-FETs is controlled by the input voltage V in .Adjustable DC source voltage is used for analysis instead of the main capacitor in real circuits.
All other DC voltages in the diagram are referenced to the ground.It is supposed that all transistors are operating in strong inversion region.Hence, the power supply range of the inverter must be adequately high to turn on both of the transistors M Ni and M Pi in the interval V in ∈ V IL ,V IH , see Fig. 3. Pump voltage gain of two stages labeled G v = V 1 − V 2 , must be greater than the sum of the threshold voltages of these transistors, labeled V TH MNi , V TH MPi .The switch transistor must be ON, when the output inverter is at a high logic level, i.e.
The output voltage of the inverter V inv = f(V in ) is setting the drain current of the switch transistor M Si , labeled I S .The CMOS inverter voltage transfer characteristic [12][13][14] is derived based on the fact that the drain current of both MOSFETs must be equal for each of the operating regions.
The complex expression of the voltage transfer characteristics is not necessary for the practical results.Considering the electrical field in structure is much less than critical electrical field [10], then "long channel" can be defined as where L eff is the effective channel length [10], [12], V max is the maximal bias voltage (drain-source, gate-source), µ eff is effective mobility and v sat is the saturation velocity [10].
Then, the transfer part of the characteristics is well linearized, as it is shown in Fig. 3. Input voltages between the limit values V IL and V IH do not define the valid output logic level [12].Inverter cross current I cross is the maximal in the switching point when V IN = V inv [12].Analytical equation of V SP is derived in [5].Now, an analytical estimation of the voltage transfer characteristics has the following form: The slope of the transition part is determined by the Early voltage of MOSFETs, V ADIBL , which is proportional to the voltage V GS and relationship only contains the model parameters of PDIBLC2 and PDIBLCB [10].
So that, difference V IH − V IL is very small, V IL → V SP , V IH → V SP and the wide of the transition part is negligibly small (zero in the ideal case).
The voltage on the capacitor is changing continuously from 0 to the supply voltage V 2 in the passive time interval and the voltage at the terminal "IN" may be theoretically doubled in the active interval of the clock signal, i.e.V IN = 2V 2 .Thus, the drain current I S through the switch transistor M Si (and its orientation) will be analyzed in the interval of the input voltage V in ∈ 0,V 1 (the D,S pins of the switch transistor are not distinguished in the scheme).The direction of the forward-"charging" current (that is required) matches the orientation in the scheme.The control voltages configuration for the setting both the forward (I S F ) and reverse current of the drain (I S R ) of the M Si transistor are shown in Tab 1.

Parameter
Value Respecting the condition (1), transistor M Si is always ON in the interval V in ∈ 0,V 2 ).The bulk both of the M Ni and M Si transistors is connected to the same bias voltage V BN (usually to the ground) and in the same technology process.Moreover, this transistor is operating in the triode region, as it is shown bellow.In this case, the condition V DS < V DS sat is valid, where the saturation voltage is calculated from [10], [15] V Substituting the specific values from Tab. 1 into the V DS sat expression, following inequality is obtained: Expression on the right hand sight of ( 5) must also satisfy the condition (1).Considering the worst case of the threshold voltage, V TH MSi = V TH MNi , then Saturation voltage V DS sat can be approximated by the function V GS − V TH near the point V GS = V TH (long channel MOSFET is provided).However, real saturation voltage is greater than function expressed in (4) for higher voltage V GS , V DS sat > V GS − V TH , i.e.A bulk < 1, for V GS V TH .Subsequently, the inequality ( 6) is always true.
The drain current direction is changed, and it is controlled by the constant gate-source voltage The gate-source voltage decreasing quickly in the interval V IL ,V IH , while a change of the drain-source voltage is negligible.Hence, the drain current achieves the maximal value at point V IL and transistor is abruptly switched off after exceeding the switching point.Neglecting the transition part of the inverter transfer characteristic, drain current can be considered the constant in the interval V in ∈ V IL ,V SP .Total current I S is given by the following formula: Current I S R is calculated on the basis of the two following cases: • if where I DS0 is the drain current in triode region and I D sat0 is the drain current in saturation region at V DS = V DS sat .The reverse current waveform for the both cases is shown in Fig. 4. The source-bulk voltage is the parameter.
The drain current of the M Di transistor is zero in the reverse configuration due to shorted gate and source electrodes,

Time Response Characteristics
Step response is a typical characteristic situation in the switched-capacitor circuits.
Step response characteristics of the circuits are shown in Fig. 6 and 8.The time-varying voltage on the main capacitor to the clock signal will be found for both the forward and reverse configuration to determining pumping losses.The extreme values of the bias voltage have been chosen for the following optimization process.The time domain method must be used for the calculation due to the nonlinearity behavior of this system.It is also necessary to define the next conditions for the analysis process: • parasitic capacitances are negligibly small compared with the main pumping capacitors, C s C i .
• rise time and fall time delay of the clock signal and propagation delays of the inverter are very short compared to the charge/discharge time of the main capacitors.
• leakage currents of all the components are neglected.
• settling time of the switches is zero.
The main capacitor is charged, when the gate of the switch transistor is connected to high output voltage level of the inverter V inv = "H" = V 1 , the drain is connected to the input stage voltage V 2 and the main capacitor is connected to ground.This situation is shown in Fig. 5.
When the switches S 1 , S 2 and S 3 are ON at t = 0, the current flowing through the capacitors i c F is supplied both of the transistor until the capacitor voltage does not exceed the value V 0 F at time t 0 F , see Fig. 5.Total current i c F is given by  The voltage on the capacitor is equal to V 2 in steady state and the particular value of the voltage V 0 F can be derived from where source-bias voltage is equal to v c F (V BN = 0).Dependence of the threshold voltage on the V SB voltage (body effect [10], [12], [13], [15]) is given by where V TH0 is threshold voltage at zero bias voltages, φ s is the surface potential and K 1 , K 2 are body effect coefficients (model parameters).Combining ( 12) and ( 13), the instantaneous value of the voltage in which the transistor M Di will be OFF, is calculated from where Substituting the voltage v cF in the static model for V in and using equations for the drain current [10], [12], [13], [15], time response characteristic is found by the solving of following differential equation with the initial condition v c (t 0 ) = v c 0 for each of the intervals, as it is shown in (11).The drain current equation is the composite function (NF) in the form consequently, the analytical solution would be unreasonably complicated for practical design.Thus, the estimation is done providing the constant nested functions v TH ,A bulk and µ eff according this criteria: When t ≤ t 0 F , the voltage v c F change in time is approximately same as at the beginning of the transient process.Contrariwise, when t > t 0 F and i D = 0 the characteristic curve is approximated by the nested function values which would acquire in the steady state.
The same principle is also used for the reverse configuration, as it is shown in Fig. 7. Bias voltages are listed in Tab. 2.

Condition
Index of NF.
Tab. 2. Bias voltages of the nested functions (NF) V TH , A bulk and u eff .
Therefore, solving of ( 15) can be only found by integrating the voltage square [v gs (t) − V TH ] 2 , eventually v ds (t) and v 2 ds (t) for triode region.The time-varying voltage v C F for the forward configuration is given by where L is channel length and c oxe is electrical oxide capacitance.Integration constants, labeled IC 1 and IC 2 , are generally calculated from the initial conditions that are substituted into (15) -Cauchy's equation: where ζ = Using the voltage V 0 F in (18), the initial time t 0 F is given by Discharge of the main capacitor is shown in Fig. 7.The CMOS inverter is modeled by the voltage source BV controlled by the time-varying voltage v cR .The switch transistor is ON after the switches S 1 , S 2 , S 3 are closed at t = 0 and the capacitor C i was charged on the value in the interval of the voltages v C R (0) ∈ (V 2 ,V SP ).
The initial condition v C R (0) ∈ (V IL ,V SP ) will be considered to a complete description of time response characteristics.Then, the main capacitor is firstly discharged by the constant current I S until the voltage of BV achieves V 1 at time Value of the constant current I S R for V in = v c R (0 + ) follows from the static model, parameters for i s (t) are mentioned in Tab. 2 (index SR).
The default differential equation for each of the time interval is the same as in the previous case, Because the voltages are equal to V 2 in steady state for both the configurations, the coefficients in the exponential functions are also the same.The integration constant IC R can be easily expressed as and the point t 0 R is given by

Minimization of the Pumping Losses
The sizing of the switch transistor will be discussed in this part.The main criterion of the optimal pump design is based on the maximum voltage gain at the end of each phase of the clock signal, as it is shown in Fig. 9. Sizing of the switch transistor M Si can be set, so that the voltage gain is greater than 2V 2 , better V max at point T/2.The transistor length is determined from condition (2) and the width is determined based on the following condition: The optimal width W MS opt will be searched while using the limit initial conditions to satisfy the worst case that can be taken into account in the real circuit.Using the condition (24) and ( 16), (21) then the following equality is true: and it is giving desired value of the width at the known clock frequency.However, the optimal point can be estimated even in a simpler way.Both the time response characteristics v C F (t) and v C R (t) in the intervals t > t 0 F and t > t 0 R are compared to each other via its linearization in the initial time, as it is shown in Fig. 10.  the linear change voltage as in the initial time, the transient process would be terminated at time τ.This parameter is equivalent to the time constant, but it is a function of the bias voltages (is not constant), unlike the first order linear systems.It is derived from the first order Taylor approximation, If the capacitor is charged from the initial value v c (t 0 ) to value in the steady state v c ∞ , then the voltage on the capacitor reaches the value The increase of the pump stage voltage must not fall bellow the value ∆V max ≥ V 2 during half of the period, as it is shown in Fig. 7. Discharge time through the parameter τ R primarily determines the amount of the pumping losses and τ R > τ F , thus Thence the parameter α is given by Parameter τ R can be calculated from (26), however it is approximately given by the reverse current Using the condition (27) and respecting the time value t 0 F from (19), in which the M D i transistor is OFF, then the found width W M S opt is given by where Parameter k is selected from Tab. 3 based on the parameter α from (28), ÎS R is the drain current calculated for the unity width ÎS R = I SR /W .
In case the multiple of the time constant satisfies the session kτ R t 0 F , (30) now becomes to

Sizing of the "Diode" Transistor
Analysis results show that dynamic properties are not practically dependent on the sizing of the transistor M D i in the wide range of the ratio W /L. It only needs to be adequately dimensioned for the pump output load current L in steady state.After the clock signal φ goes to H logic level (corresponds to V DD ), the output voltage starts from the initial value V out,av − V r /2 and can theoretically achieve the maximum value V out,max during T/2.V out,av is the required average value of the output voltage and V r is the peak value of the ripple voltage.The situation is shown in Fig. 11.The transistor M D N +1 is on in the active interval of the clock signal.
Time response characteristics will be firstly determined.Providing the capacitive character of the load impedance, the state description of the voltage on the capacitor v out,av (t) is in an accordance to (15) (R L → ∞).The step response characteristics of the circuit in Fig. 12 after closed S at t=0, when the capacitor is charged from the initial value v c (0 + ) = v c 0 to the steady state v c ∞ , is given by The maximal output voltage value v c ∞ is equal to V 0F from ( 14) and β factor is calculated at the bias voltages in steady state, The increase of voltage α D at time expressed as the multiples The optimal width of the M D transistor is determined from a condition, that the voltage v out from Fig. 11 must achieve the maximal allowable ripple voltage V r during T/2 at the desired average value of the output voltage.The maximal output voltage V out,max is calculated from (32), into which the concrete values are substituted for input voltage V 2 , Of course, the specified amplitude of the AC voltage value v r (t) depends on both the external load R L , C L and on the equivalent internal pump impedance including R pump , C pump .Consequently, the following inequality must be true: Therefore, where pump capacitance may be neglected, provided C L C pump and α ≥ with the minimal value of the average voltage V out,av .However, parameter α D should be chosen, so that the load capacitor was charged by the large current all along of the active interval.Consequently, the transistor is fully switched on (v gs v TH , strong inversion) and the load voltage is the approximately linear function of time.Results from Tab. 4 show that significant voltage change meets this assumption for α, which no exceeding the value about 0.7.Otherwise, the width quickly grows with α → 1 despite the improvement of dynamic properties.An example of the width calculation vs. α parameter is shown in Tab. 5.

Experimental Part
The real circuits properties were simulated in the professional environment ELDO Spice, Design Architect-IC v2008.2_16.4.All assertions from the previous parts were be verified in the three-stages charge pump including the real models of all the components.Firstly, the equation validity expressing the optimal point W s /L s (Fig. 13) will be tested via the comparison of the calculated functional values 16), (21) and the pump output voltage value V out,av dependending on the ratio W s /L s .The optimal width calculated from simplified (31) is listed in the last line.Setting of the voltages V 1 , V 2 and source-bulk bias voltage of the N/PMOS for the calculation must first be resolved.Starting from the fact, that the maximal output voltage value with a change of the circuit parameters (clock frequency, main capacitances, etc.) is achieved, just when the voltage gain of the first pump stage is maximal (it decreases with increasing the number of stages).In accordance to situation in Fig. 1, power supplies of the pump stage (Fig. 2) are V 2 = V DD , V 1 = 2V DD .The bulk of the NMOS is connected to ground (V SB N = V DD ) and bulk of the PMOS is selected so that the inverter switching point was the maximum (at the constant setting of the inverter transistors sizing).Using the definition V SP [12], [15], then V BS P = 0 (in the last pump stage).As a consequence, the worst case of the V SP voltage, labeled V SP max in the N-stages pump is taken into account.Then, general formula of the V SP max V B P = V B N = 0 can be written as, Example calculation of the switch transistor width for practical design will be shown in the following part.The charge pump parameters from Tab. 6 will be considered and: T = 100 ns, V Bn = 0, V Bp = 0. Channel length is same for all the transistors.• the maximal inverter switching point [5] at appropriate bias voltage values

Parameter
• The drain current value in the specicific technology process and for unity width is • finally, the switch transistors width calculated from (31) is equal to The results correspond with data from Tab. 6.They show that the pump output voltage is maximal (bold) if the time response characteristic of the pump stage at time T/2 does not exceed the value V max , as it is shown in Fig. 9.The optimal width W M s must be less than the calculated value from (30), (31), otherwise, the pumping losses cause the discontinuous decrease of the output voltage due to the opening the feedback of the system (the condition 1 is not satisfied).It is a critical parameter from the view of the design process.
Conversely, the voltage gain is not changed in a wide ratio range W D /L D of the diode transistor, as it is shown in Fig. 14.

Conclusion
Guidelines on the design of the switch and "diode" transistors for the cross-coupled charge pump architecture without using long-time iteration process was presented in this paper.The symbolic description was used for calculation.The equivalent channel MOSFETs resistance was designed, so that the voltage gain and power efficiency were maximal.Analytical formulas are including the extreme values of circuit bias voltages to achieve satisfactory results in N-stage architecture, in which these types of the transistors have same dimensions in each of the stages.All the results were verified by the professional simulation software ELDO.
The switch and diode MOSFETs channel length was determined based on the critical electrical field in structure (breakdown voltage and maximal Drain-source voltage), see (2).The width of the switch and "diode" transistor were determined based on the analytical expression of the time response characteristics of the pump stage as an analog block.Switch transistors width, see (30), (31), was found using the criteria of the maximal difference between forward/charge and reverse/discharge current during the period of the clock signal.The ratio W s /L s , in which the sum of the time characteristics (reverse+forward) of the pump stage achieve the maximum value was compared with results fort three-stage pump, see Tab. 7. Compliance between both of the values is obvious.Simulation results show that switch resistance cannot be very small because increasing the ratio W/L, the reverse switch current decreases pump efficiency.This ratio can be less than one at the extreme values of input parameters (power supply, clock frequency).Exceeding the critical value of the reverse current, the pump output voltage is discontinuously decreased (see Fig. 13) because the basic condition (1) is not valid.This is an important practical result.
An estimation of the minimal width of the diode transistors W D , see (35), is possible to determine from the requirements on the output load current and the output ripple voltage.Static and dynamic properties of the pump are quite stable over a wide range of the ratio W D /L D , see Fig. 14.Reverse current through the diode transistor is practically zero.

Fig. 1 .
Fig. 1.Reverse current through the switch transistor in the crosscoupled charge pump.

Fig. 3 .
Fig. 3.The voltage transfer characteristics of the CMOS inverterfor long channel MOSFET and its linearization.

Fig. 4 .
Fig. 4. Reverse current of the switch transistor vs. input voltage.

Fig. 5 .
Fig. 5. Configuration for the charge of the main capacitor.

Fig. 7 .
Fig. 7. Configuration for the discharge of the main capacitor

Fig. 8 .
Fig. 8. Time response characteristics of the circuit from Fig. 7. Coefficients C 1 , C 2 , C 3 , C 4 and C 5 are calculated from:

Fig.
Fig. Linearization of the time response characteristics.

Tab. 3 .
0 during time t = kτ.Parameters 1 > α > 0 and k ≥ 0 are multiple constants.The specific values of α and k parameters calculated for exponential function of v C R (t), are shown in Tab. 3. Relationship between parameters k and α calculated from (16).

Fig. 11 .
Fig. 11.The last stage of the charge pump and waveform of the output voltage in the steady state.

Fig. 13 .
Fig. 13.Pump output voltage vs. the ratio W s /L s .

Fig. 14 .
Fig. 14.Pump output voltage vs. the ratio W D /L D .
Si , M N i , M Pi and M D i are the same sized in each the pump stage.Simulation parameters (unless noticed otherwise) are specified in Tab. 6.