A 28-nm 32 Kb SRAM For Low-V MIN Applications Using Write and Read Assist Techniques

Abstract. In this paper new write and read assist techniques, reduced coupling signal negative bitline (RCS-NBL) and low power disturbance noise reduction (LP-DNR) of 6T static random-access memory (SRAM) to improve its minimal supply voltage (VMIN), have been presented. To observe the improvements in VMIN and power consumption of SRAM with the help of proposed assist techniques, a 32Kb capacity SRAM, with 128 words of 256 bits width, is designed and simulated in 28-nm bulk CMOS technology. New RCSNBL scheme, shows an improvement in SRAM write VMIN by 295mV and also reduces overstress on pass transistor (PG) of the selected bitcell by 40mV. Proposed LP-DNR scheme demonstrates an improvement in SRAM read VMIN by 35mV and also shows a saving of the power loss in the existing DNR scheme during the read access which occurs due to continuous flow of current from the cross coupled latch to the discharge block path after the bitlines have settled. The static power consumption of this SRAMmacro is improved by 48.9% and 11.7%while dynamic power by 91.7% and 8.1% with the help of proposed write and read assist techniques respectively. Area overheads of these proposed RCS-NBL and LP-DNR assist techniques for this macro are less than 0.79% and 3.70% respectively.


Introduction
In advanced nanometer CMOS technologies, reduction of minimal supply voltage (V MIN ) and chip-area are the primary concerns of SRAM design.The reduction in V MIN of the SRAM cell for scaled devices is limited because of the local threshold voltage variations resulting from random dopant fluctuations and lithographic-dependent patterns have been increasing [1].Also, with the increased threshold voltage variations in scaled transistors the access-disturbance margin (ADM) [2] and write margin (WM) [3] of the SRAM bitcell have been degrading.Process variations make SRAM design less predictable and controllable, moreover the SRAM design space in terms of prediction and control degrades further as supply voltage (V DD ) scales down [5].Meanwhile, to improve the data stability of the bitcell, dual supply voltage schemes have been suggested [6], [7].These schemes use higher supply voltage for bitcell array and lower supply voltage for peripheral blocks to improve the ADM of an SRAM.Write margin (WM) of an SRAM bitcell, has been improved by pushing selected bitline to negative voltage or by decreasing the cell voltage [2].Now a days SRAM read and write assist techniques are widely used approaches to lower the V MIN of an SRAM [8].Firstly, with the help of read and write assist techniques SRAM stability and write ability have been increased from their minimum respective levels required for proper read and write in SRAM without any assist techniques, which allows us to reduce the corresponding SRAM V MIN until the SRAM stability and write ability touch their respective original levels.In this paper, we present 28-nm bulk CMOS technology based 32 Kb 6T SRAM, featuring low V MIN with new write and read assist techniques.The focus has been to reduce the V MIN of SRAM since it is one of the most effective approaches to reduce dynamic as well as static power of SRAM.
Remaining part of this paper is organized as follows.Section 2 describes the conventional SRAM assist schemes.Section 3 elaborates the proposed reduced coupling signal negative bitline (RCS-NBL) scheme.Section 4 discusses the proposed low power disturbance noise reduction (LP-DNR) scheme.Section 5 deals with the impact of process variation on various SRAM parameters.Section 6 demonstrates the implementation and simulation results.Finally, we conclude in Sec. 7.

SRAM Assist Schemes
As shown in Fig. 1 conventional SRAM assist techniques are categorized into write and read assist schemes.

Write Assist Schemes
The techniques which aid the bitcell in changing the state during write operation are called write assist techniques and now these techniques are widely used in most low power SRAMs.The basic idea behind the write assist scheme is to decrease the ratio of strength of pull-up transitor to pass transistor of an SRAM cell when the wordline (WL) of the cell is enabled for write operation.
Conventional SRAM write assist schemes are categorized into following four techniques depending on the approach used to lower the ratio of pull-up to pass transistor strength of an SRAM cell during the write operation.Negative bitline (NBL) scheme, Wordline overdrive (WLOD) scheme, Lowering cell V DD voltage (V DDCELL ) (LCV) scheme [2] and Raising cell ground voltage (V SSCELL ) (RCGV) scheme.Figure 1(a) shows the schematic of an 6T SRAM bitcell and Fig. 1(b) shows these conventional write assist techniques to enhance the write ability of the SRAM bitcell.In NBL scheme the selected bitline is pushed to negative voltage during write operation, which results in an increase of V GS of the corresponding pass transistor hence the strength of this pass transistor has been enhanced, this improves the WM of the cell.While in WLOD scheme the strength of pass transistor is increased by boosting the WL voltage i.e. the gate voltage of the pass transistor.In LCV scheme, the strength of pull-up device is reduced by lowering the source voltage (V DDCELL ) of pull-up devices while keeping wordline voltage (V WL ) at V DD.In RCGV scheme also, the same idea is used to weaken the pull-up device, but in this case it is achieved by weakening the pull-up gate voltage instead of the source voltage, which is realized by raising the V SSCELL , during the write operation.

Read Assist Schemes
The read disturb problem can be mitigated by adding a dedicated read port to isolate the bitcell internal nodes from the bitlines, but these resulting 7T, 8T, 9T and 10T SRAM bitcells [9][10][11][12][13] occupy larger area.The access-disturbance margin (ADM) can be improved by reducing the amount of charge injection from the pre-charged bitline to the '0' node of the active bitcell.This can be achieved by reducing the strength of pass transistor and/or bitline capacitance with slow WL rise [14], [15].Figure 1(c) shows conventional SRAM read assist scheme, WL underdrive (WLUD), used to improve the ADM of an SRAM bitcell by reducing the strength of the pass transistor.

Proposed Reduced Coupling Signal Negative Bitline Scheme
In this work, NBL technique is being used as write assist scheme, since this is the most effective technique to reduce the SRAM V MIN [16].Also, this technique shows highest WM without reducing the ADM of the half selected bitcells [2].To realize NBL write assist scheme, capacitive coupling signal (CCS) approach shown in Fig. 2(a) is being used, which generates negative voltage at the bitline supposed to get down for write operation.In this scheme ENB_NBL signal propagates to NBL_FIRE signal as the falling edge of ENB_NBL signal triggers the fall of NBL_FIRE signal from the voltage level it was sitting before.The NBL_FIRE signal is coupled to negative bias (NVSS) signal through capacitor C 1 .The pre-charged voltage level of NBL_FIRE signal before it starts to fall is one of the key parameters to determine the negative bias (NVSS) voltage level, which means that for higher V DD operation the generated voltage level of NVSS signal will be more negative.As shown in Fig. 3(a) with the help of write driver and column multiplexer, NVSS signal is applied to the selected bitline.Thus, coupling technique produces higher negative bitline bias level for higher V DD operation but there are two main disadvantages of higher negative voltage level at bitline, one stability concern of the half-selected bitcells in the same column and the other one is overstress on pass transistor of the selected bitcell, which is connected to this negative biased bitline, as for this pass transistor V GS is too large, and this overstress condition is also getting worse for high V DD operation [1].
To address these two issues, reduced coupling signal (RCS) circuit as shown in Fig. 2(b) is proposed here as write assist scheme.In this scheme, the voltage level of NBL_FIRE signal is reduced with the help of coupling voltage reduction block shown in this figure .With the reduction in voltage level of NBL_FIRE signal, the negative bias (NVSS) signal level is reduced and hence negative bitline voltage level is reduced.In this work, 32 Kb SRAM with column mux (CM) = 8 i.e. an SRAM with physical rows (PR)=128 and physical columns (PC)=256 has been simulated with CCS-NBL, proposed RCS-NBL and state of the art SCS-NBL [1] write assist schemes.In CM=8 configuration 8-columns of bitcells are muxed with single write driver and hence single write assist block as shown in Fig. 3(a).Simulated waveforms are plotted in Fig. 3 respectively.Figure 3(b) and 3(c) demonstrate that the negative voltage level of NVSS is reduced by 40 mV with the help of RCS-NBL scheme as well as SCS-NBL scheme, and which has resulted in reduction of negative bitline voltage by same amount, this reduction will be more significant for higher V DD operation.Thus RCS-NBL and SCS-NBL schemes ad-dress both the issues mentioned above.However, as shown in Fig. 3(c) proposed RCS-NBL scheme also improves the performance of write operation of the bitcell as compared to SCS-NBL scheme, because in this scheme the generation of NVSS signal can be triggered at the same time when CLKW signal rises from '0' to '1' while in the case of SCS-NBL scheme generation of NVSS signal will be initiated after ∆t time to get same assist level as in the case of RCS-NBL scheme.With 6σ process variation, simulation results shown in Fig. 4

Proposed Low Power Disturbance Noise Reduction (LP-DNR) Scheme
Read assist scheme WLUD improves the stability of half-selected bitcells but degrades both the read and write performances of selected bitcell [4].Further WLUD scheme also shows rise in access time of bitcell with reducing V MIN , then to improve the V MIN , disturbance noise reduction (DNR) scheme was proposed as read assist scheme [2].In this scheme, both the bitlines are lowered simultaneously, before the WL is activated to reduce the level of noise injection to the bitcell nodes, by discharging through clamping and discharge blocks.With lowering the bitlines voltage level at WL enabled time ADM increases to a certain level and thus the bitlines voltage level at which ADM is getting its maximum value, is defined as bitline safe-voltage level (V SAFE ).Process Variation(σ)

Minimum bitline voltage(V)
Minimum BL(V) provided by level P ) DNR block with rocess Variation(σ Fig. 6.Simulated minimum bitline voltage(V) at WL rise time with process variation(σ).
However, ADM degrades drastically as bitline voltage level goes below V SAFE [2]. Figure 5 shows the plot of simulated results of ADM versus bitline voltage level at WL enabled time with 6σ process variation for the bitcell being used in this work and these results also endorse the same trend of steep degradation of ADM with bitline voltage level below V SAFE .Thus to ensure enough data stability of the selected bitcells, proposed circuit must provide bitline voltage level at WL enable timing, more than or equal to V SAFE but not below it.Hence here for 6σ process variation cross-coupled latch, clamping and discharge circuits have been designed to keep bitline lowest voltage level to V SAFE .Figure 6 shows the simulated results of biltline voltage level provided by DNR block with process variation for V DD = 1.0 V.These results demonstrate that DNR block being used in this work is providing bitline voltage level which is more than or equal to V SAFE as indicated in Fig. 5.In DNR scheme, after the lowering of bitlines, as WL is activated bitcell read current (I Read ) from bitline to cell node storing '0' , in addition to bitline discharge current pulls down the corresponding bitline low enough to put ON one of the two PMOSs of cross-coupled latch for which this bitline is acting as its gate.Thus as per the action of cross-coupled latch, this bitline goes down to '0' and other one goes to (V SAFE +ΔV).PMOS which is ON keeps one of the two bitlines at (V SAFE +ΔV) for the period WL enabled time to the time at which the bitline is pre-charged to V DD again.For this period, pass transistor of the bitcell connected to the same bitline supplies current to it since this pass transistor is working very close to the subthreshold region.Thus, during this time period, a sum of PMOS ON current and pass transistor subtheshold current, I LOSS , is drawn from supply V DD and pushed to discharge block through the pair of clamping PMOS devices connected to the bitline settled at (V SAFE +ΔV).
To save this loss of power contributed by I LOSS , DNR circuit [2] has been modified and resulting circuit shown in Fig. 7(a) is proposed here as a new low power disturbance noise reduction (LP-DNR) read assist scheme.Fig. 7(b) shows the timing diagram of proposed LP-DNR circuit for an access operation of the bitcell.As shown in this figure after WL is enabled, I Read in addition to discharge current pulls the bitline BT enough low to turned-on PMOS P10 of I LOSS path shut-off circuit, subsequently shut-off signal is activated (shut-off='1') with LP_DNR='1'.Thus during SHUT_PCH window, active shut-off signal turns off P2 & P3 devices, which results in stop of the flow of I Loss but in case of DNR scheme this flow continues throughout SHUT_PCH window.In proposed LP-DNR scheme, as the flow of I LOSS is blocked by turning off P2 device, the bitline BB starts to charge towards V DD while BT remains at 0V, finally bitlines, BB & BT are synchronized with cell data, hence neither '1' noise nor '0' noise can inject to the cell which results in highest stability of the bitcell.Also, with this synchronization of bitlines with cell data the active current drawn from power supply V DD is diminished.

Impact of Process Variability
In modern technologies intrinsic device variability of scaled devices dominates the traditional (worst-case) overall process spread that is generally used to determine the design window for the digital design community [17].Transistor threshold voltage standard deviation σV T can be used to represent the intrinsic device variability, which is expressed as follows [18].
To simulate various SRAM parameters, with the impact of process variation, σV T for all the concerned devices have been obtained using (1).
The simulation results for 6.5σ weak bitcell, shown in Fig. 8 demostrate the need of LP-DNR circuit to combat the access disturbance of the cell.For SRAM read operation bitlines are pre-charged to V DD before the access of the cell, and access of the cell is obtained by turning ON pass transistors (PG1,PG2) of the cell by enabling WL. Figure 8(a) shows the simulated waveforms for read operation, as the bitcell is accessed, noise from BT will be injected to the cell storage node XT storing '0' data before this access of the cell, thus XT node voltage rises to the voltage level which is sufficient to flip the cell, which results in functional failure.Further, the required voltage level at XT to flip the cell is also degrading as the cell gets weaker due to process variation.Figure 8(b) shows that the bitlines are lowered by LP-DNR circuit before the access of the cell hence the level of noise injection from BT to bitcell node XT storing '0' data before the access of the cell, is reduced which results in successful read operation of the cell.
Simulation results shown in Fig. 9, demonstrate the improvement in read V MIN with the help of LP-DNR and DNR schemes respectively.In this figure, green curve shows the  minimum bitline voltage for non-destructive read operation of the cell, blue and red curves represent the bitline voltage level provided by LP-DNR and DNR schemes respectively.Here points A and B are representing SRAM read V MIN without and with read assist techniques, respectively.It can be observed from these results that with the help of both the proposed as well as the DNR scheme, SRAM read V MIN has improved by 35 mV.

Implementation and Simulation Results
In this paper, all the layouts have been carried out using Synopsys Custom Designer Layout Editor (CDLE) and verified for DRC and LVS checks using IC Validator for 28-nm CMOS technology node while the RC parasitic extraction has been done using Synopsys Tool STAR-RC for the same technology node.Layouts of 6T SRAM bitcell as well as 3×3 miniarray are shown in Fig. 10 13.To get the loading netlist for this SRAM instance each bitcell in array is replaced by its extracted netlist deduced from miniarray as discussed above.To observe the impact of proposed assist schemes with respect to no assist circuits and with assist circuits, extracted netlists for existing assist circuits, CCS and DNR have been used.For the proposed assist circuits RCS-NBL and LP-DNR, extracted netlists of the respective blocks have been used.

Fig. 10 .Fig. 11 .
Fig. 10.Layout of 6T SRAM bitcell (a).Layout of 3×3 miniarray for 6T SRAM cell (b).X=1.689µm (a) and (b).Parasitics of centred 6T-SRAM bitcell of miniarray have been deduced from the extracted netlist of miniarray.Fig-ures 11(a) and (b) show the layouts of capacitive coupling signal (CCS) circuit and proposed reduced coupling signal (RCS) circuit respectively.Layouts of DNR and LP-DNR circuits are as shown in Fig. 12(a) and (b).In this work, the simulation setup for 32 Kb SRAM with CM=8 , is made using center decode architecture as shown in Fig.

Figure 14 Tab. 1 .
Figure14depicts the sigma-qualification of SRAM.In this figure, red square, blue dot and green rhombus represent SRAM V MIN to qualify for a particular level of process variation(σ) for no write assist scheme, with proposed write assist scheme (RCS-NBL) and for retention mode, respectively.Power numbers along with V MIN of above mentioned SRAM macro, collected with the help of simulations, for respective write assist and read assist schemes as well as without assist schemes are shown in Tab. 1 (a) and (b) respectively.SCHEME V (V)MIN demonstrate the improvement in SRAM write V MIN with NBL techniques.In this figure, blue plot shows the required bitline voltage to write the bitcell, red, green and black plots represent coupled NBL voltage levels with CCS-NBL, proposed RCS-NBL and SCS-NBL techniques, respectively.Points A and B represent SRAM write V MIN without and with write assist techniques respectively.It can be observed from this figure that the proposed RCS-NBL as well as the SCS-NBL write assist technique demonstrate improvement in SRAM write V MIN by 295 mV.