High-Precision CMOS Analog Computational Circuits Based on a New Linearly Tunable OTA

Implementation of CMOS current-mode analog computational circuits are presented in this paper. A new Linearly Tunable OTA is employed in a modified structure as a basic building block for implementation of the circuits either linear or nonlinear functions. The proposed transconductance amplifier provides a constant Gm over a wide range of input voltage which allows the implementation of high precision computational circuits including square rooting, squaring, multiplication and division functions. Layout pattern of the proposed circuit confirms that the circuit can be implemented in 102 m × 69 m active area. In order to verify the performance of the circuits, the post layout simulation results are presented through the use of HSPICE and Cadence with TSMC level 49 (BSIM3v3) parameters for 0.18 m CMOS technology, where under supply voltage of 1.8 V, the maximum relative error of the circuits within 500 A of input range is about 11 A (2.2 % error) and the THD remains as low as 1.2 % for the worst case. Moreover, the power dissipation of the complete structure is found to be 0.66 mW.

The first group is based on the trans-linear (TL) principle introduced in [7]. This group is also classified in two subgroups including BJT and MOS trans-linear circuits. In bipolar transistors, it employs the exponential characteristic of current and voltage [7], [8]. In this method the cause of error originates from the nonzero values of the base currents and of the temperature dependence of the bipolar transistor parameters (the thermal voltage is linearly increasing with temperature and the saturation current has an exponential dependence on temperature). In CMOS technology, TL principle relies on the exploiting of loop transistors operating either in weak inversion [9], [10] or strong inversion [11], [12]. For weak inversion, although it leads to circuits offering low power consumption, the dynamic range and the operation speed turn out to be limited. For the TL principle in strong inversion, the body effect is a serious problem in a way that this effect causes mismatch in the threshold voltages which in turn, influences the linearity and accuracy of the circuits, however in some studies this effect was properly discussed and a few techniques were proposed [13], [14].
The most important aspects of computational circuits include power consumption, operation speed, design cost, simplicity and area efficiency. Although in practice, most of these parameters trade with each other and several design techniques have been proposed [15], [16] to satisfy the compromise between these characteristics, but the main challenge in designing computational circuits is how to implement with minimal effort a large number of these functions [17]. One possible technique to do this is to design a multifunctional computational structure which is based on the possibility of a multiple use of the same structure as a core of the design. On the basis of this technique, if the design effort being mainly focused on the improving of the core performances, all of the functions which will be implemented through the use of the core structure will automatically be improved. From this point of view, the second and third groups can be also classified.
The second group emphasizes on the use of piecewise linear approximation method [18][19][20], expansion of the functions using Taylor series [21], [22] and presenting a new approximation [23], [24] in which each term of the approximated series is realized using a current-mode [18][19][20][21], [23], [24] or voltage-mode [22] basic building block. In order to make the realization of the functions simple, some of these approximations have used only second-order [21], [22] or third-order [18], [24] terms which leads to low-precise implementation of computational circuits. Following this, the higher order approximations [20], [23] have been proposed to achieve higher accuracy at the expense of complex structure and consequently higher consumption of power. The complex structures reported in [25], [26], but not based on the piecewise linear approximation method or expansion of Taylor series or not CMOS-based circuits can be located in this group, owing to the fact that they also consume more power.
The third group deals with the structure based on the Operational Trans-conductance Amplifier (OTA). Although these structures can implement slightly less functions rather than the second group, but the advantages of reconfigurability, lower power consumption and higher accuracy encourage the designers to utilize this method. There are limited number of literatures on the use of OTAs for designing these circuits [27][28][29][30], while some of them do not allow multifunctional operation [27], [28] and some others suffer from having constant trans-conductance and not having entire linearity over the input range [29], [30]. This problem in turn influences the performance of the implemented computational circuits in terms of accuracy and efficiency.
The objective of this paper is to examine the applicability of a new Linearly Tunable OTA (LTOTA) as a basic building block which is employed in a modified structure to implement computational circuits either linear or nonlinear functions. The proposed trans-conductance amplifier provides a constant G m over a wide range of input voltage which allows the implementation of high precision computational circuits. In addition, the proposed LTOTA behaves as a bipolar OTA in which its trans-conductance is linearly tuned by the bias current, therefore all of the bipolar based OTA configurations can be easily replaced by the CMOS LTOTA, while their performance nearly remains the same. Due to the simple and compact structure, the power consumption of the implemented circuits is comparatively low.

Circuit Description
In order to realize computational circuits, a CMOS based trans-conductance circuit is employed as a basic building block of the design. The proposed structure is shown in Fig. 1, where I in is the input current. The transconductance gains of OTA 1 and OTA 2 can be varied by adjusting an external DC bias current of I 1 and I 2 , respectively. According to the figure, the input current of I in is injected into the OTA 1 , which is employed as a current controlled grounded resistor. The voltage across the OTA 1 is then utilized as the input voltage for the OTA 2 . Considering G m1 and G m2 as the trans-conductance gains of the OTA 1 and OTA 2 respectively, one can find the input-output relationship as follows: (1) If the trans-conductance of OTA 2 (G m2 ) has the square-root proportion to its current, by keeping I in and G m1 constant, the square-rooter circuit can be achieved. In the case of direct proportion of G m1 and G m2 to the current, the multiplier and divider circuits will be obtained. Also if I in = I Gm2 the squaring circuit is implemented. The implementation of these functions will be thoroughly discussed in Sec. 3. Figure 2 shows the trans-conductance circuit which is the basic building block to implement computational circuits. The differential input voltage of V in is applied in the form of V in = V 1 -V 2 , and I a and I ss represent the bias and tail currents, respectively. The operation of circuit is as follows:

Proposed CMOS OTA Circuit
Since the drain current of M 1 is constant (I DS1 = I a ), neglecting the body effect, V GS1 also has to remain constant; as a result any variation in the voltage of V 1 , will be reflected to the source terminal (V A ) level-shifted by V GS1 . Supposing M 1 operates in saturation region, the voltage of this node is given by: where K = 0.5 0 C OX (W/L) is related to trans-conductance parameter and V TH is the threshold voltage of MOS transistor. The transistor M 3 works in saturation region as well, thus its current can be written as: Replacing (3) in (4) yields: Similarly, one can find the current of transistor M 2 as: Transistors M 10 and M 11 sink extra currents of nodes A and B, respectively. This is due to the fact that I DS2 and I DS3 change with input voltage and since M 1 and M 4 have the constant current of I a , in order to prevent M 2 and M 3 being in linear region, M 10 and M 11 are considered. Also M 5 and M 6 are employed as a cascode stage to provide high output impedance at the output node. V Bn1 is chosen in which these transistors operate in the saturation region.
The transistors M 15 -M 18 act as a current sub-tractor which form the output current as follows: or: From (8), it is obvious that G m of the circuit is In addition, it implies that I a has the square root proportion with the trans-conductance gain. In order to have linearly tunable OTA, a current squaring circuit is employed in which its output will be applied as the bias current of the proposed OTA. Therefore, the next section will deal with current squaring circuit.

Current Squaring Circuit
The modified current squaring circuit which is based on the Translinear Loop (TL) principle is shown in Fig. 3 [31]. Supposing trans-conductance parameters of all transistors are well matched, considering translinear loop composed of M 1 to M 4 , we have: Writing KCL at nodes C and D: SQ DS4 x b 4 I I I I where I b is bias current and I x and I SQ represent input and output currents, respectively. Considering I DS1 = I DS2 = I b , substituting (10) and (11) into (9) and squaring both sides twice, the output current is given by: It is seen that the squaring of I x is appeared at the output. Note that the bias current of I b recognizes the input range of the circuit (I x 2I b ) as thoroughly discussed in [31].

Proposed Linearly Tunable OTA
The complete circuit of LTOTA is shown in Fig. 4, where the right side (M 1 -M 18 ) specifies trans-conductance circuit where its G m can be adjusted via I SQ fed to transistors M 13 (12) and (8) as the output of squaring and trans-conductance circuits respectively, the final output can be written as: Equation (13) indicates that the trans-conductance gain can be linearly tuned by the current of I x , while K and I b are constant values. Note that this linear relationship is the same as the trans-conductance gain in the bipolar-based OTA which is very useful in many applications [32]. Since the proposed LTOTA is realized by MOS transistors all in saturation region, therefore it is very suitable and efficient for fabricating in CMOS process.

Post Layout Simulation Results
In this section, post layout simulation results of the proposed circuits and their applications are presented through the use of HSPICE and Cadence with TSMC level 49 (BSIM3v3) parameters for 0.18 m CMOS technology  so as to verify the performance of the circuits. Layout pattern of the proposed LTOTA is illustrated in Fig. 5 which confirms that the circuit can be implemented in 102 m × 69 m active area. The aspect ratios of transistors are given in Tab. 1 and the power supply voltage is set to V DD = 1.8 V. Figure 6 shows the linear output current resulted from subtraction of two nonlinear input currents (I DS2 and I DS3 ) which were formulated in (5), (6) and (8). The constant G m in the corresponding range of the input voltage is shown in the figure as well. For this simulation, the bias current of I a which determines the trans-conductance is 100 A and the tail current of I ss is set to 300 A. It should be pointed out that the high linearity of G m comes from symmetrical configuration of the circuit which provides the symmetric currents of I DS2 and I DS3 as proved in (5) and (6), in which their subtraction is entirely linear. show that by changing the DC bias current of I a , the OTA can linearly convert the input voltage in the range of 1 V to 1 V into output current with nonlinearity less than 1%.   In order to demonstrate the feasibility of the designed OTA and LTOTA, they are employed in the structure of Fig. 1 for realization of some functional circuits. Replacing LTOTA in the structure leads to implement a multiplier/divider circuit. Since the bias current has a linear relation with G m we have: Considering I in and I 2 as the input currents and I 1 as the normalized current (I norm ), so the multiplier function is achieved. Also, supposing I 2 and I 1 as the input currents namely I num and I den respectively and I in as the normalized current, the output current will be proportional to I num /I den . Thus the structure performs as a divider circuit. Figure 9 shows how the structure works as a multiplier circuit. The figure depicts DC transfer characteristic of the analog multiplier, where the output current swings between -250 A to +250 A and the normalized current is set to 125 A. The simulation result of the structure when it employs as a divider circuit is depicted in Fig. 10. The characteristic between I out and denominator current (I den ) for swept currents of numerator (I num ) between +125 A and -125 A with 50 A per step is plotted while I norm is set to 125 A. num out norm den In the case that I in and I 2 are equal and I 1 being considered as a normalized current, a squaring function will be realized. In this case, the output current is given by: 2 in out norm By applying a triangle waveform with the frequency of 100 kHz to the input, the squaring function as well as the error value are appeared at the output (Fig. 11). It can be clearly seen that the simulated result is in a close agreement with the expected output, and the maximum error is 173 nA.
Let us consider the structure of Fig. 1. Replacing the OTA in this structure, one can find the output current as: In the case that I 1 = I in , we have:  Considering I 1 as the input current, by applying I 2 = 125 A as a normalize current the square-rooter function is implemented. To prove the efficiency of the circuit, a triangle waveform similar to the squaring circuit is applied; then the output current is achieved as shown in Fig. 12.
In order to examine the effect of temperature variation on the circuit, threshold voltage variation in the presence of temperature which is the most important parameter for this issue is considered which can be derived as [33]: where ms is the gate-substrate contact potential, is a body effect constant and F is the Fermi energy.
Considering NMOS and PMOS current mirrors in the circuit (M 7 -M 9 and M 12 -M 36 ), because they work on the principle that identical transistors with equal gate-to-source and drain-to-source voltages carry equal drain currents and since these voltages of corresponding transistors are equal in all conditions, any variations in the threshold voltage are automatically compensated. Therefore, probable temperature variations do not affect the performance of the current mirrors. For the complete circuit and also rest of the transistors, the simulations are carried out based on the conditions of Fig. 6 in different temperatures for transconductances, and relative errors are shown in Fig. 13(a) where the maximum error occurred at -40 o C with 0.63%.
Moreover, the body effect and channel length modulation affect the threshold voltage of the transistors [33]. Considering the mismatch for equality of threshold voltages in pair transistors of M 1 and M 3 and also M 2 and M 4 and subsequently rewriting (5) and (6) we have: (22) From (22), the mismatch values are subtracted in the second term ( V T1 -V T2 ), and consequently they cancel each other or minimize the error quantity. Considering the first term of the equation, the mismatch leads to a small DC offset in the output current which can be regarded as an error in the bias current of I a or a DC compensated current at the output. In order to show the effects of these nonidealities, Monte Carlo analysis is carried out by applying ±5% Gaussian distribution at ±3 level in the variation of threshold voltage and the result is shown in Fig. 13(b).
The Monte Carlo analysis for total harmonic distortion (THD) is shown in Fig. 14. The same conditions and distribution of simulations in Fig. 13 are applied for both of OTA and LTOTA circuits. The results show that most of the samples occur in the ranges of 0.6% to 0.8% and 1.0% to 1.2% for OTA and LTOTA circuits, respectively. Distortion analysis of the OTA circuit is carried out for different input amplitudes as well as signal frequency. The amplitude dependency of HD3 and IM3 are plotted in Fig. 15(a). In the worst case, HD3 and IM3 components are -68 dB and -67 dB for 2 V p-p differential input voltage at 10 MHz signal frequency. Variation of distortion components with frequency are also simulated and plotted in Fig. 15(b).  . 15. IM3 and HD3 vs. a) peak to peak input voltage at 10 MHz, b) with 2 V p-p input differential voltage.  Step response of the OTA for slew rate simulation.
A 2 V p-p step waveform is applied to unity-gain closed loop OTA whose response shown in Fig. 16. I ss and I a are set to typical values of 400 A and 150 A respectively, and the output load is a capacitance with 10 pF capacity.
Measuring the slope of output response gives both positive and negative slew rate as 5.7 V/ s. The comparison of the proposed circuit with previous works is shown in Tab. 2.

Conclusion
The major intention of this paper was to present a new method to implement computational circuits using linearly tunable CMOS OTA circuit. The proposed method enjoyed these attractive features: 1. Use of CMOS transistors, compatible with the current digital signal processing CMOS technology; 2. New tunable OTA proposed which could be linearly tuned by a bias current, therefore could be used as a bipolar OTA; 3. Could realize several linear and nonlinear functions with high precision performance; 4. The bipolar based OTA configurations could be easily replaced by the CMOS LTOTA; 5. Current-mode realization provided simple and intuitive configuration.
It should be pointed out that the main objective of the paper was that multiplier, divider, squarer and squarerooter functions could be simultaneously available using two designed OTA. Although each function could be separately found in the literature, without the new proposed OTA, they cannot be realized by one circuitry.