Electronically Tunable Current-mode High-order Ladder Low-pass Filters Based on CMOS Technology

This paper describes the design of current mode low-pass ladder filters based on CMOS technology. The filters are derived from passive RLC ladder filter prototypes using new CMOS lossy and lossless integrators. The all-pole and Elliptic approximations are used in the proposed low-pass filter realizations. The proposed two types of filter can be electronically tuned between 10 kHz and 100 MHz through bias current from 0.03 μA to 300 μA. The proposed filters use 1.5 V power supply with 3 mW power consumption at 300 μA bias current. The proposed filters are resistorless, use grounded capacitors and are suitable for further integration. The total harmonic distortion (THD) of the low-pass filters is less than 1% over the operating frequency range. PSPICE simulation results, obtained by using TSMC 0.18μm technology, confirm the presented theory.


Introduction
Active filters are essential building blocks in analog signal processing particularly in communication, instrumentation and control systems.Over the years, high performance voltage-mode active filters have received much attention.Recently, current-mode filters are becoming more popular with many advantages compared to the voltage-mode counterparts.This is attributed to the simplicity of the current-mode circuit building blocks, the compact design that can be provided and the operation with low supply voltages.Moreover, in current mode the summation and subtraction can be easily realized with relatively simple circuitry.This leads to reduced die area, lower power consumption requirements and improved high frequency performance.On the other hand it is well known that the performance of high-order filters may be preferable than lower-order counterparts in some applications [1].Thus, using high order filters [2], [3], superior performance can be achieved compared to that obtainable using low-order filters [4], [5].Moreover, high order filters can save area on the chip.Thus, allowing several subsystems to be integrated on the same chip.
For the design of high-order low-pass active filters, the realization method based on doubly terminated passive RLC ladder prototypes was used [6].High frequency ladder low-pass filters were presented in [7] by using currentmode integrators.Low input impedance current mirror and grounded capacitors were used for designing differential current-mode integrators.The major drawbacks of the circuits in [7] are the use of excessive number of active and passive components while achieving a relatively narrow tuning range.Current-mode high-order Butterworth lowpass ladder filter using the multiple-output current-controlled current-conveyor (MCCCII) was introduced in [8].It suffers from the narrow tuning range and the use of large numbers of active devices.All-pole Chebyshev low-pass ladder filters were presented using the fully balanced switched-current integrator [9] and the current-mode damped integrators [10].However, the proposed circuit in [9] cannot work at high-frequencies and that in [10] suffers from errors in the cut-off frequency.The current-mode filters presented in [11], [12] use simulated RLC ladder networks.The passive components are transformed to coupled-biquad structures that can be realized by multiple output OTAs and grounded capacitors.The realizations of current-mode leapfrog ladder filters using the current-difference buffer-amplifier (CDBA) and the differential-voltage current-conveyor (DVCC) were presented in [13] and [14] respectively.These realizations require many active building blocks and use floating resistors and may, therefore, be not suitable for integration.A different realization method of low-pass leapfrog filters was presented in [15].The proposed realization uses the second-generation current-conveyor (CCII) and exploits to advantage the frequency-dependence of the differential gain of the operational amplifier (OA) for implementing an integrator.While avoiding the use of externally connected passive components is an advantage, the proposed circuit in [15] lacks electronic tuning of the filter parameters and requires a relatively large number of active devices.In [16] the multiple outputs current conveyor (MOCC) was used to synthesize the low-pass filter (LPF) from the LC ladder prototype.However, the proposed circuit requires a relatively large number of passive components and lacks the electronic tunability of the filter parameters.High-order filters using bipolar junction transistor-based DO-CCCII were presented in [17].Each DO-CCCII uses 20 transistors without including the DC bias current.Since the number of DO-CCCII is equal to the order of the filter +1, then it is obvious that the proposed circuit requires a large number of bipolar junction transistors.Moreover, because of the dependence on the parasitic resistances at terminals x of the DO-CCCIIs, the parameters of the circuit are temperature dependent.Another topology for implementing high-order filters using CMOS-based DO-ICCII was introduced in [18].Each ICCII uses 16 MOSFETs in addition to special bias voltages applied to the gates of two transistors.Of course these bias voltages can be obtained from the DC supply voltages, but this requires additional circuits.Since the number of ICCII equal the order of the required filter +1, then it is obvious that the area on the chip will be very large.Moreover, the circuit does not enjoy independent control of its parameters.High order voltage mode circuits are also available; see for example [19].The circuit in [19] suffers from the classical disadvantages of the operation in voltage mode; that is the complicated circuits required for realizing summation and subtraction.Moreover, the circuit uses floating passive elements which is not attractive for integration.Thus, it appears that there is a need for new designs of high-order LPFs enjoying the following attractive features: use of less number of active and passive components, avoid the use of resistors, enjoy the electronic tunability of the filter parameters and are suitable for integration.
Therefore, it is the major intention of this paper to present two transistor level designs of current-mode thirdorder ladder low-pass filters using CMOS technology.The well-known all-pole and Elliptic RLC prototypes are used for synthesizing the circuit elements of the proposed filters.The proposed filters are realized on the transistor-level using lossy integrators, lossless integrators, gain circuits and grounded capacitors.The proposed circuits enjoy the following attractive features: relatively small number of components, low-voltage supply, low-power consumption, no use of externally-connected resistors and wide-range electronic tuning of the filter characteristics.The PSPICE simulation results obtained are in excellent agreement with the theoretical results and confirm that the proposed filters are suitable for high-frequency up to VHF which would be very suitable for designing communications system.

CMOS Current-mode Lossy and Lossless Integrators
The basic lossy integrator, or first order low-pass filter, used in this paper as a main building block is depicted in Fig. 1.With a single input (X) and two outputs (Y 1 and Y 2 ) the transfer function of the lossy integrator is described by (1) 1 2 The current-mode dual output lossy integrator shown in Fig. 1 can be easily implemented on the transistor level by using MOS transistors as shown in Fig. 2. The current transfer functions can be obtained by using the small signal model shown in Fig. 3. Routine analysis of the circuit of Fig. 3 yields the current transfer functions of equations ( 2) and ( 3) where g mi is transconductance of transistor i. Assume that transistor M 1 -M 4 are matched (g m1 = g m2 = g m3 = g m4 = g m ), the current transfer functions of Fig. 3 become On the other hand, the lossless integrator can be easily realized by modifying the lossy integrator as follows.First, an inverting gain is added to the output of inverting lossy integrator [20].Second, the inverted output is fed back to the input as shown in Fig. 4. Thus, the non-inverting and inverting current-mode lossless integrator transfer functions obtained at ports Z 1 and Z 2 , respectively, can be expressed as Figure 5 shows a possible transistor level realization for the lossless integrator shown in the block diagram of Fig. 4. The output of the lossy integrator formed of transistors M 1 , M 2 and M 3 is connected to the inverting gain unit formed of transistors M 4 and M 5 and then fed back to the input.There are two current outputs I OB (port Z + ) and I OA (port Z -) taken from transistors M 6 and M 2 , respectively.Assuming that transistors M 1 -M 6 are matched with g m1 = g m2 = g m3 = g m4 = g m5 = g m6 = g m , the current transfer functions can be obtained by using the small signal model shown in Fig. 6.Routine analysis of the small signal model of Fig. 6 yields the following transfer functions . ( From Fig. 3 and Fig. 6, the input impedance of both integrators can be expressed as In equations ( 2)-( 5) and ( 7)-( 8) the transconductance g m of any transistor is given by where , C ox , W and L are surface mobility, channel oxide capacitance, channel width and channel length of the MOS transistor, respectively and I D is the bias current I B of the transistor.Equation (10) clearly shows that transconductance can be tuned by adjusting the bias current I B .Thus, the parameters of the lossy and lossless integrators of Figs. 2 and 5 can be electronically tuned.

Synthesis of RLC Ladder Low-Pass Filters
This section describes the synthesis procedure of ladder filter based on the signal flow graph (SFG) method.
Two types of passive RLC ladder low-pass filter; the allpole and Elliptic filters [21][22][23][24][25], are provided as prototypes.In some applications, a higher fall off rate is required in the transition band; that is a very high attenuation is required very near the cutoff frequency.This requirement mandates the use of elliptic functions in the approximation of the filter transfer function and leads to the design of Elliptic or Cauer filters [22].
Firstly, the doubly terminated current-mode thirdorder all-pole passive RLC ladder low-pass filter prototype shown in Fig. 7 is considered.Considering the prototype shown in Fig. 7, using KCL the current and voltage relationship can be written as Using equations ( 11)-( 16), a SFG can be constructed and is shown in Fig. 8(a).Voltages at different nodes and currents in different branches are forming the nodes of the SFG.The voltage nodes need to be transformed into current nodes.The transconductance g m is used to normalize the voltage nodes to current nodes.The variables R S = R L = 1/g m are used to simplify the realization method.Furthermore, lossless integrators with its negative feedback in lefthand and right-hand sides can be replaced by lossy integrators.The finalized current-mode SFG is shown in Fig. 8(b).It can be seen that the all-pole low-pass ladder filter can be designed based on lossy and lossless integrators.
Secondly, the passive RLC doubly terminated thirdorder Elliptic low-pass filter shown in Fig. 9 is also used as a prototype.Considering the prototype in Fig. 9, routine analysis yields the following current and voltage relationships:     Using ( 17)-( 23), a modified RLC prototype can be redrawn as shown in Fig. 10.For simplicity, the current terms ( 20) and ( 23) are replaced by I x and I y respectively and the capacitor C 3 is replaced by two new capacitors (C 1 + C 3 ) and (C 3 + C 4 ) connected with two dependent sources as shown in Fig. 10.From equations ( 17)-( 23) and Fig. 10, a SFG can be drawn as shown in Fig. 11(a).Voltages at different nodes and currents in different branches are forming the nodes of voltage and current in the SFG.The voltage nodes need to be transformed into current nodes.The transconductance g m is used to normalize the voltage nodes to current nodes.The variables R S = R L = 1/g m are used to simplify the realization method.Furthermore, lossless integrators with its negative feedback in left-hand and right-hand sides can be replaced by lossy integrators.The finalized current-mode SFG is shown in Fig. 11(b).It can be seen that the elliptic low-pass ladder filter can be designed based on lossy, lossless integrators and current gains.

CMOS Realization of Ladder Low-Pass Filters
Considering the SFG shown in Fig. 8(b), the third-order all-pole low-pass ladder filter can be constructed by using 2 lossy integrators and a lossless integrator.In current-mode realizations, summing and subtracting can be easily implemented by direct connection without additional circuit elements.Using the block diagrams shown in Figs. 3 and  Using the block diagram in Fig. 12 and the circuits shown in Figs. 2 and 5, the complete circuit diagram of the synthesized third-order all-pole ladder low-pass filter is shown in Fig. 13.In Fig. 13, the bias currents are realized by using PMOS current mirrors M Bi with identical aspect ratios for providing the equal bias currents.
In a similar way using the Elliptic filter SFG shown in Fig. 11(b), the third-order Elliptic low-pass ladder filter can be constructed by using lossy, lossless integrators and additional current gains.Inspection of Fig. 11(b) shows that the SFG of Elliptic filter has two feedback paths.The current gains are needed to provide the feedback paths.Elliptic third-order ladder low-pass filter can be implemented by using the block diagrams of two lossy integrators and a lossless integrator.Two multiple outputs (+, -, k) current splitters are used to provide the current feedback between I' 1 and I' 2 .It can be seen that the proposed circuit requires only three capacitors while the prototype RLC filter uses three capacitors and one inductor.The current-gain can be easily realized by defining the aspect ratios of the particular transistors and its bias current.Using the SFG in Fig. 11(b), the design of third-order elliptic low-pass ladder filter can be realized by using the block diagram of two lossy integrators, one lossless integrator and two current splitters as shown in Fig. 14.
Using the block diagram in Fig. 14 and the circuits shown in Figs. 2 and 5, the complete circuit of the thirdorder Elliptic low-pass ladder filter is shown in Fig. 15.It can be seen that the proposed circuit requires only three capacitors while the prototype RLC filter of Fig. 9 requires three capacitors and one inductor.In Fig. 15 the bias currents are implemented using PMOS current mirrors M Bi with identical aspect ratios for providing the equal bias currents.As shown in the block diagram in Fig. 14, two extra current amplifiers with current gain k are required.In Fig. 15 these current amplifiers are realized by using the MOSFET transistors shown in the two dotted boxes.Note that the capacitors used in the circuits are on-chip type [26] as shown in Fig. 16.These capacitors can be simultaneously implemented with the whole circuit on the chip for full integration.This would also enable high frequency operation as it reduces the parasitic capacitances associated with of-the-chip connections.

Effect of Non-idealities
This section shows the influence of the NMOS transistors parasitic elements.Lossy and lossless integrators are the main building blocks of the proposed filters.Therefore, due to the transistor parasitic elements, when the circuits work at relatively high-frequencies their performances may deviate from the theory.Non-ideal analysis of integrators can be performed by using the small signal model of NMOS in Fig. 16.In the small signal model shown in Fig. 17, the input parasitic capacitances C gs and C gd , the conductance g ds and the transconductance g m are incorporated.The effects of the transistor parasitic components on the performance of the proposed low-pass filters are described in the following subsections.

Parasitic Capacitances
This section will consider the effect of the parasitic capacitances C gd and C gs , which is important for determining the performance of a CMOS circuit, particularly at high frequencies.

Lossy Integrators
Using the small signal model of MOS transistor of Fig. 17, considering only the parasitic gate-drain capacitance C gd , that affects the inverting and non-inverting lossy integrator, and assuming that the transconductances of MOS transistors are matched, then transfer functions of the lossy integrator of Fig. 2 can be approximated by ( 24) and ( 25), respectively Similarly, considering the parasitic gate-source capacitance C gs that affects inverting and non-inverting lossy integrator, and assuming that the transconductances of MOS transistors are matched, then the transfer functions of the lossy integrators are given by ( 26) and (27), respectively   Equations ( 23)- (26) show the effect of the parasitic capacitances on the performance of the lossy integrator.In saturation operation, the parasitic gate to drain capacitance C gd and gate to source capacitance C gs will vary anywhere within the ranges depending on the bias conditions involved [22].For the specific case where it is assumed that the parasitic capacitances     Inspection of equations ( 29)-( 32), shows the effect of the parasitic capacitances C gd and C gs on the performance of the lossless integrator.In saturation region, the parasitic gate to drain and source capacitances C gd and C gs will vary anywhere within the ranges depending on the bias conditions involved.To prevent significant errors, the selected capacitance C 1 should be 1 9 5 From (33), it is clear that the errors can be minimized by selecting relatively large values for the capacitance C 1 .

Parasitic Resistance r ds
The most commonly used small-signal model for a MOS transistor operating in the active region is shown in Fig. 17 where  represents the channel-length modulation effect which is normally less than 1.It produces the slope of drain current as a function of the voltage v DS .The channel conductance will be dependent upon L through  which is inversely proportional to L (  1/L).The small-signal channel conductance g ds is expressed as Equation ( 35) shows the direct effect of the drain current (bias current) and the channel-length modulation  on g ds .This would affect the gain and the cut-off frequency of the filter.It is a trade-off situation especially if short-channel (L < 5 µm) is used in order to minimize the die area of the chip and its power consumption.However, the resulting small reduction in gain of the filters may be tolerated and can be easily compensated in the succeeding stages.

Lossy Integrators
Using the small signal model of MOS transistor with parasitic conductance and assuming that the transconductances of the MOS transistors are matched, where it is assumed that g mi = g m and g dsi = g ds the transfer functions of the lossy integrators can be approximated by Inspection of equation ( 36) and (37) clearly shows that magnitude and the cut-off frequency of the lossy integrators will be slightly affected by g ds .In order to avoid significant errors in the transfer functions of the lossy integrators the transistor transconductance g m must satisfy the condition Inspection of equations ( 10) and (38) shows that significant errors can be avoided if large transistor width W is used.

Lossless Integrators
In a similar way, taking into consideration the effect of the parasitic drain-source conductance g ds , the transfer functions of the inverting and non-inverting lossless integrators can be expressed as From equations ( 41) and ( 42), it can be seen that both types of lossless integrator are affected by the parasitic conductance g ds as a parasitic pole at low frequency ω L = 4g ds / C 1 will appear in each transfer function.However, these effects will be significant at very low-frequency where the working frequency is much less than the frequency of the parasitic pole.Thus, the resulting parasitic poles will provide the lower frequency limitation of lossless integrators and the maximum gain at low frequency k = g m /4g ds .

Transistor Mismatches
This section will consider the effect of transistor mismatches on the performance of the proposed integrator circuits.

Lossy Integrators
Consider the lossy integrator circuit of Fig. 2. Using the small signal model of the MOS transistor of Fig. 17, ignoring the effects of C gs and g ds and assuming that the transconductances of the MOS transistors are g m1 and g m2 for the transistors M 1 and M 2 respectively, reanalysis shows that the transfer function of the lossy integrator of Fig. 2 can be expressed by (43) Inspection of equation ( 43) shows that, due to the transistor mismatch, the low frequency gain of the lossy integrator will deviate from unity as predicted by equations ( 4) and ( 5).This effect is not significant and can be easily compensated, if required, by an additional current amplifier or attenuator.

Lossless Integrators
In a similar way the effect of transistors mismatch on the performance of the lossless integrator of Fig. 5 can be studied.Using the small signal model of the MOS transistor of Fig. 17, ignoring the effects of C gs and g ds and assuming that the transconductances of the MOS transistors are g m1 for the transistor M 1 and g m2 for the transistors M 2 and M 3 respectively, reanalysis shows that the transfer function of the lossless integrator of Fig. 5 can be expressed by (44) ( This low-frequency pole will be at zero frequency when g m1 = g m2 resulting in an ideal lossless integrator.But it may be moved slightly in the right-half plane if g m1 > g m2 or slightly in the left-half plane if g m1 < g m2 .Thus, in order to avoid any unexpected performance care must be taken to ensure that g m1  g m2 .This can be easily achieved by trimming the bias currents of the transistors.

Simulation Results
This section describes the simulation results of the proposed electronically tunable current-mode ladder thirdorder low-pass filters.PSPICE simulation results are carried out by using TSMC 0.18 µm CMOS technology, +1.5 V power supply.The extracted small signal parameters of NMOS and PMOS are  n = 0.1 V -1 ,  n C ox = 100 A/V 2 , V THn = 0.37 V and  p = 0.1 V -1 ,  p C ox = 25 A/V 2 , V THp = 0.38 V respectively.The minimization of the aspect ratio W/L is required for obtaining the desired transconductance with minimum error and die area.Thus, the aspect ratios of the transistors used in Figs. 13 and  The simulated DC transfer characteristic of the proposed lossy integrator is shown in Fig. 18.Inspection of Fig. 18 clearly shows that large values of channel length L result in smaller error and DC-offset than the small values of L. However, it is a trade-off between the error and die area minimizations.Using more accurate current mirror structures; for example cascode current mirrors and large values of L would result in smaller errors but a large die area, complex structures and more power consumption will be the price for this reduced error.
In order to verify the operation of the transistors in the saturation region, the values of V GS and V DS were monitored over the bias current range [0.03, 0.3, 3, 30, 300] µA for the transistors M 1 and M 2 of the lossy integrator of Fig. 2 and transistors M 1 -M 5 of the lossless integrator of Fig. 5.In all cases it was found that V DS > V GS -V THN and V GS > V THN .Thus, the operation of the transistors in the saturation region is confirmed for the bias current range of interest.The frequency response of CMOS lossy integrator of Fig. 2 and CMOS lossless integrator of Fig. 5 are depicted in Fig. 20 and 21, respectively.As explained in Sec.4.1, the capacitor C 1 = 10 pF is selected for minimizing the effect of parasitic capacitances and the bias current I B was varied in the range [0.03, 0.3, 3, 30, 300] µA.Figures 20  and 21 clearly show that the frequency response can be tuned, using the bias current, over a wide range of frequencies (10 kHz to 100 MHz).From Fig. 21, the low-frequency current gain of the lossless integrator is around 25 dB.This agrees well with the theory presented in Sec.4.2.2.Inspection of Fig. 21 clearly shows that there is a parasitic zero in the gain-frequency characteristic.This parasitic zero can be attributed to the parasitic output resistances of the MOSFETs which is inversely proportional to the transistor length L. Thus, for L = 0.36 µm and bias current I B = 300 µA the output resistance of the transistor will be approximately 33 kΩ.This is a relatively low value and would result, in conjunction with the transistor parasitic capacitance, in a parasitic zero in the transfer characteristic.However, as shown in Fig. 21, this parasitic zero manifests itself at relatively high frequencies outside the frequency ranges of interest.The specifications of the prototype third-order filter with Chebyshev response are as follows: Cut-off frequency = 2 MHz, A max = -6 dB and passband ripple = 0.1 dB [27].The RLC prototype of Fig. 7   tion results obtained from the RLC prototype filter of Fig. 7 and the proposed all-pole filter in Fig. 13 is shown in Figure 24 shows that the variation of the input impedance at a bias current I B = 300 µA.Inspection of Fig. 24 shows that the input impedance is around 100 Ω along the pass-band frequency of around 100 MHz and becomes almost zero within the stop-band.Thus, the input impedance is relatively low over a wide range of the pass band.Figure 25 shows the group delay of the proposed all-pole low-pass filter.It can be seen that the group delay is flat along the pass-band with a value around 4 ns.
The specifications of the prototype third-order Elliptic filter are as follows: the cut-off frequency = 2MHz, A max = -6 dB, A min = -35 dB, and passband ripple = 0.1 dB [27].The Elliptic prototype low-pass filter of Fig. 9       The performance of the proposed third-order all-pole and Elliptic low-pass filters can also be verified by applying multi tones (10,40,70,100,130,160,190 and 220 MHz) to the filters at the bias current equal to 300 µA.From Figs. 30 and 31, it appears that the out-of-band tones (> 100 MHz) have been removed and only the in-band tones (< 100 MHz) can be obtained at the output.Furthermore, it can be seen that, with the same order of the filter, the characteristic of the Elliptic filter is better than that of the all-pole counterpart especially in removing signals in the stop-band.
The total harmonic distortion (THD) of the proposed third-order all-pole and Elliptic low-pass filters was measured and the results are shown in Fig. 32 and 33, respectively.The results were obtained by applying two sinusoids with variable amplitudes at two frequencies (1 MHz and 10 MHz) with bias current I B = 300 µA.The THD at 10 MHz of the proposed filters are found to be below 0.7% and 0.6%, respectively.
The performance of the proposed filters can be verified by applying the in-band signal into the filters.Both of the filters are setting the frequency cut-off at 100 MHz based on 300 µA of the bias current.Sinusoidal signals of      Table 1 shows a comparison of the performance of the proposed all-pole and Elliptic third-order ladder low-pass filters with previously published filters.Most of the previous works cannot be operated at relatively very high frequencies and have no electronic tunability feature because of the limitation of the used active devices.Most of the pervious works use excessive number of transistors and relatively large power supply voltages.It can be seen that the proposed filters use a low number of components without any externally connected resistors compared with previously published works.Table 1 shows that electronic analog filter design and CMOS analog integrated circuit design.He is a member of IEEE, USA.
C gdi = C gd , C gsi = C gs with C gd = WL D C ox and C gs = W((2/3)(L)+L D ))C ox , it can be seen that parasitic capacitances C gd and C gs produce a small deviation in the frequency response of the low-pass filter.To prevent significant errors, the capacitance C 1 should be In a similar way, the effect of the parasitic gate-drain and gate-source capacitances C gd and C gs , that affect the inverting and non-inverting lossless integrator of Fig. 5 can be considered.Assuming that the transconductances of MOS transistors are matched, the transfer functions of the lossless integrators affected by the parasitic capacitances C gd and C gs can be expressed as . The voltage-controlled current source g m v gs is the most important component of the model, with the transistor current-voltage relationship given by of equation(44)  shows that, due to the transistor mismatch, the lossless integrator becomes a lossy integrator with a very low frequency pole at 15 were selected as W/L = 70 µm/0.36µm.The bias currents I B are provided by using positive current mirrors (PMOS) with identical aspect ratio W/L = 100 µm / 0.36 µm.The special NMOS transistors (M 19 and M 24 ) of Fig. 15 use W/L = 4.8 µm / 0.36 µm for obtaining the current gain k = 0.07.The special PMOS transistors (M B20 and M B25 ) of Fig. 15 use of W/L = 6.8 µm / 0.36 µm to achieve the bias current 0.07I B .

Fig. 18 .
Fig. 18.DC-characteristic of the proposed lossy integrator using different values of W/L.

Fig. 19 .
Fig. 19.Transconductance of a MOS transistor against its bias current.Variations of the transconductance of the MOS transistor were also measured as a function of the bias current of the transistor aspect ratio W/L = 70 µm / 0.36 µm.The result shown in Fig. 19 confirms the dependence of the transconductance on the bias current.

Fig. 23 .Fig. 24 .
Fig. 23.Magnitude response of proposed third-order all-pole LPF as a function of the bias current I B .

Fig. 25 .
Fig. 25.Group delay of the proposed all-pole low-pass filter at bias current I B = 300 µA.

Fig. 22 .
It can be seen that the frequency response of the proposed filter and the RLC prototype are very close but the slope of the stop band has slight deviations.The electronically-tuned feature of the proposed third-order all-pole low-pass filter can be provided by adjusting the bias current I B [0.03, 0.3, 3, 30, 300] µA.The frequency response of the filter can be tuned over a wide range of frequencies (10 kHz and 100 MHz) as shown in Fig.23.It can be seen that the results are in agreement with the theoretical predictions.
was simulated using the following components: C 1 = C 4 = 120 nF, C 3 = 11.4 nF, L 2 = 102.8nH d an R S = R L = 1 Ω.The proposed Elliptic filter of Fig. 15 was simulated using the following components: C A = C B = (C 1 + C 3 ) = (C 3 + C 4 ) = 8.5 pF (W/L = 50 µm / 50 µm) and C 2 = 7.5 pF (W/L = 45 µm / 45 µm) and bias current I B = 5 µA.The simulation results obtained from the proposed Elliptic LPF and the RLC prototype are depicted in Fig. 26.It can be seen that the magnitude response of the proposed Elliptic filter is quite similar to that of the prototype Elliptic filter but the stop-band magnitude is slightly different.The electronically-tuned feature of the proposed thirdorder Elliptic low-pass filter can be provided by adjusting the bias current I B [0.03, 0.3, 3, 30, 300] µA.The frequency response of the filter can be tuned over a wide frequency range as shown in Fig. 27.It can be seen that the results are in good agreement with the theoretical predictions.

Figure 28
Figure 28 shows the variation of the input impedance of the Elliptic low-pass filter.The input impedance with bias current I B = 300 µA is obtained around 100 Ω along

Fig. 26 .
Fig. 26.Comparison of the proposed Elliptic LPF with the RLC prototype.

Fig. 27 .
Fig. 27.Magnitude response of the proposed third-order Elliptic LPF as a function of the bias current I B .

Fig. 28 .
Fig. 28.Input impedance of the proposed Elliptic low-pass filter at bias current I B = 300 µA.

Fig. 29 .
Fig. 29.Group delay of the proposed Elliptic low-pass filter at bias current I B =300 µA.the pass-band frequency of around 100 MHz and becomes almost zero in the stop-band.Thus, the input impedance is relatively low over a wide range of the pass band.Fig.29shows the group delay of the proposed Elliptic low-pass filter at bias current I B = 300 µA.It can be seen that the group delay is flat along the pass-band with a value around 4 ns.

Fig. 30 .
Fig. 30.Multi tones measurement of the proposed third-order all-pole low-pass filter at bias current I B = 300 µA.

Fig. 31 .
Fig. 31.Multi tones measurement of the proposed third-order Elliptic low-pass filter at bias current I B = 300 µA.

Fig. 32 .
Fig. 32.THD of the proposed third-order all-pole low-pass filter at bias current I B = 300 µA.

Fig. 34 .
Fig. 34.Input and output of 10 MHz waveforms of Chebyshev LPF at bias current I B = 300 µA.

Fig. 35 .Fig. 36 .Fig. 37 .
Fig. 35.Input and output of 10 MHz waveforms of the Elliptic LPF at bias current I B = 300 µA. 10 MHz with 30 µA p-p are applied to the both filters.It can be seen that the sinusoidal signal can be obtained at the outputs of the proposed Chebyshev and Elliptic filters as shown in Fig. 34 and 35, respectively.It is evidently found that in-band signal can be passed the proposed filters with low distortion.Transistor mismatches are the major sources of errors in the proposed MOSFET based filters.To investigate the effect of transistor mismatches on the performance of the proposed filters Monte Carlo analysis was performed.A hundred of samples are run for verifying the frequency response.The 2% uniform deviation of NMOS transistors surface mobility  with bias current I B = 300 µA is assumed.The results are shown in Figs.36 and 37. Inspection of Fig. 36 shows that the cutoff frequency of the filter deviates from its nominal value by about ±2 MHz which corresponds to ±2%.Inspection of Fig. 37 shows that the cut-off frequency of the Elliptic filter deviates from its nominal value by about ±2 MHz which corresponds to ±2% error.In order to investigate the feasibility of integrated circuit fabrication and to estimate the area on the chip of the proposed circuits, the physical layout of the proposed low-pass Chebyshev and Elliptic filters were obtained and are shown in Figs.38 and 39 respectively.The resulting dimensions of these layouts are approximately 200 µm  240 µm and 210 µm  360 µm, for Chebyshev and Elliptic filters, respectively.

Fig. 38 .
Fig. 38.The physical layout of the low-pass Chebyshev filter.

Fig. 39 .
Fig. 39.The physical layout of the Elliptic low-pass filter.
Taher ABUELMA'ATTI was born in Cairo, Egypt, in 1942.He received the B.Sc. degree in Electrical Engineering from the University of Cairo, Cairo, Egypt, in 1963, and the Ph.D. degree and the Doctor of Science degree, both from the University of Bradford, Bradford, England, in 1979 and 1999, respectively.From 1963 to 1967, he was at the Military Technical College, Cairo, as a Teaching Assistant.He was with the Iron and Steel Company in Helwan, Cairo, from 1967 to 1973 as a Senior Electrical Engineer.From 1973 to 1976, he was with the College of Engineering, University of Riyadh, Riyadh, Saudi Arabia, as a Teaching Assistant.From 1980 to 1981, he was with the Faculty of Engineering, University of Khartoum, Khartoum, Sudan, as an Assistant Professor, and from 1981 to 1982 he was with the College of Engi-neering, King Saud University, Riyadh, Saudi Arabia, as an Assistant Professor.In 1982, he joined the College of Engineering, University of Bahrain and in 1987 he became an Associate Professor.In 1991 he joined the College of Engineering Sciences, King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia, where he became a Full Professor in January 1995 and in April 2008 he became a Distinguished University Professor.In April 2009, he was appointed as an Honorary Visiting Professor at the Department of Electronic and Electrical Engineering, University of Manchester, Manchester, U.K.He is the author or coauthor of more than 600 journal articles and technical presentations.According to Scopus (Elsevier) his current "h-index" is 23.His research interests include problems related to analysis and design of nonlinear electronic circuits and systems, analog integrated circuits, and active networks design.