A Novel Cyclic Time-to-Digital Converter Based on Triple-Slope Interpolation and Time Amplification

This paper investigates a novel cyclic time-todigital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals (Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT) variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. This converter also improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the integral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.


Introduction
High resolution time-to-digital converter (TDC) has been widely used in many applications such as on-chip time signal measurement systems, biochemical sensor readouts and frequency synthesis circuits [1], All Digital Phase Locked Loops (ADPLLs) [2], [3], laser range finders [4], digital storage oscilloscopes, and capacitive sensor readouts [5].In these converters, the time interval between two input signals is converted into a digital output code.TDCs can be divided into two main groups: direct conversion and indirect conversion TDCs [6].Direct conversion TDCs employ delay-line elements which include a chain of buffers or inverters in their structure.These converters are used to measure short time intervals between the rising edges of the input signals [7], [8].The main disadvantages of direct conversion TDCs are the circuit complexity, which results in high power consumption and high sensitivity to PVT variations [9].In addition, these converters are sensitive to the mismatch between the elements causing the non-linear factors.In general, the dynamic range of the converters is limited by the number of delay stages.Therefore, the conversion rate is slow [10].Indirect conversion TDCs can be divided into the ramp TDCs [11], and the multi-slope pulse stretching TDCs [12], [13].There are also converters that take advantage of the interpolation technique for conversion which is implemented based on multi-slope pulse stretching methods [9], [14], [15].The interpolation circuits are usually united with the counterbased TDCs to increase the input range to infinity [9].Indirect conversion TDCs feature low sensitivity to PVT variation, sub-gate resolution, simple circuit structure, low chip area, and good dynamic range.In order to achieve high performance, a high-resolution, high-speed TDC is required.A perfect solution is the employment of a twostep TDC which ampli es the time residue after the coarse conversion and subsequently performs a ne conversion [16].This paper investigates a novel cyclic TDC that employs analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution.The advantages of the proposed 9-bit cyclic TDC are the followings.1) This converter has a low circuit complexity compared with TDCs previously proposed.2) The proposed converter does not use delay lines and vernier delay lines (VDL) in its structure, resulting in taking advantage of low sensitivity to PVT variation in the design.
3) It features high resolution and accuracy due to employing two-step and analog interpolation structures.4) The proposed cyclic TDC reduces the number of circuit elements compared with the previously proposed converters.Therefore: 5) This converter reduces the active chip area and the power consumption.6) In the proposed converter, there is no apparent mismatch between the circuit elements.Thus, the linear range of the converter is appropriate without extra elements.7) This converter has a good dynamic range and reduces INL and DNL errors.In the proposed converter, analog interpolation is performed based on a triple-slope conversion.Simulation results prove that our TDC achieves a resolution of 0.273 ps by 470 μW energy consumption through a 1.8 V power supply.The INL and DNL errors are in the range of +1.1/-0.8LSB and +1.15/-1.1 LSB, respectively.Also, the dynamic range of the converter is 360 ps.The basic principles of the time domain 2.5b/stage cyclic structure are described in the following section, while the implementation of the proposed cyclic TDC using the interpolation and time amplification techniques is presented in Sec. 3. Next, Section 4 gives a description of the operation details of the proposed cyclic TDC, and the simulation results are presented in Sec. 5. Section 6 concludes this work.

Time Domain Cyclic Structure
Figure 1 shows the block diagram of a cyclic TDC which includes an input pulse generator, a time domain 2.5b TDC and a register and digital error correction logic.At the beginning of the conversion, the pulse generator receives two time input signals (Start and Stop) and generates a pulse whose width is the time interval between the rising edges of the two.The generated pulse is the first time input of the converter and is fed to the cyclic TDC.The detailed circuit implementation and transfer curve of a 2.5b/stage TDC are shown in Fig. 2 and Fig. 3, respectively [13].The structure of the time domain 2.5b/stage is similar to a conventional 2.5b multiple digital-to-analog converter (MDAC) which is a main block in voltage domain pipeline and cyclic converters [17], [18].The time domain 2.5b/stage consists of a TDC, a digital-to-time converter (DTC) and a time amplifier (TA) [19].According to Fig. 2, the TDC can quantize the time input and produce a 2.5b digital output code.Next, according to the output digital code, the DTC produces a time reference which is necessary to generate the time residue.Finally, the time residue is ampli ed by the TA and fed to the next operation phase.The transfer curve is inverted due to complementary operation of the time-register [13].Therefore, the following equation is obtained for time output: where Q is a quantization level [13].According to (1), the relationship between T in and T out can be expressed as follows: where T res and T FS are the time residue and the full scale time, respectively [13].

Proposed Cyclic TDC
In this section, the performance of the proposed 9-bit cyclic TDC in different modes of operation is investigated.The block diagram of the 2.5b/stage converter is shown in Fig. 4, along with the corresponding timing diagram depicted in Fig. 5.The proposed TDC consists of a 3-bit digital counter, two comparators, a pulse multiplier, an interpolation capacitor, a constant current source, and some simple control logics.The following subsections describe the converter operation in its different modes.Firstly, the pulse generator produces a pulse whose width is the time interval between the rising edges of two input signals (T in ).

Step 1: Charging the Input Capacitor
In the rising edge of the Start signal (or the rising edge of T in ), switch S 1 is turned on while switches S 2 , S 3 , and S 4 are turned off.Hence, the input capacitor (C in ) is charged by a constant current source (I ref ) linearly.The equivalent circuit for this operating step is illustrated in Fig. 6.Thus further charging of C in is stopped in the rising edge of the Stop signal (or the falling edge of T in ).At the end of this step, the voltage on C in (V C ) is proportional to T in and obtained as follows: where V in is the voltage on C in at the end of step 1.

Step 2: Discharging Input Capacitor and Generating Complementary Voltage Residue
This step is similar to an analog interpolation TDC presented in [10].In Step 2, an analog interpolator circuit is used for digitizing the time interval between two input signals and producing a digital output code.The proposed TDC performs a triple-slope time stretching for quantizing the time interval and increases the resolution.According to the equivalent circuit of Step 2 shown in Fig. 7, switches S 1 , S 3 , and S 4 are turned off while S 2 is turned on.As a result, C in is discharged by a constant current source (I ref ), alternatively.Analog interpolation is performed by a second reference clock (CLKD) [10].To quantize an input pulse, C in is discharged periodically during CLKD and a digital counter counts the number of discharging steps (quantization levels).The voltage drop across C in in each period of CLKD is calculated as: where V and 2 Q are the voltage drop across C in and the pulse width of CLKD in each period, respectively.The full-scale time (T FS ) of the proposed cyclic TDC is de ned by the total time delay for discharging C in .Therefore, in each step of the operation of the cyclic TDC, T FS is depended to the input signal and calculated as: where At the end of this step, the voltage on C in is calculated as: where V res is voltage residue of the input capacitor and m is the number of CLKD cycles required for discharging C in .At the end of Step 2, according to the proposed TDC operation and ( 7), V res has a negative voltage value which is proportional to the complimentary time residue.Comparator 1 compares the voltage on C in with '0' and switches its output accordingly.Thus, when the output of comparator 1 begins '0', the digital counter is stopped.A digital register saves the produced 3-bit output in each step.Finally, the digital error correction logic gathers four saved 2.5 bits and produces the nal 9-bit output.

Step 3: Charging Interpolation Capacitor and Generating Main Voltage and Main Time Residue
The equivalent circuit for this operating step is illustrated in Fig. 8.During this step, the main voltage residue where V mvr is the main voltage residue, thus: Simultaneously, the main time residue is generated by comparator 2. The output of comparator 2 is '1' as long as the voltage of C in is greater than '0'.As can be seen in Fig. 5, in the falling edge of chg , S 4 is turned off and the output of comparator 2 begins '0'.Thus, comparator 2 produces a pulse whose width is the main time residue.The main time residue is calculated as:

Step 4: Generating 4×Pulse Multiplier
In this step, the main time residue is amplified by a 4×pulse multiplier (PM) which is the time input for the next cyclic step.As can be seen in Fig. 9, the pulse multiplier includes an OR gate and four delayed signals [13], [19].4×PM achieves accurate gain and wide input linear range without calibration.Thus: The digital register saves four digital output codes that are produced by the digital counter in four cyclic steps.Finally, the digital error correction logic produces the final 9-bit output.

Operation Details of the Proposed Cyclic TDC
An example of a detailed operation of the proposed cyclic TDC is investigated in this section.Consider an input signal of T in = 9.8 Q (0 T in 16 Q ) which is the time interval between the rising edges of two input signals (Start and Stop).Therefore, the digital 9-bit output code for this time input is '100111001'.The operation details of the proposed converter are as follows.
Step 1: Suppose the time interval between the rising edges of the two input signals is T in1 = 9.8 Q .Therefore, m 1 = [(9.8Q )/(2 Q )] = 4 and the output of the digital counter is '100'.As a result, T FS1 = 10 Q , and the interpolation capacitor is discharged in 5 cycles of CLKD.The voltage of the C in is proportional to 0.2 Q (V res1 ) which is a negative voltage value and is a complementary voltage residue.Thus, the interpolation capacitor is charged for 2 Q which produces the main voltage residue.Thus, the main time residue is T res1 = 2 Q -0.2 Q = 1.8 Q , and the voltage of C in is proportional to 1.8 Q (V mvr1 ).The time residue is amplified by a 4×PM (4 1.8 Q = 7.2 Q ) and fed to the second step.
Step 2: In the same way, T in2 = 7.2 Q and m 2 = [(7.2Q )/(2 Q )] = 3.Thus, the digital output code for the second step is '011'.According to (9), T FS2 = 8 Q and C in is discharged in 4 cycles of CLKD.Therefore, complementary voltage residue is proportional to 8 Q (V res2 ).Therefore, the interpolation capacitor is charged for 2 Q and the main voltage residue is produced (V mvr2 ).The time residue (T res2 = 1.2 Q ) is amplified by a 4×PM (4 1.2 Q = 4.8 Q ) and fed to the third step.Similar to the two previous steps, step 3 and step 4 are described as the following: Step 3: and the digital output code for the third stage is '010'.Also, T FS3 = 6 Q , (V res3 ) and the main voltage residue is (V mvr3 ).The time residue is T res3 = 0.8 Q and 4×PM output is (4 0.8 Q = 3.2 Q ) which is fed to the last stage.
Step 4: and the digital output code for the third stage is '001'.Also, T FS4 = 4 Q , (V res4 ) and the main voltage residue is (V mvr4 ).The time residue is T res4 = 1.2 Q and 4×PM output is In each step, the digital output code is saved by a register.Finally, the four generated digital output codes are combined in the digital error correction logic which produces the nal 9-bit output.This operation is calculated as: As shown in Fig. 10, the generated output digital code obtained from the digital error correction logic in the proposed converter is a correct digital output code.

Simulation Results
In this section, the simulation results of the proposed 9-bit cyclic TDC are investigated.The simulation is performed in TSMC 45 nm CMOS technology.Figure 11 shows the layout prototype of the cyclic converter, where the active area is 825 μm 2 .In this section, a case (T in = 9.8 Q ) for simulation results of the converter is presented.Simulation is implemented by the following elements: an input capacitor (C in = 15 pF), and a constant current source (I ref = 40 mA).To evaluate the proposed TDC operation, Q = 35 ps is used which is equal with a buffer delay in this technology.The digital output codes of the four steps in the cyclic TDC are '100', '011', '010' and '001', respectively gathered in the digital error correction logic and producing a nal 9-bit digital output code ('100111001').In this case, T in = 9.8 Q = 343 ps.Thus, the voltage of C in in step 1 is 915 mV. Figure 12 shows the voltage waveforms of C in for the four steps of the proposed cyclic TDC.As shown in Fig. 12, the voltages of C in in steps 2, 3, and 4 are 672 mV, 448 mV and 300 mV, respectively.Also, Figure 13 shows the voltage waveform of C in in the four steps of the proposed 9-bit cyclic TDC.In the analog interpolator circuit, C in is discharged periodically by I ref in 2 Q periods.The complementary voltage residue of step 1 is -18.7 mV.Moreover, the complementary voltage residues of steps 2, 3, and 4 are -75.7 mV, -112 mV and -74.6 mV, respectively and are proved by (4)(5)(6)(7)(8)(9).Therefore, the main voltage residue of step 1 is 167.2 mV.Also, the main voltages residue of steps 2 and 3 are 111.9mV and 74.6 mV, respectively.For each step, the output of comparator 2 are amplified by a 4×PM and fed to the next step.Figure 14 shows the output waveforms of the PMs.For this case, the post-layout simulation of the proposed cyclic TDC is shown in Fig. 15.Also, a Monte-Carlo simulation which shows the effect of transistor mismatch is shown in Fig. 16.Comparison of the theoretical and simulation results confirms our TDC operation.The proposed cyclic TDC achieves time resolution of 0.273 ps at a conversion rate of 300 MS/s.A ramp input is applied to measuring the time output, the differential nonlinearity (DNL), and the integral nonlinearity (INL) of the proposed converter in the linearity performance of the corresponding region shown in Fig. 17.As shown in this figure, the cumulative digital output code count with 512 samples is used so that the accuracy of the proposed TDC improves.1 LSB, respectively.The simulated TDC achieves an input dynamic range (DR) of 360 ps and a time resolution of (2 Q /(4×4×4×4) = 0.273 ps).Also, the total power consumption of the cyclic TDC is 470 μW which shows improvement in comparison with the previous cyclic TDC [13], [20].Step 1 Step 2 Step 3 Step 4  Step 1 Step 2 Step 3 Step 4     The performance of the proposed cyclic TDC is summarized in Tab. 1 with the previously reported highresolution TDCs.The results confirm the performance of our TDC.Compared with previous works, the proposed cyclic TDC improves circuit complexity, resolution, dynamic range, and chip area.

Conclusion
In this study, a novel approach for cyclic TDC is presented which employs interpolation and time amplification techniques for digitizing the time interval between two input signals.The proposed 9-bit cyclic TDC has a simple circuit architecture and does not use delay lines and VDLs in its structure.Therefore, it has a low sensitivity to PVT variations.The proposed TDC uses cyclic, analog interpolation, and two-step structures.Thus, this converter improves time resolution and accuracy.In fact, the analog interpolation is performed based on a triple-slope conversion.Also, the dynamic range of the proposed converter is lower than the TDCs previously proposed.In this converter, the linear range of the converter is increased without extra elements.In addition, the active chip area and the power consumption of the proposed TDC are reduced due to employing a cyclic and triple-slope interpolation structures.Reducing the INL and DNL errors is another advantage of this converter.The theoretical and simulation results confirm the merits of this TDC operation.Shahid Chamran University of Ahvaz, Ahvaz, Iran.He has worked in data converter field.
Ebrahim FARSHIDI was born in Shoshtar, Khozestan.He received his Ph.D. degree in Electronic Engineering from Isfahan University of Technology in 2007, and is presently an Associate Professor in Electronic Engineering in Shahid Chamran University of Ahvaz, Ahvaz, Iran.He has worked in data converter and digital electronic field.

Fig. 7 .
Fig. 7.The equivalent circuit for discharging input capacitor and generating complementary voltage residue step.

Fig. 8 .
Fig. 8.The equivalent circuit for charging interpolation capacitor and generating main voltage and main time residue step.

Fig. 10 .
Fig. 10.Operation of the digital error correction logic.

Figures 18 and 19
Figures 18 and 19 show DNL and INL of the converter in the linearity performance of the corresponding region, respectively.It can be seen that the measured INL and DNL of the converter are +1.1/-0.8LSB and +1.15/-1.1 LSB, respectively.The simulated TDC achieves an input dynamic range (DR) of 360 ps and a time resolution of (2 Q /(4×4×4×4) = 0.273 ps).Also, the total power consumption of the cyclic TDC is 470 μW which shows improvement in comparison with the previous cyclic TDC[13],[20].

Fig. 11 .
Fig. 11.The layout prototype of the proposed cyclic TDC.

Fig. 13 .
Fig. 13.The voltage waveform of C in in a period of conversion.

Fig. 17 .
Fig. 17.Output code of the proposed TDC with ramp input.