A Memristor as Multi-bit Memory: Feasibility Analysis

The use of emerging memristor materials for advanced electrical devices such as multi-valued logic is expected to outperform today's binary logic digital technologies. We show here an example for such non-binary device with the design of a multi-bit memory. While conventional memory cells can store only 1 bit, memristor-based multi-bit cells can store more information within single device thus increasing the information storage density. Such devices can potentially utilize the non-linear resistance of memristor materials for efficient information storage. We analyze the performance of such memory devices based on their expected variations in order to determine the viability of memristor-based multi-bit memory. A design of read/write scheme and a simple model for this cell lay grounds for full integration of memristor multi-bit memory cell.


Introduction
The quest for yet higher performance, energetic efficiency and market growth for information storage pushes the boundaries of existing complementary metal oxide semiconductor (CMOS) technology to its physical limits [1], [2].The predicted end of roadmap for CMOS set grounds for other candidate technologies that are expected to emerge.The fundamental studies of material physics overlap with this emerging field of beyond-CMOS technologies, where novel paradigms are set for providing new concepts and materials for the foundation of nano-electronics technology beyond the era of silicon.Among such emerging technologies are materials that feature a nonlinear resistance trace that can also be "programmed" to store their resistive state.These materials are known as memristors, and their existence was predicted by Leon Chua in 1971 [3], and they were further analyzed theoretically by Sung Mo Kang [4].Memristor devices were fabri-cated by HP labs for the first time [5].Since 2008, this type of devices has sparked vast interest in the scientific community.Memristive devices hold a strong promise for producing low voltage ReRAM memories [7], [8], [9] since they require low power and can be easily integrated within standard fabrication process.However, some challenges remain for the advancement of viable memristor-based technologies, including the architecture of memristor arrays [7], [10].
One important and promising application of these technologies is the realization of multi-bit random access memory [11][12][13][14][15][16][17].Inspired by the success of multi-bit flash memory, that proved to be highly efficient in high memory density, there have been several recent attempts to fabricate such multi-bit cells with memristors [18][19][20][21][22][23][24].The main questions remaining for understanding the potential of memristors are their physical limitations and reliability in storing information, and how many bits per cell can be stored?
Herein, we develop a methodology to analyze the upper bound of information density of memristor multi-bit cells (MBC).Based on the TiO 2 prototypical system we consider variations in electron mobility, process related physical dimensions, concentration and diffusion coefficient of oxygen vacancy.These variations are taken into account for estimating the overall uncertainty in the expected resistivity response of a memristor memory cell and therefore can be mapped into a general form of noise level restricting the number of resistance values to be used for representing information stored in the device.Achieving an understanding of the potential and limitations of such multi-valued memories is imminent for the advancement of memristor technologies.
The physical mechanism on which memristive materials such as TiO 2 and other metal oxides change their resistivity is yet fully understood.The most common model for this phenomenon is related to the diffusion of oxygen vacancies in response to electron current flow, enabling the resistivity non-linearities of the material.Throughout this work we use the Pickett's model [25] that is considered as the reference model for memristors [26].

Basic Concept
A realization of the redox memristor as an analog memory cell, can be achieved by mapping the continuously varying resistance of the memristor material into more than two resistance states, thus defining the multi-bit nature of the memory.For example, a 2 bit memory will introduce 4 states, i.e. the first state is the Low Resistance State (LRS) (see Fig. 1(d)) and 2 more intermediate states are defined between the LRS and High Resistance State (HRS).However, there are remaining challenges for quantizing the resistance of the memristor into discrete states at standard conditions.Deviations from the programmed resistance value are expected mostly due to temperature effects [27].An ensemble of memristor devices is expected to produce even higher level of variations due to uncertainty in device critical dimensions and due to other small variations between (presumably identical) devices.The resistance space is then divided into discrete values for representing the stored data (i.e.information bits), each value has its own noise margins.The noise margin indicates the uncertainty in resistance signal i.e., the values of which cannot be associated with stored information.
One should note that while the span of a memristor's resistance typically covers the values 10 2 Ω ≤ R ≤ 10 5 Ω, it is challenging to use the full range of resistance values.Since the typical operating voltage and currents for programming memristors are 1-3 V and 100 A [5], the resistivity values are limited to smaller than 10 4 Ω.Another aspect of the resistance range is related to the read/write (R/W) speed of devices with varying resistivity (mediated by their RC) and retention time [28].Yet, an advantage of the discrete levels method is that a memristor can be treated as digital entity and consequently all noises can easily be corrected, even under process variations that cause for device mismatch, or if exist, memristor programming mismatch.

Interfacing the Memory Cell
As the main requirement from such memory cells is the ability to read and write stored information, herein we discuss a simple mechanism for interfacing the memristor multi-bit memory (see Fig. 2), taking into account the physical mechanism of such memristor devices.The presented R/W mechanism shows feasibility of the discretization concept of a memristors, taking into account the noise margins and thereby bit density per cell and constitutes a foundation for such technology, as shown in the next section.
Reading process: Interfacing memristors requires the use of analog to digital conversion (ADC).A possible implementation of such conversion is illustrated schematically in Fig. 2. Here, a current source drives a memristor  and a reference current is input into a known reference resistance.The two voltages can be converted into frequency and then the pulse trains can be counted and divided resulting in a digital number, as was reported in detail in ref [29][30][31].
Writing process: In general, there are two ways to program a memristor for multi valued resistivity: 1. Reading the memristor value prior to its programming.
2. Reset the memristor before writing to its initial state.
The first option is slower since it requires reading the value of the memristor.In addition, it requires having more than one writing current (at least 8 different currents), since moving the resistance is typically non-symmetric in respect to the two directions.In this paper our analysis assumes the second approach with one current for programming.We thus consider this option as the worst-case scenario for noise margin.

Memristor Noise Margin (MNM)
In principle, one could define an infinite number of resistance states in an ideal device.However, as the number of resistance states increases, the relative noise and errors in the read/write process increase accordingly.Here we ask: what is the maximum number of such discrete states that would still allow a correct operation of the memory device.It is therefore essential to define the noise margins.
The development of the memristor predictive physical model is not yet available for memristor devices except to the regression model of reference [5].We analyze the expected noise margin that can be fitted to empirical data, using this model.Furthermore, the analysis we performed using the nonlinear resistance model is general, and can be easily applied to other models.The nonlinear resistance we use: (1) where f on , f off, i on , i off , a on , a off , b and w c are empirical parameters deduced from the regression [5].
We analyze the transformation of the depletion region area to resistance with the linear and non-linear model [6].Both known models are shown.The non-linear model, shown in (2) and the linear model in (3) are given below.The linear resistance model was slightly modified in order to take account for the device depletion region at all resistance values.Equation (3) represents the modified linear model.
, ln( )   where R on and R off are the resistance minimum and maximum values, w on and w off is the depletion layer widths, and w is the updated position of the depletion layer.
Using the nonlinear model, we derive the margins for a general variable p i : where p 1 = a on (or a off ), p 2 = i on (or i off ), p 3 = f on (or f off ). dw(t)/dt is given in (1) and can be evaluated numerically.The maximum resistance variation is therefore: A direct expression for w is inaccessible; however, an implicit dependence of the highest possible variation of the resistivity on the set of parameters {p} is obtained via estimation of their time period [5].We, therefore, derive dR/dp as a function of time and remove the time dependence by taking the highest possible variation for all variables {p} as: In ( 6) we calculate the allowed resistance variations dR considering the worst case scenario.Equation ( 6) accounts for the resistance variations within one discretized resistance level and thus does not account for the accumulated error (since the error produced by a specific parameter is directional).Therefore, the more general expression for the overall noise margins is provided with (7) below: where max(p i ) will be the maximum total reversed error (or in our case the parameter b).Equation ( 7) states that the allowed resistance variations, dR allowed , depend on the resistance variations of neighboring resistance levels, dR n , dR n -1 .

Simulation Results -MNM Analysis
In order to perform the MNM analysis, we assumed variations of the HP memristor model, with parameter values, shown in Tab. 1 [5] additionally to the reported barrier width change (1 nm -2 nm).Equation ( 1) was solved using a high-order finite difference expansion of w on a uniform grid of time-step Δt.This method is well suited for numerically solving differential equations on regular grids.[32][33] The smoothness of the numerical results was achieved by convergence of the order of the expansion.In this scheme, the value of the function derivative at some grid point is calculated based on the value of this function on neighboring grid points.Specifically for this work we used an initial condition to the solution, from which we derived the solution on the time grid at third-order expansion.At grid points close to the grid boundary we used a lower order.w was solved for an applied current pulse of a half sinusoidal waveform at frequency of 2 MHz (see Fig. 4).By keeping the time period of the current pulse constant and varying its amplitude, we search for a current amplitude which will change the resistance to the lowest distinguishable value in the range of kΩ (see Fig. 3(a) and (b)).This scheme is designed to provide highest possible resistance steps with minimum noise margins.Since the resistance curves are asymmetric, the transition from LRS to HRS is more gradual than the transition from HRS to LRS.We found that such desirable gradual transition can be achieved by amplitude of 2.3 mA, providing the steps shown in Fig. 3 below.This can also be seen in Fig. 4 where we used a range of current amplitudes and calculated their corresponding steady state resistance values.
In order to simulate the margins, we used a base resistance of 100 Ω and a R off /R on ratio of 500 and evaluated the parameters variation, dR.The noise margins corresponding to the parameters of ( 1) are evaluated based on the resistance steps of Fig. 3. (The resistance values of the steps are 100 Ω, 986 Ω, 1521 Ω, 1952 Ω corresponding to w = 1 nm, 1.368 nm, 1.438 nm, 1.478 nm, respectively).
While this analysis is in principle mathematically correct, it can be improved by casting physical arguments to some of the parameters in use.One can note that the variations listed in Tab. 2 and 3 are large and in principle they should indicate that multi-bit memory applications are infeasible.However, we argue here that the activation energy for oxygen vacancy diffusion should remain independent and we therefore assume that errors associated with the parameter i off can be ignored as it assumed to be constant.Furthermore, the parameter w c can be regarded as normalizing constant in of its large contribution to the overall resistance variation.Moreover, it shows a constant variation in relation to the initial conditions of the depletion area.

Conclusions and Discussion
This work provides a method for evaluating the noise margins of memristor-based memory devices.Using this method we performed a numerical analysis of multi-bit memristor.This analysis evaluates the noise margins associated with physical variations of devices.We find that the linear model predicts larger resistance variations compared to the nonlinear model.However, even with the larger variations of the linear model we find the multi-bit memory feasible.

Fig. 1 .
Fig. 1.Resistance field of the memristor.Blue color represents the depletion layer (oxygen vacancies shown as positive atoms).

Fig. 2 .
Fig. 2. Possible implementation of an interface for reading memristor device using ADC.

4 Tab. 1 .
Variablea off [nm] f off [m/s] i off [A] b [A] w C [pm]Parameters values that were used for the case of for i > 0.
Prof. Fish serves as an Editor in Chief for the MDPI Journal of Low Power Electronics and Applications (JLPEA) and as an Associate Editor for the IEEE Sensors, IEEE Access, Elsevier Microelectronics and Integration, the VLSI Journals.He also served as a chair of different tracks of various IEEE conferences.He was a co-organizer of many special sessions at IEEE conferences, including IEEE ISCAS, IEEE Sensors and IEEEI conferences.Prof. Fish is a member of Sensors, VLSI Systems and Applications and Bio-medical Systems Technical Committees of IEEE Circuits and Systems Society.Doron NAVEH received the B.Sc. degrees in Physics and Materials Science from Ben-Gurion University, Israel, in 2001.He completed his M.Sc.studies in Physics in 2003 at Ben-Gurion University and obtained his Ph.D. degree from Weizmann Institute of Science, Israel, in 2009.He was a postdoctoral fellow in the Department of Mechanical and Aerospace Engineering at Princeton University in 2008-2009 and in the Department of Electrical and Computer Engineering at Carnegie Mellon University 2009-2012.In 2012 he joined the Bar-Ilan University in Israel, as a faculty member in the Electrical and Computer Engineering Department.There he founded the laboratory for nanoelectronic devices, specializing in devices produced from 2D materials.
Israel.The M.Sc.thesis focused on emerging technologies such as integrated photonic devices, and implementation of memristor based multi-bit memories under the supervision of Prof. Alexander Fish and Dr. Doron Naveh.He is currently (2015) a Ph.D. student of Electrical Engineering at the Emerging Nanoscaled Integrated Circuits and Systems (ENICS) Lab at Bar Ilan University, under the supervision of Dr.Joseph Shor and focusing on area of efficient and power grid Analog Design.His research interests additionally to analog design include memristors and image sensors.Alexander FISH received the B.Sc. degree in Electrical Engineering from the Technion, Israel Institute of Technology, Haifa, Israel, in 1999.He completed his M.Sc. in 2002 and his Ph.D. (summa cum laude) in 2006, respec-tively, at Ben-Gurion University in Israel.He was a postdoctoral fellow in the ATIPS laboratory at the University of Calgary (Canada) from 2006-2008.In 2008 he joined the Ben-Gurion University in Israel, as a faculty member in the Electrical and Computer Engineering Department.There he founded the Low Power Circuits and Systems (LPC&S) laboratory, specializing in low power circuits and systems.In July 2011 he was appointed as a head of the VLSI Systems Center at BGU.In October 2012 Prof. Fish joined the Bar-Ilan University, Faculty of Engineering as an Associate Professor and the head of the nanoelectronics track.Prof. Fish also leads new Emerging Nanoscaled Integrated Circuits and Systems (ENICS) Labs.Prof. Fish's research interests include development of secured hardware, ultra-low power embedded memory arrays, CMOS image sensors and high speed and energy efficient design techniques.He has authored over 100 scientific papers in journals and conferences, including IEEE Journal of Solid State Circuits, IEEE Transactions on Electron Devices, IEEE Transactions on Circuits and Systems and many others.He also submitted 22 patent applications.Prof. Fish has published two book chapters.He was a co-author of papers that won the Best Paper Finalist awards at IEEE ISCAS and ICECS conferences.