Enhanced Model of Nonlinear Spiral High Voltage Divider

This paper deals with the enhanced accurate DC and RF model of nonlinear spiral polysilicon voltage divider. The high resistance polysilicon divider is a sensing part of the high voltage start-up MOSFET transistor that can operate up to 700 V. This paper presents the structure of a proposed model, implemented voltage, frequency and temperature dependency, and scalability. A special attention is paid to the ability of the created model to cover the mismatch and influence of a variation of process parameters on the device characteristics. Finally, the comparison of measured data vs. simulation is presented in order to confirm the model validity and a typical application is demonstrated.


Introduction
Nowadays, the power consumption is one of the most important integrated circuit parameters.High voltage power start-up MOSFET transistor described in this paper is used to minimize the power consumption [1,2].It is designed to provide initial current directly from the high voltage source.This MOSFET transistor charges up the regulator voltage on an external capacitor to about 14 V.The main goal is to minimize power consumption of the circuit that is directly connected to the rectified DC high voltage source.This high voltage can be up to 400 V for a 230 V AC supply and 700 V for switcher applications using power factor correction.
The HV start-up MOSFET is fabricated in an analog 1 µm CMOS technology.The simplified structure of this MOSFET is depicted in Fig. 2. The source and drain are formed from a low-doped Nwell and are contacted by N+ diffusion.The drain drift area contains a floating P doped resurf diffusion (ptop) fabricated before field oxide.The MOSFET channel is created from Pwell not isolated from the P-substrate and it is covered by polysilicon gate.This drain-gate-source structure is rotary symmetrical around vertical axis in the center of the drain.It means that the drain is created in the shape of a circle and the gate and the source in the shape of an annulus.
The drain is located in the center of the device and contains rounded bonding pad.A drain bonding wire is connected directly to this bonding pad and this is only one possible way how the drain can be connected.The oxide breakdown is much lower (about 100 V) than maximum allowed drain voltage.The drain can be biased up to 700 V and this makes integrated direct sensing of the high drain voltage impossible.Hence, the high resistance polysilicon spiral voltage divider is used for sensing of high drain voltage.The spiral is connected to the drain and continues spirally toward the gate.How the polysilicon spiral divider is connected to other device components is depicted in the schematic symbol of HV MOSFET in the Fig. 1 (terminals d, tap1, tap2).The spiral divider is designed to have the electric field distribution as much similar as possible as the drain drift area under it.This ensures the voltage between divider and silicon does not exceed oxide breakdown voltage.The polysilicon spiral divider has a big impact on a distribution of electric field in low doped drain drift area.And on the contrary, the strong electric field in low doped drain drift area causes a lot of parasitic effects that have a big influence on DC and RF device characteristics.These attributes make the modeling of this start-up MOSFET complicated, especially the divider ratio voltage and frequency dependency.The divider is usually modeled by the simple RC network, but there exist the operation areas where such simple model is not sufficient.

Spiral Divider Modeling
For the purpose of the equivalent lumped element circuit creation the polysilicon spiral is divided into several separate spiral elements.This division is shown in Fig. 3(a) where each spiral element has a different color.For better lucidity only the first four turns are depicted in this figure.The equivalent 3D circuit in Fig. 3(b) is obtained if these spiral elements are uncoiled to parallel plains.The 3D equivalent circuit in Fig. 3(b) can be redrawn for better lucidity to the 2D equivalent circuit, which is depicted in Fig. 4.

Spiral Element Length
The spiral divider of the HV MOSFET transistor is a special case of the Archimedes spiral [3].The radius r of the spiral is increased in one turn by a radius increment ∆r.The basic equation defined in polar coordinates for the radius is where r 0 is an initial radius of the spiral and ϕ is an actual angle circumscribed by the spiral.The curve length can be calculated in the following way.If f (φ) is the function of the curve in polar coordinates (φ is an angle) then the length L of the curve is defined as For the spiral defined in polar coordinates by (1) the spiral length L is obtained by substituting the equation ( 1) into ( 2), and by solving this integral the spiral length is When ∆r << r 0 then equation ( 3) can be simplified to

Divider Ratio Modeling
Model of a similar device has been published in [4] but without ratio scalability and statistical modeling.These two important model abilities have been developed and implemented into the new model that is introduced in this paper.The divider ratio is dependent on the drain and source voltage V D and V S .The voltage dependency caused by depletion effects in the ptop and nwell layers is modeled by Verilog-A code using nonlinear functions.The increasing of the drain voltage causes the depletion of the ptop and nwell and when the ptop is fully depleted under the spiral polysilicon divider then it causes a change of the ratio voltage dependency slope as is depicted in Fig. 5.The geometrical ratio is based on (4) and can be expressed as where ϕ D , ϕ tap1 and ϕ tap2 are drain, tap1 and tap2 angles on the spiral, L 1 and L 2 are long and sensing part of the spiral.
The normalized ratio is modeled as where ratio el is electrical ratio, β D1 , β D2 and β S are drain and source voltage dependency model parameters, V D , V S and V tap2 are voltages on pins drain, source and tap2, and V P is ptop pinch-off voltage.The voltage dependency coefficient β D2 is temperature dependent and can be expressed as where meas.@ Vs = 0 V sim.@ Vs = 0 V meas.@ Vs = 5 V sim.@ Vs = 5 V meas.@ Vs = 10 V sim.@ Vs = 10 V meas.@ Vs = 15 V sim.@ Vs = 15 V meas.@ Vs = 20 V sim.@ Vs = 20 V Fig. 5. Drain and source voltage dependency of normalized ratio.
The model is scalable by an editable model argument ratio geom that is refined to ratio geom = ratio mult ratio geom − ratio ∆ δ ratio (8) where ratio mult and ratio ∆ are model fitting parameters for ratio scalability and δ ratio is relative statistical mismatch model parameter.

Divider Dynamical Modeling
The AC response is modeled by a distributed RC network.The magnitude and phase of the normalized ratio are depicted in Figs. 6 and 7.The AC measurement setup is described in Appendix.The full macromodel circuit of HV start-up MOSFET is shown in Fig. 12.
The high resistance polysilicon spiral segments are modeled by the Verilog-A code.Each resistor segment is modeled as where N seg is number of divider segments (excluding sense segment), R tot is total spiral divider resistance and is calculated as where R SH is polysilicon spiral sheet resistance, L tot is a total spiral divider length, ∆ T = T − T nom , W is spiral segment width, δ W is absolute statistical process model parameter, α p1 and α p2 are temperature coefficients dependent on R SH where α rsh1 , α rsh2 , α rp1 , and α rp2 are polysilicon temperature coefficients.The resistance of the sense segment is The capacitances are modeled by the Verilog-A code and are voltage dependent similarly as resistances.The voltage dependency is caused by depleting effects of very low doped drift drain area due to the high electric field.Each capacitor segment is modeled [4] as where c P is the pinch-off capacitance coefficient model parameter and C tot is total spiral divider capacitance and is calculated as where C pa is polysilicon (field oxide) capacitance per unit area, C f r is fringe capacitance per length and C c is capacitance model fitting parameter.

Divider Statistical Modeling
This HV start-up MOSFET was placed on process control monitoring test chip where this device is measured on each fabricated wafer in a standard production.Data from this test chip are used for statistical process control and also for statistical modeling.
The mismatch modeling [5], [6] is implemented only to the divider ratio.The parameter δ ratio is relative statistical mismatch model parameter and is defined as where σ ratio is relative standard deviation of the divider ratio and VAR MATCH RAT IO is random variable of mean 0 and standard deviation 1 that represents the normalized Gaussian distribution for modeling the stochastic variations.The histogram of measured and simulated voltage V tap2 and box plot are depicted in Figs. 8 and 9 (one lot typically contains from 20 to 30 wafers and one wafer typically contains 5 test chips).The number of measured devices was 3825.
The standard deviation σ ratio is equal to the standard deviation of measured electrical parameter The influence of process parameters variation on the device parameters is implemented through master variables by using mapping equations: where R SH nominal , δ W nominal , C pa nominal and C f r nominal are nominal values, σ RSH , σ DW , σ CPA and σ CFR are the standard deviations, and VAR RSH , VAR DW , VAR CPA and VAR CFR are master random variables of mean 0 and standard deviation 1 that represents the normalized Gaussian distribution for modeling the stochastic variations.
As an example, the histogram of measured and simulated electrical process parameter DW is depicted in Fig. 10 and the box plot in Fig. 11.The number of measured devices was 29257.The standard deviations of device parameters σ RSH , σ DW , σ CPA and σ CFR can be calculated from the standard deviations of these measured electrical process parameters by using forward and backward propagation of variances [7].

HV Start-Up MOSFET Application
The AC/DC convertor has been selected as an example of typical application of HV start-up MOSFET with polysilicon spiral divider.The simplified AC/DC convertor circuit is depicted in Fig. 13.The HV start-up MOSFET subblock is modeled by the circuit in Fig. 12 and by the equations introduced in this paper.

Fig. 10 .Fig. 11 .
Fig. 10.The histogram of measured and simulated electrical process parameter DW .The red curve represents modeled Gaussian distribution.

Fig. 12 .
Fig. 12.The full macromodel circuit of HV start-up MOSFET with polysilicon spiral divider.Fig. 13.The simplified circuit of AC/DC convertor.The HV start-up MOSFET subblock is modeled by the circuit in Fig. 12.
is temperature, model parameter β D2T nom represents value of β D2 at nominal temperature T nom and α D is temperature coefficient.
About the Authors . ..Jan DIV ÍN was born in Valašské Meziříčí, Czech Republic, in 1986.He works as characterization engineer of the ON Semiconductor company.He is a post gradual student of Czech Technical University in Prague at the Department of Radio Engineering.He has a M.Sc. in Electronics and Communication from the Brno University of Technology.His Ph.D. study is devoted to characterization of new model types of radio-frequency semiconductor devices.Karel PT Á ČEK received his M.Sc.degree in Electrical Engineering from the Brno University of Technology, Czech Republic, in 2003.Currently, he works as a design engineer at ON Semiconductor, Czech Republic.His research interests include designing of monolithic high voltage devices as well as their ESD protections.He works on his Ph.D. thesis with the topic of communication between galvanically isolated high voltage and low voltage parts of an integrated circuit.Josef DOBE Š received the Ph.D. degree in microelectronics at the Czech Technical University in Prague in 1986.From 1986 to 1992, he was a researcher of the TESLA Research Institute, where he performed analyses on algorithms for CMOS Technology Simulators.Currently, he works at the Department of Radio Electronics of the Czech Technical University in Prague.His research interests include the physical modeling of radio electronic circuit elements, especially RF and microwave transistors and transmission lines, creating or improving special algorithms for the circuit analysis and optimization, such as time-and frequency-domain sensitivity, poles-zeros or steady-state analyses, and creating a comprehensive CAD tool for the analysis and optimization of RF and microwave circuits.